import circt.stage.ChiselStage

object Main extends App {

val usage = """
  Usage: main [--target dir] design
"""
  if (args.isEmpty || (args.length != 1 && args.length != 3)) {
    println(usage)
  }  else {
    val options = args.length match {
      case 1 => (args(0), Array(""));
      case 3 if args(0) == "--target" => (args(2), Array("--target-dir", args(1)))
      case unknow => {
        println("Unknow option ", args(0))
        sys.exit(-1);
      }
    }
   
    ChiselStage.emitSystemVerilogFile(
     options._1 match {
      case "example" => new Example();
      case "mux4" => new Mux4();
      case "counter" => new Counter();
      case unknow => {
         println("Unknown design ", unknow)
         sys.exit(-1);
        } 
      },
      args = options._2,
      firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")
    )
  }
}