Jetbl/chisel-tuto - Change EILR5STVE3MCOXN5MKVD76O4T5KRKG2DKB5TFZVE2RT3R6XZ64CQC

initial testing

Created by DKnvySJf4xXE1ZMbLJTWwLAFszpk4pYnRY7RXm78mKr5 on July 19, 2023

EILR5STVE3MCOXN5MKVD76O4T5KRKG2DKB5TFZVE2RT3R6XZ64CQC

Dependencies

[2] XLQZZVFLCO3JI7D6HWD4B4DZRVB7OCJ6KAQ2URBBKOOJA56KY37QC

In channels

main

Change contents

File addition: xtask (d--x------)
[2.1]
File addition: src (d--x------)
[0.17]

File addition: main.rs (----------)

[0.34]

use std::{path::PathBuf, process::Command};
fn main() {
    let design = std::env::args().nth(1).expect("you should pass one arg");
    let out = PathBuf::from("testing").join("designs");
    if !out.exists() {
        std::fs::create_dir(&out).expect(format!("cannot create {} dir", out.display()).as_str());
    }
    let out = std::fs::canonicalize(out).expect("canonicalize failed");
    Command::new("/home/adiallo/.local/share/coursier/bin/mill")
        .current_dir("rtl")
        .arg("ucb_tuto")
        .args([
            "--target",
            out.display().to_string().as_str(),
            design.as_str(),
        ])
        .status()
        .expect("failed to compile the rtl");
}

File addition: Cargo.toml (----------)

[0.17]

[package]
name = "xtask"
version = "0.1.0"
edition = "2021"
# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
[dependencies]

File addition: testing (d--x------)
[2.1]
File addition: tests (d--x------)
[0.1021]

File addition: mux4.rs (----------)

[0.1040]

use chisel_tuto::get_handle;
use cxxrtl::{CxxrtlHandle, CxxrtlSignal};
use std::env;
struct Blink {
    pub handle: CxxrtlHandle,
    pub clk: CxxrtlSignal<1>,
    pub led: CxxrtlSignal<1>,
    pub counter: CxxrtlSignal<12>,
}
impl Blink {
    fn new() -> Self {
        let lib = concat!(env!("OUT_DIR"), "/Example.so");
        let handle = get_handle(lib);
        let clk = handle.get("clock").unwrap().signal();
        let led = handle.get("io_led").unwrap().signal();
        let counter = handle.get("counter").unwrap().signal();
        Self {
            handle,
            clk,
            led,
            counter,
        }
    }
    fn step(&mut self) {
        self.handle.step()
    }
}
#[test]
fn test_example() {
    let mut blink = Blink::new();
    blink.step();
    for cycle in 0..1000 {
        blink.clk.set(false);
        blink.step();
        let counter: u16 = blink.counter.get();
        assert_eq!(counter, cycle);
        blink.clk.set(true);
        blink.step();
        let counter: u16 = blink.counter.get();
        assert_eq!(counter, cycle + 1);
        let curr_led: bool = blink.led.get();
        assert_eq!(curr_led, (cycle / 128) % 2 == 1);
    }
}

File addition: src (d--x------)
[0.1021]

File addition: main.rs (----------)

[0.2289]

use std::{env, fs::File};
use chisel_tuto::get_handle;
use cxxrtl::{CxxrtlHandle, CxxrtlSignal, Vcd};
struct Blink {
    pub handle: CxxrtlHandle,
    pub clk: CxxrtlSignal<1>,
    pub led: CxxrtlSignal<1>,
    pub counter: CxxrtlSignal<12>,
}
impl Blink {
    fn new() -> Self {
        let lib = concat!(env!("OUT_DIR"), "/example.so");
        let handle = get_handle(lib);
        let clk = handle.get("clk").unwrap().signal();
        let led = handle.get("led").unwrap().signal();
        let counter = handle.get("counter").unwrap().signal();
        Self {
            handle,
            clk,
            led,
            counter,
        }
    }
    fn step(&mut self) {
        self.handle.step()
    }
}
fn main() {
    let mut blink = Blink::new();
    let mut vcd = Vcd::new();
    vcd.timescale(cxxrtl::TimescaleNumber::One, cxxrtl::TimescaleUnit::Us);
    // vcd.add_without_memories(&blink.handle);
    vcd.add(&blink.handle);
    // vcd.add_if(&blink.handle, |name, obj| {
    //     dbg!(&name);
    //     dbg!(&obj);
    //     obj.r#type == CxxrtlType::Wire
    // });
    blink.step();
    let mut prev_led = false;
    let mut vcd_file = File::create("wave.vcd").unwrap();
    vcd.sample(0);
    for cycle in 0..1000 {
        blink.clk.set(false);
        blink.step();
        vcd.sample(cycle * 2);
        blink.clk.set(true);
        blink.step();
        vcd.sample(cycle * 2 + 1);
        let _counter: u16 = blink.counter.get();
        // println!("counter {counter}");
        let curr_led = blink.led.get();
        if prev_led != curr_led {
            println!("cycle {cycle}, led {curr_led}");
            prev_led = curr_led;
            // blink.counter.set(100u16);
        }
        vcd.write(&mut vcd_file).unwrap();
    }
}

File addition: lib.rs (----------)

[0.2289]

use cxxrtl::{CxxrtlHandle, _cxxrtl_toplevel};
pub fn get_handle(lib: &str) -> CxxrtlHandle {
    unsafe {
        let lib = libloading::Library::new(&lib).unwrap();
        let func: libloading::Symbol<unsafe extern "C" fn() -> *mut _cxxrtl_toplevel> =
            lib.get(b"cxxrtl_design_create").unwrap();
        let top = func();
        std::mem::forget(lib);
        CxxrtlHandle::new(top)
    }
}

File addition: build.rs (----------)

[0.1021]

use std::env;
use std::path::{Path, PathBuf};
use std::process::Command;
struct Builder {
    include: String,
    capi: PathBuf,
}
impl Builder {
    fn new() -> Self {
        let output = Command::new("yosys-config")
            .args(&["--datdir/include"])
            .output()
            .expect("failed to get yosys include dir");
        let stdout = String::from_utf8_lossy(&output.stdout);
        let include = stdout.trim().to_string();
        let capi = Path::new(&include).join("backends/cxxrtl/cxxrtl_capi.cc");
        Self { include, capi }
    }
    fn build(&self, source: PathBuf, dest: PathBuf) {
        let cc_file = dest.with_extension("cc");
        // touch(format!("/tmp/out/{}", tmp.file_name().unwrap().to_string_lossy()).as_str());
        Command::new("yosys")
            .args(&["-p", &format!("write_cxxrtl {}", cc_file.to_string_lossy())])
            .arg(&source)
            .status()
            .expect("cargo:waring=failed generate cxxrtl code");
        Command::new("clang++")
            .args(&["-g", "-O3", "-fPIC", "-shared", "-std=c++14"])
            .arg(format!("-I{}", &self.include))
            .arg(&self.capi)
            .arg(cc_file)
            .arg("-o")
            .arg(dest)
            .status()
            .expect("cargo:warning=failed generate cxxrtl code");
    }
}
fn main() {
    let builder = Builder::new();
    let out = PathBuf::from(env::var("OUT_DIR").unwrap());
    let designs = PathBuf::from("designs");
    println!("cargo:rerun-if-changed={}", designs.display());
    for file in std::fs::read_dir(designs)
        .into_iter()
        .map(|r| r.filter_map(|f| f.ok()))
        .flatten()
    {
        if let Ok(metadata) = file.metadata() {
            if metadata.is_file() {
                let file = file.path();
                if file.extension().and_then(|ext| ext.to_str()) == Some("sv") {
                    let file_name = file.file_stem().unwrap();
                    let dest = out.join(file_name).with_extension("so");
                    let modified = metadata.modified().unwrap();
                    let dest_modified = dest.metadata().and_then(|m| m.modified());
                    let duration = dest_modified
                        .ok()
                        .and_then(|m| m.duration_since(modified).ok());
                    if !dest.exists() || duration.is_none() {
                        builder.build(file, dest);
                    }
                }
            }
        }
    }
}

File addition: Cargo.toml (----------)

[0.1021]

[package]
name = "chisel-tuto"
version = "0.1.0"
edition = "2021"
# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html
[dependencies]
cxxrtl = {path = "../../rust-cxxrtl/cxxrtl"}
libloading = "0.8"

File addition: Cargo.lock (----------)

[0.1021]

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File addition: rtl (d--x------)
[2.1]
File addition: src (d--x------)
[0.19298]
File addition: main (d--x------)
[0.19315]
File addition: scala (d--x------)
[0.19333]

File addition: Main.scala (----------)

[0.19352]

import circt.stage.ChiselStage
object Main extends App {
val usage = """
  Usage: main [--target dir] design
"""
  if (args.isEmpty || (args.length != 1 && args.length != 3)) {
    println(usage)
  }  else {
    val options = args.length match {
      case 1 => (args(0), Array(""));
      case 3 if args(0) == "--target" => (args(2), Array("--target-dir", args(1)))
      case unknow => {
        println("Unknow option ", args(0))
        sys.exit(-1);
      }
    }
   
    ChiselStage.emitSystemVerilogFile(
     options._1 match {
      case "example" => new Example();
      case unknow => {
         println("Unknown design ", unknow)
         sys.exit(-1);
        } 
      },
      args = options._2,
      firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")
    )
  }
}

File addition: Example.scala (----------)

[0.19352]

import chisel3._
import circt.stage.ChiselStage
class Example extends Module {
  val io = IO(new Bundle {
    val led = Output(Bool())
  })
  val counter  = RegInit(0.U(12.W))
	counter := counter + 1.U
  io.led := counter(7)
}

File addition: build.sc (----------)

[0.19298]

// import Mill dependency
import mill._
import mill.define.Sources
import mill.modules.Util
import scalalib._
// support BSP
import mill.bsp._
object ucb_tuto extends SbtModule { m =>
// override def forkWorkingDir = os.pwd / os.up / "testing" / "designs"
  override def millSourcePath = os.pwd
  override def scalaVersion = "2.13.8"
  override def scalacOptions = Seq(
    "-language:reflectiveCalls",
    "-deprecation",
    "-feature",
    "-Xcheckinit"
  )
  override def ivyDeps = Agg(
    ivy"org.chipsalliance::chisel:5.0.0",
  )
  override def scalacPluginIvyDeps = Agg(
    ivy"org.chipsalliance:::chisel-plugin:5.0.0",
  )
}

File addition: Cargo.toml (----------)

[2.1]

[workspace]
members = [
    "testing",
    "xtask",
]
exclude = ["rtl"]

File addition: Cargo.lock (----------)

[2.1]

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File addition: .ignore (----------)

[2.1]

.git
.DS_Store
# Added by cargo
/target
rtl/out
rtl/.metals
rtl/.bloop
testing/designs

File addition: .cargo (d--x------)
[2.1]
File addition: config.toml (----------)
[0.33203]
```
[alias]
xtask = "run --package xtask --"
```

initial testing

Dependencies

In channels

Change contents

File addition: xtask (d--x------)

File addition: src (d--x------)

File addition: main.rs (----------)

File addition: Cargo.toml (----------)

File addition: testing (d--x------)

File addition: tests (d--x------)

File addition: mux4.rs (----------)

File addition: src (d--x------)

File addition: main.rs (----------)

File addition: lib.rs (----------)

File addition: build.rs (----------)

File addition: Cargo.toml (----------)

File addition: Cargo.lock (----------)

File addition: rtl (d--x------)

File addition: src (d--x------)

File addition: main (d--x------)

File addition: scala (d--x------)

File addition: Main.scala (----------)

File addition: Example.scala (----------)

File addition: build.sc (----------)

File addition: Cargo.toml (----------)

File addition: Cargo.lock (----------)

File addition: .ignore (----------)

File addition: .cargo (d--x------)

File addition: config.toml (----------)