{"header":{"message":"Fix crashlog-symbolizer register decoder","description":null,"timestamp":"2024-06-25T19:14:44Z","authors":[{"email":"a@koz.email","name":"Alexander Koz"}]},"hash":"3COGCWJDMCTKVLO77N4RCZM5KE2VVLLFLBQKK6J4B2ZSELGHNWTAC","authors":[],"deps":{"hashes":[["3COGCWJDMCTKVLO77N4RCZM5KE2VVLLFLBQKK6J4B2ZSELGHNWTAC","Fix crashlog-symbolizer register decoder"],["AA",null],["N37SUM4JCJBPJ47YSITTXZNT3HDOA4I7J23UNY57LHJPPVEZSBZQC","Initial import (history reset)"],["LPY4GRFYWVW4SRMAFQTH6GSXQ2OZO5RV3HLBMLOBZLVPYESMU7OQC","Add symbolisation utils"],["6DKYV5SGHT5KLDWJ5YGAZMSWODVDLIRHF6B4A3BPTTL6ORZFRABAC","update cargo and other deps"],["UEVSH77MUES342YHST7RXMAGSXHZS2QMAZURGLGRCV6HK5V73CTQC","Improve sprite examples, fix metadata for docs.rs"],["L5F4RDN7GGVCZRGO6PO2D6FPVHCMMCFQEOS4GFPVVEROUFX2VT2AC","Update cargo build-script output format (#374)"],["TEZ4CSBTCOT46E6OSCBLYRWPKEHXRHL5ZGDNESKQBIUZSIBWECAAC","symbolizer: rid of sqlx, use rusqlite"]],"deps":["N37SUM4JCJBPJ47YSITTXZNT3HDOA4I7J23UNY57LHJPPVEZSBZQC","LPY4GRFYWVW4SRMAFQTH6GSXQ2OZO5RV3HLBMLOBZLVPYESMU7OQC","6DKYV5SGHT5KLDWJ5YGAZMSWODVDLIRHF6B4A3BPTTL6ORZFRABAC"],"known":["UEVSH77MUES342YHST7RXMAGSXHZS2QMAZURGLGRCV6HK5V73CTQC","L5F4RDN7GGVCZRGO6PO2D6FPVHCMMCFQEOS4GFPVVEROUFX2VT2AC","TEZ4CSBTCOT46E6OSCBLYRWPKEHXRHL5ZGDNESKQBIUZSIBWECAAC"]},"hunks":[{"Edit":{"inode":{"change":3,"pos":30793},"path":"support/addr2line/src/lib.rs","line":1,"atom":{"NewVertex":{"up_context":[{"change":3,"pos":30793}],"down_context":[{"change":3,"pos":30794}],"flag":"BLOCK","start":110,"end":147,"inode":{"change":3,"pos":30793}}},"contents":[{"Add":"#![feature(let_chains)]"},{"Add":""},{"Add":"pub mod ef;"}]}},{"Edit":{"inode":{"change":3,"pos":35967},"path":"support/addr2line/src/fmt/crashlog.rs","line":2,"atom":{"NewVertex":{"up_context":[{"change":3,"pos":35999}],"down_context":[{"change":3,"pos":35999}],"flag":"BLOCK","start":152,"end":181,"inode":{"change":3,"pos":35967}}},"contents":[{"Add":"use std::io::prelude::Write;"}]}},{"Edit":{"inode":{"change":3,"pos":35967},"path":"support/addr2line/src/fmt/crashlog.rs","line":97,"atom":{"NewVertex":{"up_context":[{"change":3,"pos":39132}],"down_context":[{"change":3,"pos":39132}],"flag":"BLOCK","start":182,"end":8776,"inode":{"change":3,"pos":35967}}},"contents":[{"Add":"}"},{"Add":""},{"Add":"// impl CrashLog {"},{"Add":"// \tpub fn new() -> Self {"},{"Add":"// \t\t//"},{"Add":"// \t\t//"},{"Add":"// \t\t//"},{"Add":"// \t}"},{"Add":"// }"},{"Add":""},{"Add":""},{"Add":"impl CrashLog {"},{"Add":"\tpub fn pretty_print_sub_title(&self, mut out: W, indent: &str, title: &str) -> std::io::Result<()> {"},{"Add":"\t\twriteln!(out, \"{indent} {title}\")"},{"Add":"\t}"},{"Add":""},{"Add":"\tfn pretty_print_head(&self, mut out: W, title: bool, indent: usize) -> std::io::Result<()> {"},{"Add":"\t\tlet indented = INDENT.repeat(indent);"},{"Add":"\t\tif title {"},{"Add":"\t\t\twrite!(out, \"{indented}Crash\")?;"},{"Add":"\t\t\tif let Some(s) = self.date.as_deref() {"},{"Add":"\t\t\t\twriteln!(out, \" at {s}\")?;"},{"Add":"\t\t\t} else {"},{"Add":"\t\t\t\twriteln!(out)?;"},{"Add":"\t\t\t}"},{"Add":"\t\t}"},{"Add":""},{"Add":"\t\tif let Some(s) = self.build.as_deref() {"},{"Add":"\t\t\twriteln!(out, \"{indented} BUILD: {s}\")?;"},{"Add":"\t\t}"},{"Add":""},{"Add":"\t\tif let Some(v) = &self.heap {"},{"Add":"\t\t\twriteln!(out, \"{indented} HEAP: {v}\")?;"},{"Add":"\t\t}"},{"Add":""},{"Add":"\t\tOk(())"},{"Add":"\t}"},{"Add":"}"},{"Add":""},{"Add":""},{"Add":"impl CrashLog> where Addr: std::cmp::Eq + std::hash::Hash + WriteReport {"},{"Add":"\tpub fn pretty_print_regs<'a, 'b, W, I>(&self,"},{"Add":"\t mut out: W,"},{"Add":"\t regs: I,"},{"Add":"\t resolved: &HashMap, Report>,"},{"Add":"\t header: &str,"},{"Add":"\t title: bool,"},{"Add":"\t indent: usize,"},{"Add":"\t funcs: bool,"},{"Add":"\t short: bool,"},{"Add":"\t ranges: bool,"},{"Add":"\t demangle: bool)"},{"Add":"\t -> std::io::Result<()>"},{"Add":"\t\twhere W: Write,"},{"Add":"\t\t I: IntoIterator"},{"Add":"\t{"},{"Add":"\t\tlet indented = INDENT.repeat(indent);"},{"Add":""},{"Add":"\t\t// title:"},{"Add":"\t\tself.pretty_print_sub_title(&mut out, &indented, header)?;"},{"Add":""},{"Add":""},{"Add":"\t\tfor (k, name) in regs {"},{"Add":"\t\t\tlet addr = &self.ptrs[k];"},{"Add":""},{"Add":"\t\t\tlet space = \" \".repeat(8 - name.len());"},{"Add":"\t\t\twrite!(out, \"{indented} {name}:{space}\")?;"},{"Add":"\t\t\taddr.default_print(&mut out, title, indent, funcs, short, ranges, demangle)?;"},{"Add":"\t\t\twrite!(out, \":\")?;"},{"Add":""},{"Add":"\t\t\tif let Some(report) = resolved.get(addr) &&"},{"Add":"\t\t\t !report.symbols.is_empty()"},{"Add":"\t\t\t{"},{"Add":"\t\t\t\twrite!(out, \"\\n\")?;"},{"Add":"\t\t\t\treport.default_print(&mut out, false, indent + 2, funcs, short, ranges, demangle)?;"},{"Add":"\t\t\t} else {"},{"Add":"\t\t\t\twrite!(out, \" ??\\n\")?;"},{"Add":"\t\t\t}"},{"Add":"\t\t}"},{"Add":"\t\tOk(())"},{"Add":"\t}"},{"Add":""},{"Add":"\t/// General-purpose registers"},{"Add":"\tpub fn pretty_print_gpr(&self,"},{"Add":"\t mut out: W,"},{"Add":"\t resolved: &HashMap, Report>,"},{"Add":"\t title: bool,"},{"Add":"\t indent: usize,"},{"Add":"\t funcs: bool,"},{"Add":"\t short: bool,"},{"Add":"\t ranges: bool,"},{"Add":"\t demangle: bool)"},{"Add":"\t -> std::io::Result<()> {"},{"Add":"\t\tlet gpr = ["},{"Add":"\t\t (\"r0\", \"0\"),"},{"Add":"\t\t (\"r1\", \"1\"),"},{"Add":"\t\t (\"r2\", \"2\"),"},{"Add":"\t\t (\"r3\", \"3\"),"},{"Add":"\t\t (\"r12\", \"12\"),"},{"Add":"\t\t (\"lr\", \"14 LR\"),"},{"Add":"\t\t (\"pc\", \"15 PC\"),"},{"Add":"\t\t];"},{"Add":"\t\tlet header = \"General-purpose registers (stack)\";"},{"Add":"\t\tself.pretty_print_regs(&mut out, gpr, resolved, header, title, indent, funcs, short, ranges, demangle)"},{"Add":""},{"Add":"\t\t// let indented = INDENT.repeat(indent);"},{"Add":""},{"Add":"\t\t// // title:"},{"Add":"\t\t// self.pretty_print_sub_title(&mut out, &indented, \"General-purpose registers (stack)\")?;"},{"Add":""},{"Add":"\t\t// for k in GPR {"},{"Add":"\t\t// \tlet addr = &self.ptrs[*k];"},{"Add":""},{"Add":"\t\t// \tlet space = \" \".repeat(8 - k.len());"},{"Add":"\t\t// \twrite!(out, \"{indented} {k}:{space}\")?;"},{"Add":"\t\t// \taddr.default_print(&mut out, title, indent, funcs, short, ranges, demangle)?;"},{"Add":"\t\t// \twrite!(out, \":\")?;"},{"Add":""},{"Add":"\t\t// \tif let Some(report) = resolved.get(addr) &&"},{"Add":"\t\t// \t !report.symbols.is_empty()"},{"Add":"\t\t// \t{"},{"Add":"\t\t// \t\twrite!(out, \"\\n\")?;"},{"Add":"\t\t// \t\treport.default_print(&mut out, false, indent + 2, funcs, short, ranges, demangle)?;"},{"Add":"\t\t// \t} else {"},{"Add":"\t\t// \t\twrite!(out, \" ??\\n\")?;"},{"Add":"\t\t// \t}"},{"Add":"\t\t// }"},{"Add":"\t\t// Ok(())"},{"Add":"\t}"},{"Add":""},{"Add":""},{"Add":"\t/// Special registers"},{"Add":"\tpub fn pretty_print_sr(&self,"},{"Add":"\t mut out: W,"},{"Add":"\t resolved: &HashMap, Report>,"},{"Add":"\t title: bool,"},{"Add":"\t indent: usize,"},{"Add":"\t funcs: bool,"},{"Add":"\t short: bool,"},{"Add":"\t ranges: bool,"},{"Add":"\t demangle: bool)"},{"Add":"\t -> std::io::Result<()>"},{"Add":"\t\twhere crate::ef::PSR: TryFrom,"},{"Add":"\t\t crate::ef::CFSR: TryFrom,"},{"Add":"\t\t crate::ef::HSFR: TryFrom"},{"Add":"\t{"},{"Add":"\t\tuse crate::ef::*;"},{"Add":""},{"Add":""},{"Add":"\t\tlet gpr = [(\"mmfar\", \"MMFAR\"), (\"bfar\", \"BFAR\"), (\"rcccsr\", \"rcccsr\")];"},{"Add":"\t\tlet header = \"Special registers\";"},{"Add":"\t\tself.pretty_print_regs(&mut out, gpr, resolved, header, title, indent, funcs, short, ranges, demangle)?;"},{"Add":""},{"Add":"\t\tlet indented = INDENT.repeat(indent);"},{"Add":""},{"Add":""},{"Add":"\t\tfn print_reg(mut out: W,"},{"Add":"\t\t reg: R,"},{"Add":"\t\t name: &str,"},{"Add":"\t\t doc: &str,"},{"Add":"\t\t indent: &str)"},{"Add":"\t\t -> std::io::Result<()> {"},{"Add":"\t\t\tif !reg.is_empty() {"},{"Add":"\t\t\t\tlet space = \" \".repeat(8 - name.len());"},{"Add":"\t\t\t\twriteln!(out, \"{indent} {space}{name}: {reg:#032b} {doc}\")?;"},{"Add":""},{"Add":"\t\t\t\tlet mut max_tag_len = 0;"},{"Add":"\t\t\t\tfor (tag, doc) in reg.tags() {"},{"Add":"\t\t\t\t\tmax_tag_len = max_tag_len.max(tag.len());"},{"Add":"\t\t\t\t\tlet doc: Vec<_> = doc.trim()"},{"Add":"\t\t\t\t\t .lines()"},{"Add":"\t\t\t\t\t .map(|s| s.trim())"},{"Add":"\t\t\t\t\t .filter(|s| !s.is_empty())"},{"Add":"\t\t\t\t\t .collect();"},{"Add":"\t\t\t\t\tlet gap = \" \".repeat(max_tag_len - tag.len());"},{"Add":"\t\t\t\t\tlet pre = format!(\"{indent} {space} {tag}\");"},{"Add":"\t\t\t\t\twrite!(out, \"{pre}\")?;"},{"Add":"\t\t\t\t\tif !doc.is_empty() {"},{"Add":"\t\t\t\t\t\twriteln!(out, \":{gap} {}\", doc.first().unwrap())?;"},{"Add":"\t\t\t\t\t\tlet space = \" \".repeat(pre.len());"},{"Add":"\t\t\t\t\t\tfor line in doc.into_iter().skip(1) {"},{"Add":"\t\t\t\t\t\t\twriteln!(out, \"{space} {gap} {line}\")?;"},{"Add":"\t\t\t\t\t\t}"},{"Add":"\t\t\t\t\t}"},{"Add":"\t\t\t\t}"},{"Add":"\t\t\t}"},{"Add":""},{"Add":"\t\t\tOk(())"},{"Add":"\t\t}"},{"Add":""},{"Add":"\t\t// PSR:"},{"Add":"\t\tif let Some(Ok(reg)) = self.ptrs.get(\"psr\").map(|a| a.value()).map(PSR::try_from) {"},{"Add":"\t\t\tlet space = \" \".repeat(8 - \"PSR\".len());"},{"Add":"\t\t\tlet doc = \"(Program Status Register)\";"},{"Add":"\t\t\twriteln!(out, \"{indented} PSR:{space} {reg:#032b} {doc}\")?;"},{"Add":"\t\t\tlet apsr = reg.apsr();"},{"Add":"\t\t\tlet ipsr = reg.ipsr();"},{"Add":"\t\t\tlet epsr = reg.epsr();"},{"Add":""},{"Add":""},{"Add":"\t\t\tprint_reg("},{"Add":"\t\t\t &mut out,"},{"Add":"\t\t\t apsr,"},{"Add":"\t\t\t \"APSR\","},{"Add":"\t\t\t \"(Application Program Status Register)\","},{"Add":"\t\t\t &indented,"},{"Add":"\t\t\t)?;"},{"Add":"\t\t\tprint_reg("},{"Add":"\t\t\t &mut out,"},{"Add":"\t\t\t ipsr,"},{"Add":"\t\t\t \"IPSR\","},{"Add":"\t\t\t \"(Interrupt Program Status Register)\","},{"Add":"\t\t\t &indented,"},{"Add":"\t\t\t)?;"},{"Add":"\t\t\tprint_reg("},{"Add":"\t\t\t &mut out,"},{"Add":"\t\t\t epsr,"},{"Add":"\t\t\t \"EPSR\","},{"Add":"\t\t\t \"(Execution Program Status Register)\","},{"Add":"\t\t\t &indented,"},{"Add":"\t\t\t)?;"},{"Add":"\t\t}"},{"Add":""},{"Add":""},{"Add":"\t\t// CFSR:"},{"Add":"\t\tif let Some(Ok(reg)) = self.ptrs.get(\"cfsr\").map(|a| a.value()).map(CFSR::try_from) {"},{"Add":"\t\t\tlet space = \" \".repeat(8 - \"CFSR\".len());"},{"Add":"\t\t\tlet doc = \"(Configurable Fault Status)\";"},{"Add":"\t\t\twriteln!(out, \"{indented} CFSR:{space} {reg:#032b} {doc}\")?;"},{"Add":"\t\t\tlet ufsr = reg.ufsr();"},{"Add":"\t\t\tlet bfsr = reg.bfsr();"},{"Add":"\t\t\tlet mmfsr = reg.mmfsr();"},{"Add":""},{"Add":""},{"Add":"\t\t\tprint_reg(&mut out, ufsr, \"UFSR\", \"(UsageFault Status Register)\", &indented)?;"},{"Add":"\t\t\tprint_reg(&mut out, bfsr, \"BFSR\", \"(BusFault Status Register)\", &indented)?;"},{"Add":"\t\t\tprint_reg("},{"Add":"\t\t\t &mut out,"},{"Add":"\t\t\t mmfsr,"},{"Add":"\t\t\t \"MMFSR\","},{"Add":"\t\t\t \"(MemManage Fault Status Register)\","},{"Add":"\t\t\t &indented,"},{"Add":"\t\t\t)?;"},{"Add":"\t\t}"},{"Add":""},{"Add":""},{"Add":"\t\t// HSFR:"},{"Add":"\t\tif let Some(Ok(reg)) = self.ptrs.get(\"hsfr\").map(|a| a.value()).map(HSFR::try_from) {"},{"Add":"\t\t\tlet doc = \"(HardFault Status Register)\";"},{"Add":"\t\t\tprint_reg(&mut out, reg, \"HSFR\", doc, &indented)?;"},{"Add":"\t\t}"},{"Add":""},{"Add":"\t\tOk(())"},{"Add":"\t}"},{"Add":""},{"Add":""},{"Add":"\tpub fn pretty_print(&self,"},{"Add":"\t mut out: W,"},{"Add":"\t resolved: &HashMap, Report>,"},{"Add":"\t title: bool,"},{"Add":"\t indent: usize,"},{"Add":"\t funcs: bool,"},{"Add":"\t short: bool,"},{"Add":"\t ranges: bool,"},{"Add":"\t demangle: bool)"},{"Add":"\t -> std::io::Result<()>"},{"Add":"\t\twhere crate::ef::PSR: TryFrom,"},{"Add":"\t\t crate::ef::CFSR: TryFrom,"},{"Add":"\t\t crate::ef::HSFR: TryFrom"},{"Add":"\t{"},{"Add":"\t\t// Header:"},{"Add":"\t\tself.pretty_print_head(&mut out, title, indent)?;"},{"Add":""},{"Add":"\t\t// Stack:"},{"Add":"\t\tself.pretty_print_gpr(&mut out, resolved, title, indent, funcs, short, ranges, demangle)?;"},{"Add":""},{"Add":"\t\t// Registers:"},{"Add":"\t\tself.pretty_print_sr(&mut out, resolved, title, indent, funcs, short, ranges, demangle)?;"},{"Add":""},{"Add":"\t\twriteln!(out)"},{"Add":"\t}"}]}},{"Replacement":{"inode":{"change":3,"pos":35967},"path":"support/addr2line/src/fmt/crashlog.rs","line":382,"ins":{"up_context":[{"change":3,"pos":39180}],"down_context":[{"change":3,"pos":39718}],"flag":"BLOCK","start":8777,"end":9157,"inode":{"change":3,"pos":35967}},"del":{"edges":[{"previous":"BLOCK","flag":"BLOCK | DELETED","from":{"change":3,"pos":39180},"to":{"change":3,"start":39180,"end":39718},"introduced_by":3}],"inode":{"change":3,"pos":35967}},"ins_contents":[{"Add":"\tfn default_print(&self,"},{"Add":"\t mut out: W,"},{"Add":"\t title: bool,"},{"Add":"\t indent: usize,"},{"Add":"\t funcs: bool,"},{"Add":"\t short: bool,"},{"Add":"\t ranges: bool,"},{"Add":"\t demangle: bool)"},{"Add":"\t -> std::io::Result<()> {"}],"del_contents":[{"Del":"\tfn default_print(&self,\n\t mut out: W,\n\t title: bool,\n\t indent: usize,\n\t funcs: bool,\n\t short: bool,\n\t ranges: bool,\n\t nice: bool)\n\t -> std::io::Result<()> {\n"}]}},{"Replacement":{"inode":{"change":3,"pos":35967},"path":"support/addr2line/src/fmt/crashlog.rs","line":416,"ins":{"up_context":[{"change":3,"pos":40328}],"down_context":[{"change":3,"pos":40402}],"flag":"BLOCK","start":9158,"end":9236,"inode":{"change":3,"pos":35967}},"del":{"edges":[{"previous":"BLOCK","flag":"BLOCK | DELETED","from":{"change":3,"pos":40328},"to":{"change":3,"start":40328,"end":40402},"introduced_by":3}],"inode":{"change":3,"pos":35967}},"ins_contents":[{"Add":"\t\t\t .default_print(&mut out, title, indent, funcs, short, ranges, demangle)?;"}],"del_contents":[{"Del":"\t\t\t .default_print(&mut out, title, indent, funcs, short, ranges, nice)?;\n"}]}},{"Replacement":{"inode":{"change":3,"pos":35967},"path":"support/addr2line/src/fmt/crashlog.rs","line":422,"ins":{"up_context":[{"change":3,"pos":40516}],"down_context":[{"change":3,"pos":40595}],"flag":"BLOCK","start":9237,"end":9320,"inode":{"change":3,"pos":35967}},"del":{"edges":[{"previous":"BLOCK","flag":"BLOCK | DELETED","from":{"change":3,"pos":40516},"to":{"change":3,"start":40516,"end":40595},"introduced_by":3}],"inode":{"change":3,"pos":35967}},"ins_contents":[{"Add":"\t\t\t\tv.default_print(&mut out, false, indent + 2, funcs, short, ranges, demangle)?;"}],"del_contents":[{"Del":"\t\t\t\tv.default_print(&mut out, false, indent + 2, funcs, short, ranges, nice)?;\n"}]}},{"FileAdd":{"meta":{"basename":"ef.rs","metadata":0},"context":[{"change":3,"pos":28817}],"contents":[{"Add":"#![allow(dead_code)]"},{"Add":"#![allow(non_snake_case)]"},{"Add":""},{"Add":"use std::collections::HashMap;"},{"Add":"use std::fmt::Binary;"},{"Add":"use std::fmt::Display;"},{"Add":"use std::fmt::Debug;"},{"Add":""},{"Add":"use crate::fmt::addr::Addr;"},{"Add":""},{"Add":""},{"Add":"/// SCB+"},{"Add":"#[derive(Debug, Clone)]"},{"Add":"pub struct ExceptionFrame {"},{"Add":"\t// General-purpose registers:"},{"Add":"\t// Low regs:"},{"Add":"\tr0: u32,"},{"Add":"\tr1: u32,"},{"Add":"\tr2: u32,"},{"Add":"\tr3: u32,"},{"Add":"\t// High regs:"},{"Add":"\tr12: u32,"},{"Add":"\t/// Link Register (r14)"},{"Add":"\tlr: Addr,"},{"Add":"\t/// Program Counter (r15)"},{"Add":"\t/// Current program address."},{"Add":"\tpc: Addr,"},{"Add":""},{"Add":"\t// Special registers:"},{"Add":"\t/// Program status register."},{"Add":"\t///"},{"Add":"\t/// The Program Status Register combines:"},{"Add":"\t/// - Application Program Status Register ([`APSR`])."},{"Add":"\t/// - Interrupt Program Status Register ([`IPSR`])."},{"Add":"\t/// - Execution Program Status Register ([`EPSR`])."},{"Add":"\tpsr: PSR,"},{"Add":""},{"Add":"\t/// Configurable Fault Status"},{"Add":"\t///"},{"Add":"\t/// combines [`ufsr`][Self::ufsr] + [`bfsr`][Self::bfsr] + [`mmfsr`][Self::mmfsr]."},{"Add":"\tcfsr: CFSR,"},{"Add":""},{"Add":"\t/// HardFault Status"},{"Add":"\thfsr: HSFR,"},{"Add":""},{"Add":"\t/// MemManage Fault Address"},{"Add":"\t///"},{"Add":"\t/// The BFAR address is associated with a precise data access BusFault."},{"Add":"\t/// _This field is valid only when [`MMFSR::MMARVALID`] is set._"},{"Add":"\tmmfar: Addr,"},{"Add":""},{"Add":"\t/// BusFault Address."},{"Add":"\t/// Data address for a precise BusFault."},{"Add":"\t///"},{"Add":"\t/// Contains the address of a location that produced a BusFault."},{"Add":"\t/// The [`BFSR`] shows the reason for the fault."},{"Add":"\t/// _This field is valid only when [`BFSR::BFARVALID`] is set._"},{"Add":"\tbfar: Addr,"},{"Add":""},{"Add":"\t/// `bootinfo.rcccsr` value"},{"Add":"\trcccsr: u32,"},{"Add":"}"},{"Add":""},{"Add":""},{"Add":"pub const SCB_CPACR_FPU_MASK: u32 = 0b11_11 << 20;"},{"Add":"pub const SCB_CPACR_FPU_ENABLE: u32 = 0b01_01 << 20;"},{"Add":"pub const SCB_CPACR_FPU_USER: u32 = 0b10_10 << 20;"},{"Add":""},{"Add":"impl ExceptionFrame {"},{"Add":"\tpub fn ufsr(&self) -> UFSR { self.cfsr.ufsr() }"},{"Add":"\tpub fn bfsr(&self) -> BFSR { self.cfsr.bfsr() }"},{"Add":"\tpub fn mmfsr(&self) -> MMFSR { self.cfsr.mmfsr() }"},{"Add":"}"},{"Add":""},{"Add":""},{"Add":"impl ExceptionFrame {"},{"Add":"\tpub fn new_from(values: &HashMap>) -> Result {"},{"Add":"\t\tOk(Self { r0: values.get(\"r0\").ok_or(\"no r0\")?.value(),"},{"Add":"\t\t r1: values.get(\"r1\").ok_or(\"no r1\")?.value(),"},{"Add":"\t\t r2: values.get(\"r2\").ok_or(\"no r2\")?.value(),"},{"Add":"\t\t r3: values.get(\"r3\").ok_or(\"no r3\")?.value(),"},{"Add":"\t\t r12: values.get(\"r12\").ok_or(\"no r12\")?.value(),"},{"Add":"\t\t lr: values.get(\"lr\").ok_or(\"no lr\")?.to_owned(),"},{"Add":"\t\t pc: values.get(\"pc\").ok_or(\"no pc\")?.to_owned(),"},{"Add":"\t\t psr: values.get(\"psr\").ok_or(\"no psr\")?.value().into(),"},{"Add":"\t\t cfsr: values.get(\"cfsr\").ok_or(\"no cfsr\")?.value().into(),"},{"Add":"\t\t hfsr: values.get(\"hfsr\").ok_or(\"no hfsr\")?.value().into(),"},{"Add":"\t\t mmfar: values.get(\"mmfar\").ok_or(\"no mmfar\")?.to_owned(),"},{"Add":"\t\t bfar: values.get(\"bfar\").ok_or(\"no bfar\")?.to_owned(),"},{"Add":"\t\t rcccsr: values.get(\"rcccsr\").ok_or(\"no rcccsr\")?.value().into() })"},{"Add":"\t}"},{"Add":"}"},{"Add":""},{"Add":""},{"Add":"macro_rules! bit {"},{"Add":"\t($mask:literal, $name:ident.$field:ident, $doc:literal) => {"},{"Add":"\t\timpl $name {"},{"Add":"\t\t\tbit! {$mask, $field, $doc}"},{"Add":"\t\t}"},{"Add":"\t};"},{"Add":"\t($mask:literal, $name:ident) => {"},{"Add":"\t\tpub fn $name(&self) -> bool { self.0 & $mask != 0 }"},{"Add":""},{"Add":"\t\tpaste::paste! {"},{"Add":"\t\t\tpub const []: &'static str = stringify!($name);"},{"Add":"\t\t}"},{"Add":"\t};"},{"Add":"\t($mask:literal, $name:ident, $doc:literal) => {"},{"Add":"\t\t#[doc = $doc]"},{"Add":"\t\tpub fn $name(&self) -> bool { self.0 & $mask != 0 }"},{"Add":""},{"Add":"\t\tpaste::paste! {"},{"Add":"\t\t\tpub const []: &'static str = $doc;"},{"Add":"\t\t}"},{"Add":"\t};"},{"Add":""},{"Add":"\t($name:ident, $mask:literal) => {"},{"Add":"\t\tbit!($mask, $name)"},{"Add":"\t};"},{"Add":"\t($name:ident, $mask:literal, $doc:literal) => {"},{"Add":"\t\tbit!($mask, $name, $doc)"},{"Add":"\t};"},{"Add":"}"},{"Add":""},{"Add":""},{"Add":"macro_rules! impl_fmt {"},{"Add":"\t\t($name:ident) => {"},{"Add":"\t\t\timpl Display for $name {"},{"Add":"\t\t\t\tfn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { Display::fmt(&self.0, f) }"},{"Add":"\t\t\t}"},{"Add":"\t\t\timpl Binary for $name {"},{"Add":"\t\t\t\tfn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { Binary::fmt(&self.0, f) }"},{"Add":"\t\t\t}"},{"Add":"\t\t};"},{"Add":""},{"Add":"\t\t($name:ident, $($next:ident),+) => {"},{"Add":"\t\t\timpl_fmt!($name);"},{"Add":" impl_fmt!($($next),+);"},{"Add":"\t\t}"},{"Add":"\t}"},{"Add":""},{"Add":""},{"Add":"macro_rules! impl_from {"},{"Add":"\t($name:ident) => {"},{"Add":"\t\timpl_from! {impl $name}"},{"Add":"\t\timpl_from! {impl $name}"},{"Add":"\t};"},{"Add":"\t($name:ident) => {"},{"Add":"\t\timpl_from! {impl $name}"},{"Add":"\t\timpl_from! {impl $name}"},{"Add":"\t\timpl_from! {$name}"},{"Add":"\t};"},{"Add":"\t($name:ident) => {"},{"Add":"\t\timpl_from! {impl $name}"},{"Add":"\t\timpl_from! {impl $name}"},{"Add":"\t\timpl_from! {$name}"},{"Add":"\t};"},{"Add":"\t($name:ident) => {"},{"Add":"\t\timpl_from! {impl $name}"},{"Add":"\t\timpl_from! {impl $name}"},{"Add":"\t\timpl_from! {$name}"},{"Add":"\t};"},{"Add":"\t($name:ident) => {"},{"Add":"\t\timpl_from! {$name}"},{"Add":"\t};"},{"Add":""},{"Add":"\t(impl $name:ident<$t:ty>) => {"},{"Add":"\t\timpl From<$t> for $name {"},{"Add":"\t\t\tfn from(value: $t) -> Self { Self(value as _) }"},{"Add":"\t\t}"},{"Add":"\t};"},{"Add":"}"},{"Add":""},{"Add":"macro_rules! impl_try_from {"},{"Add":"\t($name:ident) => {"},{"Add":"\t\timpl_try_from! {impl $name}"},{"Add":"\t\timpl_try_from! {impl $name}"},{"Add":"\t\timpl_try_from! {impl $name}"},{"Add":"\t};"},{"Add":"\t($name:ident) => {"},{"Add":"\t\timpl_try_from! {impl $name}"},{"Add":"\t\timpl_try_from! {impl $name}"},{"Add":"\t};"},{"Add":"\t($name:ident) => {"},{"Add":"\t\timpl_try_from! {impl $name}"},{"Add":"\t};"},{"Add":"\t($name:ident) => {};"},{"Add":"\t($name:ident) => {"},{"Add":"\t\timpl_try_from! {$name}"},{"Add":"\t};"},{"Add":""},{"Add":"\t(impl $name:ident<$t:ty, $th:ty>) => {"},{"Add":"\t\timpl TryFrom<$th> for $name"},{"Add":"\t\t\twhere $t: TryFrom<$th>,"},{"Add":"\t\t\t Self: From<$t>"},{"Add":"\t\t{"},{"Add":"\t\t\ttype Error = <$t as TryFrom<$th>>::Error;"},{"Add":"\t\t\tfn try_from(value: $th) -> Result {"},{"Add":"\t\t\t\tlet value: $t = value.try_into()?;"},{"Add":"\t\t\t\tOk(Self::from(value))"},{"Add":"\t\t\t}"},{"Add":"\t\t}"},{"Add":"\t};"},{"Add":"}"},{"Add":""},{"Add":"macro_rules! impl_to {"},{"Add":"\t($name:ident) => {"},{"Add":"\t\timpl_to! {impl $name}"},{"Add":"\t\timpl_to! {impl $name}"},{"Add":"\t\timpl_to! {$name}"},{"Add":"\t};"},{"Add":"\t($name:ident) => {"},{"Add":"\t\timpl_to! {impl $name}"},{"Add":"\t\timpl_to! {impl $name}"},{"Add":"\t\timpl_to! {$name}"},{"Add":"\t};"},{"Add":"\t($name:ident) => {"},{"Add":"\t\timpl_to! {impl $name}"},{"Add":"\t\timpl_to! {impl $name}"},{"Add":"\t\timpl_to! {$name}"},{"Add":"\t};"},{"Add":"\t($name:ident) => {"},{"Add":"\t\timpl_to! {impl $name}"},{"Add":"\t\timpl_to! {impl $name}"},{"Add":"\t};"},{"Add":"\t($name:ident) => {"},{"Add":"\t\timpl_to! {$name}"},{"Add":"\t};"},{"Add":""},{"Add":"\t(impl $name:ident<$t:ty>) => {"},{"Add":"\t\timpl From<$name> for $t {"},{"Add":"\t\t\tfn from(value: $name) -> Self { value.0 as _ }"},{"Add":"\t\t}"},{"Add":"\t};"},{"Add":"}"},{"Add":""},{"Add":"macro_rules! impl_convert {"},{"Add":"\t($name:ident) => {"},{"Add":"\t\timpl_to! {$name}"},{"Add":"\t\timpl_from! {$name}"},{"Add":"\t\timpl_try_from! {$name}"},{"Add":"\t};"},{"Add":"\t($name:ident) => {"},{"Add":"\t\timpl_to! {$name}"},{"Add":"\t\timpl_from! {$name}"},{"Add":"\t\timpl_try_from! {$name}"},{"Add":"\t};"},{"Add":"\t($name:ident) => {"},{"Add":"\t\timpl_to! {$name}"},{"Add":"\t\timpl_from! {$name}"},{"Add":"\t\timpl_try_from! {$name}"},{"Add":"\t};"},{"Add":"\t($name:ident) => {"},{"Add":"\t\timpl_to! {$name}"},{"Add":"\t\timpl_from! {$name}"},{"Add":"\t\timpl_try_from! {$name}"},{"Add":"\t};"},{"Add":"\t($name:ident) => {"},{"Add":"\t\timpl_convert! {$name}"},{"Add":"\t};"},{"Add":"}"},{"Add":""},{"Add":"macro_rules! impl_reg {"},{"Add":"\t\t($name:ident) => {"},{"Add":"\t\t\timpl_reg!{$name}"},{"Add":"\t\t};"},{"Add":"\t\t($name:ident<$t:ty>) => {"},{"Add":"\t\t\timpl_fmt!{$name}"},{"Add":"\t\t};"},{"Add":""},{"Add":"\t\t($name:ident$(<$t:ty>)?, $($next:ident$(<$tn:ty>)?),+) => {"},{"Add":"\t\t\timpl_reg!($name$(<$t>)?);"},{"Add":" impl_reg!($($next$(<$tn>)?),+);"},{"Add":"\t\t}"},{"Add":"\t}"},{"Add":""},{"Add":"impl_reg! {PSR, IPSR, APSR, EPSR, CFSR, UFSR, BFSR, MMFSR, HSFR}"},{"Add":"impl_convert! { PSR }"},{"Add":"impl_convert! { IPSR }"},{"Add":"impl_convert! { APSR }"},{"Add":"impl_convert! { EPSR }"},{"Add":"impl_convert! { CFSR }"},{"Add":"impl_convert! { UFSR }"},{"Add":"impl_convert! { BFSR }"},{"Add":"impl_convert! { MMFSR }"},{"Add":"impl_convert! { HSFR }"},{"Add":""},{"Add":"// _PSR entry in the crash log also includes the EPSR as well._"},{"Add":"// ESPR - Execution Program Status Register"},{"Add":"//"},{"Add":"/// Program status register."},{"Add":"///"},{"Add":"/// The Program Status Register (PSR) combines:"},{"Add":"/// - Application Program Status Register (APSR)."},{"Add":"/// - Interrupt Program Status Register (IPSR)."},{"Add":"/// - Execution Program Status Register (EPSR)."},{"Add":"#[derive(Clone, Copy, PartialEq, Eq)]"},{"Add":"pub struct PSR(u32);"},{"Add":""},{"Add":"impl PSR {"},{"Add":"\tpub fn apsr(&self) -> APSR { APSR(((self.0 & 0b11111000_00000111_00000000_00000000) >> 16) as u16) }"},{"Add":"\tpub fn ipsr(&self) -> IPSR { IPSR((self.0 & 0b00000000_00000000_00000001_11111111) as u16) }"},{"Add":"\tpub fn epsr(&self) -> EPSR { EPSR(self.0 & 0b00000111_00000000_11111100_00000000) }"},{"Add":"}"},{"Add":""},{"Add":"impl Debug for PSR {"},{"Add":"\tfn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {"},{"Add":"\t\tf.debug_struct(\"PSR\")"},{"Add":"\t\t .field(\"APSR\", &self.apsr())"},{"Add":"\t\t .field(\"IPSR\", &self.ipsr())"},{"Add":"\t\t .field(\"EPSR\", &self.epsr())"},{"Add":"\t\t .finish()"},{"Add":"\t}"},{"Add":"}"},{"Add":""},{"Add":""},{"Add":"/// Application Program Status Register."},{"Add":"#[derive(Clone, Copy, PartialEq, Eq)]"},{"Add":"pub struct APSR(u16);"},{"Add":"bit! {0b1000_0000_00000000, APSR.N, r#\"Negative\"#}"},{"Add":"bit! {0b0100_0000_00000000, APSR.Z, r#\"Zero\"#}"},{"Add":"bit! {0b0010_0000_00000000, APSR.C, r#\"Carry or borrow\"#}"},{"Add":"bit! {0b0001_0000_00000000, APSR.V, r#\"Overflow\"#}"},{"Add":"bit! {0b0000_1000_00000000, APSR.Q, r#\"DSP overflow and saturation\"#}"},{"Add":"bit! {0b0000_0000_00000111, APSR.GE, r#\"Greater than or Equals\"#}"},{"Add":"impl Debug for APSR {"},{"Add":"\tfn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {"},{"Add":"\t\tf.debug_struct(\"APSR\")"},{"Add":"\t\t .field(\"N\", &self.N())"},{"Add":"\t\t .field(\"Z\", &self.Z())"},{"Add":"\t\t .field(\"C\", &self.C())"},{"Add":"\t\t .field(\"V\", &self.V())"},{"Add":"\t\t .field(\"Q\", &self.Q())"},{"Add":"\t\t .field(\"GE\", &self.GE())"},{"Add":"\t\t .finish()"},{"Add":"\t}"},{"Add":"}"},{"Add":"impl RegTags for APSR {"},{"Add":"\tfn is_empty(&self) -> bool { self.0 == 0 }"},{"Add":""},{"Add":"\tfn tags(&self) -> impl IntoIterator {"},{"Add":"\t\tif !self.is_empty() {"},{"Add":"\t\t\t["},{"Add":"\t\t\t self.N().then_some((\"N\", Self::DOC_N)),"},{"Add":"\t\t\t self.Z().then_some((\"Z\", Self::DOC_Z)),"},{"Add":"\t\t\t self.C().then_some((\"C\", Self::DOC_C)),"},{"Add":"\t\t\t self.V().then_some((\"V\", Self::DOC_V)),"},{"Add":"\t\t\t self.Q().then_some((\"Q\", Self::DOC_Q)),"},{"Add":"\t\t\t self.GE().then_some((\"GE\", Self::DOC_GE)),"},{"Add":"\t\t\t].into_iter()"},{"Add":"\t\t\t.flatten()"},{"Add":"\t\t} else {"},{"Add":"\t\t\t<[_; 6]>::default().into_iter().flatten()"},{"Add":"\t\t}"},{"Add":"\t}"},{"Add":"}"},{"Add":""},{"Add":"/// Interrupt Program Status Register."},{"Add":"#[derive(Clone, Copy, PartialEq, Eq)]"},{"Add":"pub struct IPSR(u16);"},{"Add":"bit! {0b0000_0000_00000001, IPSR.TM, r#\"Thread mode\"#}"},{"Add":"bit! {0b0000_0000_00000100, IPSR.NMI, r#\"NMI\"#}"},{"Add":"bit! {0b0000_0000_00001000, IPSR.HF, r#\"HardFault\"#}"},{"Add":"bit! {0b0000_0000_00010000, IPSR.MM, r#\"MemManage\"#}"},{"Add":"bit! {0b0000_0000_00100000, IPSR.BF, r#\"BusFault\"#}"},{"Add":"bit! {0b0000_0000_01000000, IPSR.UF, r#\"UsageFault\"#}"},{"Add":"impl Debug for IPSR {"},{"Add":"\tfn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {"},{"Add":"\t\tf.debug_struct(\"IPSR\")"},{"Add":"\t\t .field(\"TM\", &self.TM())"},{"Add":"\t\t .field(\"NMI\", &self.NMI())"},{"Add":"\t\t .field(\"HF\", &self.HF())"},{"Add":"\t\t .field(\"MM\", &self.MM())"},{"Add":"\t\t .field(\"BF\", &self.BF())"},{"Add":"\t\t .field(\"UF\", &self.UF())"},{"Add":"\t\t .finish()"},{"Add":"\t}"},{"Add":"}"},{"Add":"impl RegTags for IPSR {"},{"Add":"\tfn is_empty(&self) -> bool { self.0 == 0 }"},{"Add":""},{"Add":"\tfn tags(&self) -> impl IntoIterator {"},{"Add":"\t\tif !self.is_empty() {"},{"Add":"\t\t\t["},{"Add":"\t\t\t self.TM().then_some((\"TM\", Self::DOC_TM)),"},{"Add":"\t\t\t self.NMI().then_some((\"NMI\", Self::DOC_NMI)),"},{"Add":"\t\t\t self.HF().then_some((\"HF\", Self::DOC_HF)),"},{"Add":"\t\t\t self.MM().then_some((\"MM\", Self::DOC_MM)),"},{"Add":"\t\t\t self.BF().then_some((\"BF\", Self::DOC_BF)),"},{"Add":"\t\t\t self.UF().then_some((\"UF\", Self::DOC_UF)),"},{"Add":"\t\t\t].into_iter()"},{"Add":"\t\t\t.flatten()"},{"Add":"\t\t} else {"},{"Add":"\t\t\t<[_; 6]>::default().into_iter().flatten()"},{"Add":"\t\t}"},{"Add":"\t}"},{"Add":"}"},{"Add":""},{"Add":"/// Execution Program Status Register."},{"Add":"#[derive(Clone, Copy, PartialEq, Eq)]"},{"Add":"pub struct EPSR(u32);"},{"Add":"bit! {0b00000110_00000000_00001100_00000000, EPSR.IS_NOT_ICI, r#\"Interruptible-continuable instruction bits.\"#}"},{"Add":"bit! {0b00000000_00000000_11110000_00000000, EPSR.ICI, r#\"Interruptible-continuable instruction bits.\"#}"},{"Add":"bit! {0b00000110_00000000_11111100_00000000, EPSR.IT, r#\"If-Then block. Indicates the execution state bits of the IT instruction\"#}"},{"Add":"bit! {0b00000001_00000000_00000000_00000000, EPSR.T, r#\"Thumb state\"#}"},{"Add":"impl Debug for EPSR {"},{"Add":"\tfn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {"},{"Add":"\t\tf.debug_struct(\"EPSR\")"},{"Add":"\t\t .field(\"IS_NOT_ICI\", &self.IS_NOT_ICI())"},{"Add":"\t\t .field(\"ICI\", &self.ICI())"},{"Add":"\t\t .field(\"IT\", &self.IT())"},{"Add":"\t\t .field(\"T\", &self.T())"},{"Add":"\t\t .finish()"},{"Add":"\t}"},{"Add":"}"},{"Add":"impl RegTags for EPSR {"},{"Add":"\tfn is_empty(&self) -> bool { self.0 == 0 }"},{"Add":""},{"Add":"\tfn tags(&self) -> impl IntoIterator {"},{"Add":"\t\tif !self.is_empty() {"},{"Add":"\t\t\t["},{"Add":"\t\t\t self.IS_NOT_ICI().then_some((\"IS_NOT_ICI\", Self::DOC_IS_NOT_ICI)),"},{"Add":"\t\t\t self.ICI().then_some((\"ICI\", Self::DOC_ICI)),"},{"Add":"\t\t\t self.IT().then_some((\"IT\", Self::DOC_IT)),"},{"Add":"\t\t\t self.T().then_some((\"T\", Self::DOC_T)),"},{"Add":"\t\t\t].into_iter()"},{"Add":"\t\t\t.flatten()"},{"Add":"\t\t} else {"},{"Add":"\t\t\t<[_; 4]>::default().into_iter().flatten()"},{"Add":"\t\t}"},{"Add":"\t}"},{"Add":"}"},{"Add":""},{"Add":""},{"Add":"/// HardFault Status Register."},{"Add":"///"},{"Add":"/// The Hard Fault status register indicates an incorrect usage of a CPU instruction."},{"Add":"#[derive(Clone, Copy, PartialEq, Eq)]"},{"Add":"pub struct HSFR(u32);"},{"Add":"impl HSFR {"},{"Add":"\t// When this bit is set, the PC value stacked for the exception return points to the instruction"},{"Add":"\t// that was preempted by the exception. This error is always a Hard Fault."},{"Add":"\tbit! {0b00000000_00000000_00000000_00000010, VECTTBL, r#\"Bus Fault on vector table read.\"#}"},{"Add":"\tbit! {0b01000000_00000000_00000000_00000000, FORCED, r#\"Forced Hard Fault.\"#}"},{"Add":"\tbit! {0b10000000_00000000_00000000_00000000, DEBUGEVT, r#\"Reserved for Debug use.\"#}"},{"Add":"}"},{"Add":"impl Debug for HSFR {"},{"Add":"\tfn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {"},{"Add":"\t\tf.debug_struct(\"HSFR\")"},{"Add":"\t\t .field(\"VECTTBL\", &self.VECTTBL())"},{"Add":"\t\t .field(\"FORCED\", &self.FORCED())"},{"Add":"\t\t .field(\"DEBUGEVT\", &self.DEBUGEVT())"},{"Add":"\t\t .finish()"},{"Add":"\t}"},{"Add":"}"},{"Add":"impl RegTags for HSFR {"},{"Add":"\tfn is_empty(&self) -> bool { self.0 == 0 }"},{"Add":""},{"Add":"\tfn tags(&self) -> impl IntoIterator {"},{"Add":"\t\tif !self.is_empty() {"},{"Add":"\t\t\t["},{"Add":"\t\t\t self.VECTTBL().then_some((\"VECTTBL\", Self::DOC_VECTTBL)),"},{"Add":"\t\t\t self.FORCED().then_some((\"FORCED\", Self::DOC_FORCED)),"},{"Add":"\t\t\t self.DEBUGEVT().then_some((\"DEBUGEVT\", Self::DOC_DEBUGEVT)),"},{"Add":"\t\t\t].into_iter()"},{"Add":"\t\t\t.flatten()"},{"Add":"\t\t} else {"},{"Add":"\t\t\t<[_; 3]>::default().into_iter().flatten()"},{"Add":"\t\t}"},{"Add":"\t}"},{"Add":"}"},{"Add":""},{"Add":""},{"Add":"/// Configurable Fault Status"},{"Add":"///"},{"Add":"/// combines [`ufsr`][Self::ufsr] + [`bfsr`][Self::bfsr] + [`mmfsr`][Self::mmfsr]."},{"Add":"#[derive(Clone, Copy, PartialEq, Eq)]"},{"Add":"pub struct CFSR(u32);"},{"Add":""},{"Add":"impl CFSR {"},{"Add":"\tpub fn ufsr(&self) -> UFSR { UFSR(((self.0 & 0b11111111_11111111_00000000_00000000) >> 16) as u16) }"},{"Add":"\tpub fn bfsr(&self) -> BFSR { BFSR(((self.0 & 0b00000000_00000000_11111111_00000000) >> 8) as u8) }"},{"Add":"\tpub fn mmfsr(&self) -> MMFSR { MMFSR(self.0 as u8) }"},{"Add":"}"},{"Add":""},{"Add":"impl Debug for CFSR {"},{"Add":"\tfn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {"},{"Add":"\t\tf.debug_struct(\"CFSR\")"},{"Add":"\t\t .field(\"UFSR\", &self.ufsr())"},{"Add":"\t\t .field(\"BFSR\", &self.bfsr())"},{"Add":"\t\t .field(\"MMFSR\", &self.mmfsr())"},{"Add":"\t\t .finish()"},{"Add":"\t}"},{"Add":"}"},{"Add":""},{"Add":""},{"Add":"/// The UsageFault Status Register contains the status for some instruction execution faults, and for data access."},{"Add":"#[derive(Clone, Copy, PartialEq, Eq)]"},{"Add":"pub struct UFSR(u16);"},{"Add":"impl UFSR {"},{"Add":"\tbit! {0b0000_0000_0000_0001, UNDEFINSTR, r#\"Undefined instruction.\"#}"},{"Add":"\tbit! {0b0000_0000_0000_0010, INVSTATE, r#\"Invalid state.\"#}"},{"Add":"\tbit! {0b0000_0000_0000_0100, INVPC, r#\"Invalid `PC` load UsageFault, caused by an invalid `EXC_RETURN` value.\"#}"},{"Add":"\tbit! {0b0000_0000_0000_1000, NOCP, r#\"No coprocessor.\"#}"},{"Add":"\tbit! {0b0000_0001_0000_0000, UNALIGNED, r#\"Unaligned access UsageFault.\"#}"},{"Add":"\tbit! {0b0010_0000, DIVBYZERO, r#\"Divide by zero UsageFault.\"#}"},{"Add":"}"},{"Add":""},{"Add":""},{"Add":"impl RegTags for UFSR {"},{"Add":"\tfn is_empty(&self) -> bool { self.0 == 0 }"},{"Add":""},{"Add":"\tfn tags(&self) -> impl IntoIterator {"},{"Add":"\t\tif self.is_empty() {"},{"Add":"\t\t\treturn [None, None, None, None, None, None].into_iter().flatten();"},{"Add":"\t\t}"},{"Add":""},{"Add":"\t\t["},{"Add":"\t\t self.UNDEFINSTR().then_some((\"UNDEFINSTR\", Self::DOC_UNDEFINSTR)),"},{"Add":"\t\t self.INVSTATE().then_some((\"INVSTATE\", Self::DOC_INVSTATE)),"},{"Add":"\t\t self.INVPC().then_some((\"INVPC\", Self::DOC_INVPC)),"},{"Add":"\t\t self.NOCP().then_some((\"NOCP\", Self::DOC_NOCP)),"},{"Add":"\t\t self.UNALIGNED().then_some((\"UNALIGNED\", Self::DOC_UNALIGNED)),"},{"Add":"\t\t self.DIVBYZERO().then_some((\"DIVBYZERO\", Self::DOC_DIVBYZERO)),"},{"Add":"\t\t].into_iter()"},{"Add":"\t\t.flatten()"},{"Add":"\t}"},{"Add":"}"},{"Add":""},{"Add":"impl Debug for UFSR {"},{"Add":"\tfn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {"},{"Add":"\t\tf.debug_struct(\"UFSR\")"},{"Add":"\t\t .field(\"UNDEFINSTR\", &self.UNDEFINSTR())"},{"Add":"\t\t .field(\"INVSTATE\", &self.INVSTATE())"},{"Add":"\t\t .field(\"INVPC\", &self.INVPC())"},{"Add":"\t\t .field(\"NOCP\", &self.NOCP())"},{"Add":"\t\t .field(\"UNALIGNED\", &self.UNALIGNED())"},{"Add":"\t\t .field(\"DIVBYZERO\", &self.DIVBYZERO())"},{"Add":"\t\t .finish()"},{"Add":"\t}"},{"Add":"}"},{"Add":""},{"Add":""},{"Add":"/// The BusFault Status Register shows the status of bus errors resulting from instruction fetches and data accesses"},{"Add":"/// and indicates memory access faults detected during a bus operation."},{"Add":"#[derive(Clone, Copy, PartialEq, Eq)]"},{"Add":"pub struct BFSR(u8);"},{"Add":"impl BFSR {"},{"Add":"\tbit! {0b0000_0001, IBUSERR, r#\"Instruction bus error. Records whether a BusFault on an instruction prefetch has occurred.\"#}"},{"Add":"\tbit! {0b0000_0010, PRECISERR, r#\"Precise data bus error.\"#}"},{"Add":"\tbit! {0b0000_0100, IMPRECISERR, r#\"Imprecise data bus error.\"#}"},{"Add":"\tbit! {0b0000_1000, UNSTKERR, r#\"BusFault on unstacking for a return from exception.\"#}"},{"Add":"\tbit! {0b0001_0000, STKERR, r#\"BusFault on stacking for exception entry.\"#}"},{"Add":"\tbit! {0b0010_0000, LSPERR, r#\"BusFault during floating point lazy state preservation (only when FPU present).\"#}"},{"Add":"\tbit! {0b1000_0000, BFARVALID, r#\"BusFault Address Register valid flag. BFAR holds a valid fault address.\"#}"},{"Add":"}"},{"Add":"impl Debug for BFSR {"},{"Add":"\tfn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {"},{"Add":"\t\tf.debug_struct(\"BFSR\")"},{"Add":"\t\t .field(\"IBUSERR\", &self.IBUSERR())"},{"Add":"\t\t .field(\"PRECISERR\", &self.PRECISERR())"},{"Add":"\t\t .field(\"IMPRECISERR\", &self.IMPRECISERR())"},{"Add":"\t\t .field(\"UNSTKERR\", &self.UNSTKERR())"},{"Add":"\t\t .field(\"STKERR\", &self.STKERR())"},{"Add":"\t\t .field(\"LSPERR\", &self.LSPERR())"},{"Add":"\t\t .field(\"BFARVALID\", &self.BFARVALID())"},{"Add":"\t\t .finish()"},{"Add":"\t}"},{"Add":"}"},{"Add":"impl RegTags for BFSR {"},{"Add":"\tfn is_empty(&self) -> bool { self.0 == 0 }"},{"Add":""},{"Add":"\tfn tags(&self) -> impl IntoIterator {"},{"Add":"\t\tif !self.is_empty() {"},{"Add":"\t\t\t["},{"Add":"\t\t\t self.IBUSERR().then_some((\"IBUSERR\", Self::DOC_IBUSERR)),"},{"Add":"\t\t\t self.PRECISERR().then_some((\"PRECISERR\", Self::DOC_PRECISERR)),"},{"Add":"\t\t\t self.IMPRECISERR()"},{"Add":"\t\t\t .then_some((\"IMPRECISERR\", Self::DOC_IMPRECISERR)),"},{"Add":"\t\t\t self.UNSTKERR().then_some((\"UNSTKERR\", Self::DOC_UNSTKERR)),"},{"Add":"\t\t\t self.STKERR().then_some((\"STKERR\", Self::DOC_STKERR)),"},{"Add":"\t\t\t self.LSPERR().then_some((\"LSPERR\", Self::DOC_LSPERR)),"},{"Add":"\t\t\t].into_iter()"},{"Add":"\t\t\t.flatten()"},{"Add":"\t\t} else {"},{"Add":"\t\t\t<[_; 6]>::default().into_iter().flatten()"},{"Add":"\t\t}"},{"Add":"\t}"},{"Add":"}"},{"Add":""},{"Add":""},{"Add":"/// The MemManage fault status register"},{"Add":"/// indicates a memory access violation detected by the Memory Protection Unit (MPU)."},{"Add":"#[derive(Clone, Copy, PartialEq, Eq)]"},{"Add":"pub struct MMFSR(u8);"},{"Add":"impl Debug for MMFSR {"},{"Add":"\tfn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {"},{"Add":"\t\tf.debug_struct(\"MMFSR\")"},{"Add":"\t\t .field(\"IACCVIOL\", &self.IACCVIOL())"},{"Add":"\t\t .field(\"DACCVIOL\", &self.DACCVIOL())"},{"Add":"\t\t .field(\"MUNSTKERR\", &self.MUNSTKERR())"},{"Add":"\t\t .field(\"MSTKERR\", &self.MSTKERR())"},{"Add":"\t\t .field(\"MLSPERR\", &self.MLSPERR())"},{"Add":"\t\t .field(\"MMARVALID\", &self.MMARVALID())"},{"Add":"\t\t .finish()"},{"Add":"\t}"},{"Add":"}"},{"Add":"impl MMFSR {"},{"Add":"\t// Instruction access violation flag."},{"Add":"\t// The processor attempted an instruction fetch from a location that does not permit execution"},{"Add":"\t//"},{"Add":"\t// The PC value stacked for the exception return points to the faulting instruction. The processor"},{"Add":"\t// has not written a fault address to the `MMFAR`. This fault condition occurs on any attempt of"},{"Add":"\t// instruction fetches to an XN (eXecute Never) region, even when the MPU is disabled or not"},{"Add":"\t// present. Potential reasons:"},{"Add":"\t// - Branch to regions that are not defined in the MPU or defined as non-executable."},{"Add":"\t// - Invalid return due to corrupted stack content."},{"Add":"\t// - Incorrect entry in the exception vector table."},{"Add":"\tbit! {0b0000_0001, IACCVIOL, r#\"Instruction access violation."},{"Add":"\t\tThe processor attempted an instruction fetch from a location that does not permit execution."},{"Add":"\t\tFaulting instruction: see `PC`."},{"Add":"\t\t\"#}"},{"Add":""},{"Add":"\t// Data access violation flag."},{"Add":"\t// The processor attempted a load or store at a location that does not permit the operation."},{"Add":"\t//"},{"Add":"\t// The PC value stacked for the exception return points to the faulting instruction."},{"Add":"\t// The processor has loaded the `MMFAR` with the address of the attempted access."},{"Add":"\tbit! {0b0000_0010, DACCVIOL, r#\"Data access violation."},{"Add":"\t\tThe processor attempted a load or store at a location that does not permit the operation."},{"Add":"\t\tFaulting instruction: see `PC`."},{"Add":"\t\tAddress of the attempted access: see `MMFAR`."},{"Add":"\t\t\"#}"},{"Add":""},{"Add":"\t// MemManage fault on unstacking for a return from exception."},{"Add":"\t//"},{"Add":"\t// Unstacking for an exception return has caused one or more access violations."},{"Add":"\t//"},{"Add":"\t// This fault is chained to the handler which means that the original return stack is still present."},{"Add":"\t// The processor has not adjusted the SP from the failing return, and has not performed a new"},{"Add":"\t// save. The processor has not written a fault address to the `MMFAR`. Potential reasons:"},{"Add":"\t// - Stack pointer is corrupted"},{"Add":"\t// - MPU region for the stack changed during execution of the exception handler."},{"Add":"\tbit! {0b0000_1000, MUNSTKERR, r#\"MemManage fault on unstacking for a return from exception."},{"Add":"\t\tFault address - see MMFAR."},{"Add":"\t\tPotential reasons:"},{"Add":"\t\t- Stack pointer is corrupted"},{"Add":"\t\t- MPU region for the stack changed during execution of the exception handler"},{"Add":"\t\t\"#}"},{"Add":""},{"Add":""},{"Add":"\tbit! {0b0001_0000, MSTKERR, r#\""},{"Add":"\t\t\tMemManage fault on stacking for exception entry."},{"Add":""},{"Add":"\t\t\tThe SP is still adjusted but the values in the context area on the stack might be incorrect. The"},{"Add":"\t\t\tprocessor has not written a fault address to the MMFAR. Potential reasons:"},{"Add":"\t\t\t- Stack pointer is corrupted or not initialized"},{"Add":"\t\t\t- Stack is reaching a region not defined by the MPU as read/write memory."},{"Add":"\t\t\t\"#}"},{"Add":""},{"Add":"\tbit! {0b0010_0000, MLSPERR, r#\"MemManage fault during floating point lazy state preservation (only Cortex-M4 with FPU).\"#}"},{"Add":"\tbit! {0b1000_0000, MMARVALID, r#\"MemManage Fault Address Register (MMFAR) valid flag. SCB->MMFAR holds a valid fault address.\"#}"},{"Add":"}"},{"Add":""},{"Add":"impl RegTags for MMFSR {"},{"Add":"\tfn is_empty(&self) -> bool { self.0 == 0 }"},{"Add":""},{"Add":"\tfn tags(&self) -> impl IntoIterator {"},{"Add":"\t\tif self.is_empty() {"},{"Add":"\t\t\treturn [None, None, None, None, None].into_iter().flatten();"},{"Add":"\t\t}"},{"Add":""},{"Add":"\t\t["},{"Add":"\t\t self.IACCVIOL().then_some((\"IACCVIOL\", Self::DOC_IACCVIOL)),"},{"Add":"\t\t self.DACCVIOL().then_some((\"DACCVIOL\", Self::DOC_DACCVIOL)),"},{"Add":"\t\t self.MUNSTKERR().then_some((\"MUNSTKERR\", Self::DOC_MUNSTKERR)),"},{"Add":"\t\t self.MSTKERR().then_some((\"MSTKERR\", Self::DOC_MSTKERR)),"},{"Add":"\t\t self.MLSPERR().then_some((\"MLSPERR\", Self::DOC_MLSPERR)),"},{"Add":"\t\t].into_iter()"},{"Add":"\t\t.flatten()"},{"Add":"\t}"},{"Add":"}"},{"Add":""},{"Add":""},{"Add":"pub trait RegTags {"},{"Add":"\t/// Has no tags"},{"Add":"\tfn is_empty(&self) -> bool;"},{"Add":""},{"Add":"\t/// Returns `true` tags as (name + description)"},{"Add":"\tfn tags(&self) -> impl IntoIterator;"},{"Add":"}"},{"Add":""},{"Add":""},{"Add":"pub enum FaultKind {"},{"Add":"\t// HFSR:"},{"Add":"\t/// Bus error on a vector read error HardFault"},{"Add":"\tVECTTBL,"},{"Add":"\t/// Fault that is escalated to a hard fault"},{"Add":"\tFORCED,"},{"Add":"\t/// Fault on breakpoint escalation"},{"Add":"\tDEBUGEVT,"},{"Add":""},{"Add":"\t// MMFSR:"},{"Add":"\t/// Fault on instruction access MemManage"},{"Add":"\tIACCVIOL,"},{"Add":"\t/// Fault on direct data access"},{"Add":"\tDACCVIOL,"},{"Add":"\t/// Context stacking, because of an MPU access violation"},{"Add":"\tMSTKERR,"},{"Add":"\t/// Context unstacking, because of an MPU access violation"},{"Add":"\tMUNSTKERR,"},{"Add":"\t/// During lazy floating-point state preservation"},{"Add":"\tMLSPERR,"},{"Add":""},{"Add":"\t// BFSR:"},{"Add":"\t/// During exception stacking BusFault"},{"Add":"\tSTKERR,"},{"Add":"\t/// During exception unstacking"},{"Add":"\tUNSTKERR,"},{"Add":"\t/// During instruction prefetching, precise"},{"Add":"\tIBUSERR,"},{"Add":"\t/// During lazy floating-point state preservation"},{"Add":"\tLSPERR,"},{"Add":"\t/// Precise data access error, precise"},{"Add":"\tPRECISERR,"},{"Add":"\t/// Imprecise data access error, imprecise"},{"Add":"\tIMPRECISERR,"},{"Add":""},{"Add":"\t// UFSR:"},{"Add":"\t/// Undefined instruction UsageFault"},{"Add":"\tUNDEFINSTR,"},{"Add":"\t/// Attempt to enter an invalid instruction set state"},{"Add":"\tINVSTATE,"},{"Add":"\t/// Failed integrity check on exception return"},{"Add":"\tINVPC,"},{"Add":"\t/// Attempt to access a non-existing coprocessor"},{"Add":"\tNOCPC,"},{"Add":"\t/// Illegal unaligned load or store"},{"Add":"\tUNALIGNED,"},{"Add":"\t/// Stack overflow"},{"Add":"\tSTKOF,"},{"Add":"\t/// Divide By 0"},{"Add":"\tDIVBYZERO,"},{"Add":"}"},{"Add":""},{"Add":""},{"Add":"#[derive(Clone, Copy, Debug, PartialEq, Eq)]"},{"Add":"pub enum FpuAccessMode {"},{"Add":"\t/// FPU is not accessible"},{"Add":"\tDisabled,"},{"Add":"\t/// FPU is accessible in Privileged and User mode"},{"Add":"\tEnabled,"},{"Add":"\t/// FPU is accessible in Privileged mode only"},{"Add":"\tPrivileged,"},{"Add":"}"},{"Add":""},{"Add":""},{"Add":"/// Active exception number"},{"Add":"#[derive(Clone, Copy, Debug, Eq, PartialEq, PartialOrd, Hash)]"},{"Add":"pub enum VectActive {"},{"Add":"\t/// Thread mode"},{"Add":"\tThreadMode,"},{"Add":""},{"Add":"\t/// Processor core exception (internal interrupts)"},{"Add":"\tException(Exception),"},{"Add":""},{"Add":"\t/// Device specific exception (external interrupts)"},{"Add":"\tInterrupt {"},{"Add":"\t\t/// Interrupt number. This number is always within half open range `[0, 512)` (9 bit)"},{"Add":"\t\tirqn: u16,"},{"Add":"\t},"},{"Add":"}"},{"Add":""},{"Add":"impl VectActive {"},{"Add":"\t/// Converts a vector number into `VectActive`"},{"Add":"\t#[inline]"},{"Add":"\tpub fn from(vect_active: u16) -> Option {"},{"Add":"\t\tSome(match vect_active {"},{"Add":"\t\t\t0 => VectActive::ThreadMode,"},{"Add":"\t\t\t2 => VectActive::Exception(Exception::NonMaskableInt),"},{"Add":"\t\t\t3 => VectActive::Exception(Exception::HardFault),"},{"Add":"\t\t\t4 => VectActive::Exception(Exception::MemoryManagement),"},{"Add":"\t\t\t5 => VectActive::Exception(Exception::BusFault),"},{"Add":"\t\t\t6 => VectActive::Exception(Exception::UsageFault),"},{"Add":"\t\t\t7 => VectActive::Exception(Exception::SecureFault),"},{"Add":"\t\t\t11 => VectActive::Exception(Exception::SVCall),"},{"Add":"\t\t\t12 => VectActive::Exception(Exception::DebugMonitor),"},{"Add":"\t\t\t14 => VectActive::Exception(Exception::PendSV),"},{"Add":"\t\t\t15 => VectActive::Exception(Exception::SysTick),"},{"Add":"\t\t\tirqn if (16..512).contains(&irqn) => VectActive::Interrupt { irqn: irqn - 16 },"},{"Add":"\t\t\t_ => return None,"},{"Add":"\t\t})"},{"Add":"\t}"},{"Add":"}"},{"Add":""},{"Add":""},{"Add":"/// Processor core exceptions (internal interrupts)"},{"Add":"#[derive(Clone, Copy, Debug, Eq, PartialEq, PartialOrd, Hash)]"},{"Add":"pub enum Exception {"},{"Add":"\t/// Non maskable interrupt"},{"Add":"\tNonMaskableInt,"},{"Add":""},{"Add":"\t/// Hard fault interrupt"},{"Add":"\tHardFault,"},{"Add":""},{"Add":"\t/// Memory management interrupt (not present on Cortex-M0 variants)"},{"Add":"\tMemoryManagement,"},{"Add":""},{"Add":"\t/// Bus fault interrupt (not present on Cortex-M0 variants)"},{"Add":"\tBusFault,"},{"Add":""},{"Add":"\t/// Usage fault interrupt (not present on Cortex-M0 variants)"},{"Add":"\tUsageFault,"},{"Add":""},{"Add":"\t/// Secure fault interrupt (only on ARMv8-M)"},{"Add":"\tSecureFault,"},{"Add":""},{"Add":"\t/// SV call interrupt"},{"Add":"\tSVCall,"},{"Add":""},{"Add":"\t/// Debug monitor interrupt (not present on Cortex-M0 variants)"},{"Add":"\tDebugMonitor,"},{"Add":""},{"Add":"\t/// Pend SV interrupt"},{"Add":"\tPendSV,"},{"Add":""},{"Add":"\t/// System Tick interrupt"},{"Add":"\tSysTick,"},{"Add":"}"},{"Add":""},{"Add":""},{"Add":"#[cfg(test)]"},{"Add":"mod tests {"},{"Add":"\tuse super::*;"},{"Add":""},{"Add":""},{"Add":"\t#[test]"},{"Add":"\tfn test_mmfsr_daccviol() {"},{"Add":"\t\tlet reg = ExceptionFrame { r0: 0x00000004,"},{"Add":"\t\t r1: 0x00000008,"},{"Add":"\t\t r2: 0x00000008,"},{"Add":"\t\t r3: 0x00000008,"},{"Add":"\t\t r12: 0x00000008,"},{"Add":"\t\t lr: 0x6000d2e7.into(),"},{"Add":"\t\t pc: 0x6000d5e8.into(),"},{"Add":"\t\t psr: 0x010f0000.into(),"},{"Add":"\t\t cfsr: 0x00000082.into(),"},{"Add":"\t\t hfsr: 0x00000000.into(),"},{"Add":"\t\t mmfar: 0x00000004.into(),"},{"Add":"\t\t bfar: 0x00000004.into(),"},{"Add":"\t\t rcccsr: 0x00000000 };"},{"Add":"\t\tlet mmfsr = reg.mmfsr();"},{"Add":"\t\tassert!(mmfsr.DACCVIOL());"},{"Add":"\t\tassert!(mmfsr.MMARVALID());"},{"Add":"\t}"},{"Add":""},{"Add":"\t#[test]"},{"Add":"\tfn test_mmfsr_daccviol__() {"},{"Add":"\t\tlet reg = ExceptionFrame { r0: 0x00000004,"},{"Add":"\t\t r1: 0x00000008,"},{"Add":"\t\t r2: 0x00000008,"},{"Add":"\t\t r3: 0x00000008,"},{"Add":"\t\t r12: 0x00000008,"},{"Add":"\t\t lr: 0x6000d2e7.into(),"},{"Add":"\t\t pc: 0x6000d5e8.into(),"},{"Add":"\t\t psr: 0x010f0000.into(),"},{"Add":"\t\t cfsr: 0x00000082.into(),"},{"Add":"\t\t hfsr: 0x00000000.into(),"},{"Add":"\t\t mmfar: 0x00000004.into(),"},{"Add":"\t\t bfar: 0x00000004.into(),"},{"Add":"\t\t rcccsr: 0x00000000 };"},{"Add":"\t\tlet mmfsr = reg.mmfsr();"},{"Add":"\t\tassert!(mmfsr.DACCVIOL());"},{"Add":"\t\tassert!(mmfsr.MMARVALID());"},{"Add":"\t}"},{"Add":"}"}]}},{"Edit":{"inode":{"change":3,"pos":75604},"path":"support/addr2line/src/addr2line-crashlog.rs","line":12,"atom":{"EdgeMap":{"edges":[{"previous":"BLOCK","flag":"BLOCK | DELETED","from":{"change":3,"pos":75838},"to":{"change":3,"start":75838,"end":75910},"introduced_by":3}],"inode":{"change":3,"pos":75604}}},"contents":[{"Del":"use pd::fmt::crashlog::CrashLog;\nuse pd::fmt::report::WriteReport as _;\n"}]}},{"Edit":{"inode":{"change":3,"pos":75604},"path":"support/addr2line/src/addr2line-crashlog.rs","line":13,"atom":{"NewVertex":{"up_context":[{"change":3,"pos":75921}],"down_context":[{"change":3,"pos":75921}],"flag":"BLOCK","start":35695,"end":35696,"inode":{"change":3,"pos":75604}}},"contents":[{"Add":""}]}},{"Edit":{"inode":{"change":3,"pos":75604},"path":"support/addr2line/src/addr2line-crashlog.rs","line":15,"atom":{"NewVertex":{"up_context":[{"change":3,"pos":75922}],"down_context":[{"change":3,"pos":75922}],"flag":"BLOCK","start":35697,"end":35786,"inode":{"change":3,"pos":75604}}},"contents":[{"Add":"const ADDR_REG: &[&str] = &[\"lr\", \"pc\", \"mmfar\", \"bfar\", \"r0\", \"r1\", \"r2\", \"r3\", \"r12\"];"}]}},{"Edit":{"inode":{"change":3,"pos":75604},"path":"support/addr2line/src/addr2line-crashlog.rs","line":17,"atom":{"NewVertex":{"up_context":[{"change":3,"pos":75923}],"down_context":[{"change":3,"pos":75923}],"flag":"BLOCK","start":35787,"end":35788,"inode":{"change":3,"pos":75604}}},"contents":[{"Add":""}]}},{"Replacement":{"inode":{"change":3,"pos":75604},"path":"support/addr2line/src/addr2line-crashlog.rs","line":35,"ins":{"up_context":[{"change":3,"pos":76525}],"down_context":[{"change":3,"pos":76766}],"flag":"BLOCK","start":35789,"end":36084,"inode":{"change":3,"pos":75604}},"del":{"edges":[{"previous":"BLOCK","flag":"BLOCK | DELETED","from":{"change":3,"pos":76525},"to":{"change":3,"start":76525,"end":76766},"introduced_by":3}],"inode":{"change":3,"pos":75604}},"ins_contents":[{"Add":"\t\t\t let count = ADDR_REG.into_iter()"},{"Add":"\t\t\t .flat_map(|v| doc.ptrs.get(*v))"},{"Add":"\t\t\t .filter(|v| addrs.insert(**v))"},{"Add":"\t\t\t .map_while(|v| tx.send(*v).map_err(|err| error!(\"{err}\")).ok())"},{"Add":"\t\t\t .count();"}],"del_contents":[{"Del":"\t\t\t let count = doc.ptrs\n\t\t\t .values()\n\t\t\t .filter(|v| addrs.insert(**v))\n\t\t\t .map_while(|v| tx.send(*v).map_err(|err| error!(\"{err}\")).ok())\n\t\t\t .count();\n"}]}},{"Edit":{"inode":{"change":3,"pos":75604},"path":"support/addr2line/src/addr2line-crashlog.rs","line":69,"atom":{"EdgeMap":{"edges":[{"previous":"BLOCK","flag":"BLOCK | DELETED","from":{"change":3,"pos":77628},"to":{"change":3,"start":77628,"end":78607},"introduced_by":3}],"inode":{"change":3,"pos":75604}}},"contents":[{"Del":"\tlet docs: Vec<_> = docs.into_iter()\n\t .map(|doc| {\n\t\t let CrashLog { date,\n\t\t build,\n\t\t heap,\n\t\t ptrs, } = doc;\n\t\t let ptrs = ptrs.into_iter()\n\t\t .map(|(k, v)| {\n\t\t\t match resolved_addrs.get(&v) {\n\t\t\t\t Some(rep) => (k, rep),\n\t\t\t None => unreachable!(\"Key not found: {v:#08x?}\"),\n\t\t\t }\n\t\t })\n\t\t .collect();\n\t\t CrashLog { date,\n\t\t build,\n\t\t heap,\n\t\t ptrs }\n\t })\n\t .collect();\n"}]}},{"Replacement":{"inode":{"change":3,"pos":75604},"path":"support/addr2line/src/addr2line-crashlog.rs","line":70,"ins":{"up_context":[{"change":3,"pos":78608}],"down_context":[{"change":3,"pos":78916}],"flag":"BLOCK","start":36085,"end":36422,"inode":{"change":3,"pos":75604}},"del":{"edges":[{"previous":"BLOCK","flag":"BLOCK | DELETED","from":{"change":3,"pos":78608},"to":{"change":3,"start":78608,"end":78916},"introduced_by":3}],"inode":{"change":3,"pos":75604}},"ins_contents":[{"Add":"\tfor doc in &docs {"},{"Add":"\t\tdoc.pretty_print("},{"Add":"\t\t std::io::stdout(),"},{"Add":"\t\t &resolved_addrs,"},{"Add":"\t\t true,"},{"Add":"\t\t 0,"},{"Add":"\t\t cfg.base.flags.functions,"},{"Add":"\t\t cfg.base.flags.basenames,"},{"Add":"\t\t cfg.base.flags.ranges,"},{"Add":"\t\t cfg.base.flags.demangle,"}],"del_contents":[{"Del":"\tfor doc in docs {\n\t\tdoc.default_print(\n\t\t std::io::stdout(),\n\t\t true,\n\t\t 0,\n\t\t cfg.base.flags.functions,\n\t\t cfg.base.flags.basenames,\n\t\t cfg.base.flags.ranges,\n\t\t cfg.base.flags.demangle,\n"}]}},{"Replacement":{"inode":{"change":3,"pos":81216},"path":"support/addr2line/Cargo.toml","line":3,"ins":{"up_context":[{"change":3,"pos":81255}],"down_context":[{"change":3,"pos":81273}],"flag":"BLOCK","start":36425,"end":36443,"inode":{"change":3,"pos":81216}},"del":{"edges":[{"previous":"BLOCK","flag":"BLOCK | DELETED","from":{"change":3,"pos":81255},"to":{"change":4,"start":123,"end":141},"introduced_by":4}],"inode":{"change":3,"pos":81216}},"ins_contents":[{"Add":"version = \"0.2.0\""}],"del_contents":[{"Del":"version = \"0.1.3\"\n"}]}},{"Edit":{"inode":{"change":3,"pos":81216},"path":"support/addr2line/Cargo.toml","line":39,"atom":{"NewVertex":{"up_context":[{"change":3,"pos":82299}],"down_context":[{"change":3,"pos":82299}],"flag":"BLOCK","start":36444,"end":36458,"inode":{"change":3,"pos":81216}}},"contents":[{"Add":"paste = \"1.0\""}]}},{"Edit":{"inode":{"change":2,"pos":3671603},"path":"Cargo.lock","line":3951,"atom":{"NewVertex":{"up_context":[{"change":3,"pos":88741}],"down_context":[{"change":2,"pos":3726644}],"flag":"BLOCK","start":36758,"end":36948,"inode":{"change":2,"pos":3671603}}},"contents":[{"Add":"name = \"paste\""},{"Add":"version = \"1.0.15\""},{"Add":"source = \"registry+https://github.com/rust-lang/crates.io-index\""},{"Add":"checksum = \"57c0d7b74b563b49d38dae00a0c37d4d6de9b432382b2892f0574ddcae73fd0a\""},{"Add":""},{"Add":"[[package]]"}]}},{"Replacement":{"inode":{"change":2,"pos":3671603},"path":"Cargo.lock","line":4356,"ins":{"up_context":[{"change":3,"pos":89713}],"down_context":[{"change":3,"pos":89731}],"flag":"BLOCK","start":36949,"end":36967,"inode":{"change":2,"pos":3671603}},"del":{"edges":[{"previous":"BLOCK","flag":"BLOCK | DELETED","from":{"change":3,"pos":89713},"to":{"change":4,"start":6678,"end":6696},"introduced_by":4}],"inode":{"change":2,"pos":3671603}},"ins_contents":[{"Add":"version = \"0.2.0\""}],"del_contents":[{"Del":"version = \"0.1.3\"\n"}]}},{"Edit":{"inode":{"change":2,"pos":3671603},"path":"Cargo.lock","line":4365,"atom":{"NewVertex":{"up_context":[{"change":3,"pos":89839}],"down_context":[{"change":3,"pos":89839}],"flag":"BLOCK","start":36968,"end":36978,"inode":{"change":2,"pos":3671603}}},"contents":[{"Add":" \"paste\","}]}}],"owner":"fzzr","repo":"playdate","token":"LX2LyG97kmcWzNuctbbINLeNGQAY7ctu8OlVIcYFHqM=","login":null}

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