{"header":{"message":"Refactor soc and core","description":null,"timestamp":"2024-05-18T01:33:28.117594191Z","authors":[{}]},"hash":"LLHICJMHRWCZVTXZOJ3MO3LX6RCYUN6HTRMMJMGVOEBUXW6YMDWQC","authors":[{"key":"8Cqo1QjSCQ3F66Vh3nan9N8dv1MjQSAEz8RNwt2cTacK"}],"deps":{"hashes":[["LLHICJMHRWCZVTXZOJ3MO3LX6RCYUN6HTRMMJMGVOEBUXW6YMDWQC","Refactor soc and core"],["AA",null],["3YRZ62OF7SF6EPM6JEQ7QOOAW4VNXCXVDQ3G5NPCUUBJ6S6LXOKAC","Implemented register file and created skeleton for basic core"],["MTNLHQLQZKMX7PKQ3CDVBVFE3AGOTZHUY2WATLRBJWLFZBW6SXJQC","Focus on the hardware design by dropping alternative HDLS for Verilog"],["MOJRQVF4Q7OM2AHWAFBZOXHP5I3ZUWWKTTH6LOI5IIKB4VHXHNNQC","Factored out memory interface"]],"deps":["3YRZ62OF7SF6EPM6JEQ7QOOAW4VNXCXVDQ3G5NPCUUBJ6S6LXOKAC"],"known":["MTNLHQLQZKMX7PKQ3CDVBVFE3AGOTZHUY2WATLRBJWLFZBW6SXJQC","MOJRQVF4Q7OM2AHWAFBZOXHP5I3ZUWWKTTH6LOI5IIKB4VHXHNNQC"]},"hunks":[{"FileDel":{"deleted_names":[{"basename":"regfile.sv","metadata":0}],"del":{"EdgeMap":{"edges":[{"previous":"BLOCK | FOLDER","flag":"BLOCK | FOLDER | DELETED","from":{"change":3,"pos":1},"to":{"change":2,"start":841,"end":875},"introduced_by":2},{"previous":"BLOCK | FOLDER","flag":"BLOCK | FOLDER | DELETED","from":{"change":2,"pos":875},"to":{"change":2,"start":1,"end":1},"introduced_by":2}],"inode":{"change":2,"pos":1}}},"content_edges":{"edges":[{"previous":"BLOCK","flag":"BLOCK | DELETED","from":{"change":2,"pos":1},"to":{"change":2,"start":2,"end":840},"introduced_by":2}],"inode":{"change":2,"pos":1}},"content":[{"Del":"// SPDX-License-Identifier: CERN-OHL-S-2.0\n\n// A simple dual-read, single-write register file\n\n`default_nettype none\n`timescale 1ps/1ps\n\nmodule regfile\n(\n input bit clk, rst,\n // Write port\n input wire wen,\n input wire [5:0] waddr,\n input wire [31:0] wdata,\n // Read ports\n input wire [5:0] raddrA,\n output wire [31:0] rdataA,\n input wire [5:0] raddrB,\n output wire [31:0] rdataB\n);\n\n // r0 is always 0, so we can not implement it\n reg [31:0] registers [0:30]; \n\n always_ff @(posedge clk, rst)\n if (rst)\n for (integer i = 0; i < 32; i++) begin\n registers[i] <= 0;\n end\n else if (wen)\n registers[~waddr[4:0]] <= wdata;\n\n assign rdataA = registers[~raddrA[4:0]];\n\tassign rdataB = registers[~raddrB[4:0]];\nendmodule"}]}},{"FileDel":{"deleted_names":[{"basename":"soc.sv","metadata":0}],"del":{"EdgeMap":{"edges":[{"previous":"BLOCK | FOLDER","flag":"BLOCK | FOLDER | DELETED","from":{"change":3,"pos":1},"to":{"change":3,"start":1423,"end":1453},"introduced_by":3},{"previous":"BLOCK | FOLDER","flag":"BLOCK | FOLDER | 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logs/vlt_dump.vcd...\\n\", $time);\n $dumpfile(\"logs/vlt_dump.vcd\");\n $dumpvars();\n"},{"Del":" end\n end\n // synthesis translate on\n\nendmodule\n"},{"Del":" input wire uart_rx,\n output wire uart_tx\n"}]}},{"FileDel":{"deleted_names":[{"basename":"basic_rv32i.sv","metadata":0}],"del":{"EdgeMap":{"edges":[{"previous":"BLOCK | FOLDER","flag":"BLOCK | FOLDER | DELETED","from":{"change":3,"pos":1},"to":{"change":2,"start":2137,"end":2175},"introduced_by":2},{"previous":"BLOCK | FOLDER","flag":"BLOCK | FOLDER | DELETED","from":{"change":2,"pos":2175},"to":{"change":2,"start":877,"end":877},"introduced_by":2}],"inode":{"change":2,"pos":877}}},"content_edges":{"edges":[{"previous":"BLOCK","flag":"BLOCK | DELETED","from":{"change":2,"pos":877},"to":{"change":2,"start":878,"end":2136},"introduced_by":2}],"inode":{"change":2,"pos":877}},"content":[{"Del":"// SPDX-License-Identifier: CERN-OHL-S-2.0\n\n// A maxmimally simple core\n\n`default_nettype none\n`timescale 1ps/1ps\n\nmodule basic_rv32i\n(\n mem.core mem,\n\n`ifdef RISCV_FORMAL\n output reg rvfi_valid,\n\toutput reg [63:0] rvfi_order,\n\toutput reg [31:0] rvfi_insn,\n\toutput reg rvfi_trap,\n\toutput reg rvfi_halt,\n\toutput reg rvfi_intr,\n\toutput reg [ 1:0] rvfi_mode,\n\toutput reg [ 1:0] rvfi_ixl,\n\toutput reg [ 4:0] rvfi_rs1_addr,\n\toutput reg [ 4:0] rvfi_rs2_addr,\n\toutput reg [31:0] rvfi_rs1_rdata,\n\toutput reg [31:0] rvfi_rs2_rdata,\n\toutput reg [ 4:0] rvfi_rd_addr,\n\toutput reg [31:0] rvfi_rd_wdata,\n\toutput reg [31:0] rvfi_pc_rdata,\n\toutput reg [31:0] rvfi_pc_wdata,\n\toutput reg [31:0] rvfi_mem_addr,\n\toutput reg [ 3:0] rvfi_mem_rmask,\n\toutput reg [ 3:0] rvfi_mem_wmask,\n\toutput reg [31:0] rvfi_mem_rdata,\n\toutput reg [31:0] rvfi_mem_wdata,\n\n\toutput reg [63:0] rvfi_csr_mcycle_rmask,\n\toutput reg [63:0] rvfi_csr_mcycle_wmask,\n\toutput reg [63:0] rvfi_csr_mcycle_rdata,\n\toutput reg [63:0] rvfi_csr_mcycle_wdata,\n\n\toutput reg [63:0] rvfi_csr_minstret_rmask,\n\toutput reg [63:0] rvfi_csr_minstret_wmask,\n\toutput reg [63:0] rvfi_csr_minstret_rdata,\n\toutput reg [63:0] rvfi_csr_minstret_wdata,\n`endif\n\n input bit clk, rst\n);\n\n\n\nendmodule"}]}},{"FileDel":{"deleted_names":[{"basename":"mem.sv","metadata":0}],"del":{"EdgeMap":{"edges":[{"previous":"BLOCK | FOLDER","flag":"BLOCK | FOLDER | DELETED","from":{"change":3,"pos":1},"to":{"change":3,"start":2244,"end":2274},"introduced_by":3},{"previous":"BLOCK | FOLDER","flag":"BLOCK | FOLDER | DELETED","from":{"change":3,"pos":2274},"to":{"change":3,"start":1,"end":1},"introduced_by":3}],"inode":{"change":3,"pos":1}}},"content_edges":{"edges":[{"previous":"BLOCK","flag":"BLOCK | DELETED","from":{"change":3,"pos":1},"to":{"change":3,"start":2,"end":1346},"introduced_by":3},{"previous":"","flag":"DELETED","from":{"change":2,"pos":2300},"to":{"change":3,"start":1419,"end":2243},"introduced_by":2},{"previous":"BLOCK","flag":"BLOCK | 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All core outputs are stable over the valid period.\n// If the transfer is an instruction fetch, the core asserts instr.\ninterface mem;\n bit valid; \n bit ready; \n bit instr;\n\n enum bit[3:0] {\n READ = 'b0000,\n WRITE_BYTE0 = 'b0001,\n WRITE_BYTE1 = 'b0010,\n WRITE_BYTE2 = 'b0100,\n WRITE_BYTE3 = 'b1000,\n WRITE_HWORD0 = 'b0011,\n WRITE_HWORD1 = 'b1100,\n WRITE_WORD = 'b1111\n } mode;\n\n wire [31:0] addr;\n wire [31:0] rdata;\n wire [31:0] wdata;\n\n modport core (\n output valid,\n input ready,\n output instr,\n output mode, \n output addr,\n input rdata,\n output wdata\n );\n\n modport impl ( \n input valid,\n output ready,\n input instr,\n input mode,\n input addr,\n output rdata,\n input wdata\n );\nendinterface\n\n/* verilator lint_off DECLFILENAME */\nmodule mem_impl\n#(\n parameter integer MEM_WORDS = 4096\n)\n(\n input bit clk,\n\n mem.impl mem\n);\n\n"},{"Del":"\n always_ff @(posedge clk) begin\n mem.ready <= '0;\n \n if (mem.valid) begin\n mem.rdata <= memory[mem.addr]; \n if (wen[0]) memory[mem.addr][ 7: 0] <= mem.wdata[ 7: 0];\n if (wen[1]) memory[mem.addr][15: 8] <= mem.wdata[15: 8];\n if (wen[2]) memory[mem.addr][23:16] <= mem.wdata[23:16];\n if (wen[3]) memory[mem.addr][31:24] <= mem.wdata[31:24];\n end\n end\n\n\n // synthesis translate off\n logic [200:0] mem_file;\n initial begin\n if ($value$plusargs(\"mem\", mem_file)) begin\n $display(\"[%0t] Initializing memory\\n\", $time);\n $readmemh(mem_file, memory);\n end\n end\n \n\n phys_mem_addr: assert property(@(posedge clk) mem.addr < (4*MEM_WORDS));\n\n // synthesis translate on\nendmodule\n"},{"Del":" reg [31:0] memory [0:MEM_WORDS-1];\n reg [3:0] wen = mem.mode;\n"}]}},{"FileAdd":{"meta":{"basename":"soc","metadata":576},"context":[{"change":3,"pos":1}],"contents":[]}},{"FileAdd":{"meta":{"basename":"uart.sv","metadata":0},"context":[{"change":0,"pos":1}],"contents":[{"Add":"// SPDX-License-Identifier: CERN-OHL-S-2.0"},{"Add":""},{"Add":"// A basic valid-ready ram, default 16KiB"},{"Add":""},{"Add":"`default_nettype none"},{"Add":"`timescale 1ps/1ps"},{"Add":""},{"Add":"module uart "},{"Add":"( "},{"Add":" input logic clk_i,"},{"Add":" input logic rst_ni,"},{"Add":""},{"Add":" input logic uart_i,"},{"Add":" output logic uart_o"},{"Add":");"},{"Add":""},{"Add":" // TODO: implement"},{"Add":" "},{"Add":"endmodule"}]}},{"FileAdd":{"meta":{"basename":"soc_pkg.sv","metadata":0},"context":[{"change":0,"pos":1}],"contents":[{"Add":"// SPDX-License-Identifier: CERN-OHL-S-2.0"},{"Add":""},{"Add":"`default_nettype none"},{"Add":"`timescale 1ps/1ps"},{"Add":""},{"Add":"package soc_pkg;"},{"Add":""},{"Add":" parameter int unsigned MEM_WORDS = 4096;"},{"Add":""},{"Add":" typedef struct packed {"},{"Add":" logic valid;"},{"Add":" "},{"Add":" logic [ 7:0] wen;"},{"Add":" logic [63:0] addr;"},{"Add":" logic [63:0] wdata;"},{"Add":" } mem_in_t;"},{"Add":""},{"Add":" typedef struct packed {"},{"Add":" logic ready;"},{"Add":""},{"Add":" logic [63:0] rdata;"},{"Add":" } mem_out_t;"},{"Add":""},{"Add":""},{"Add":"endpackage"}]}},{"FileAdd":{"meta":{"basename":"soc.sv","metadata":0},"context":[{"change":0,"pos":1}],"contents":[{"Add":"// SPDX-License-Identifier: CERN-OHL-S-2.0"},{"Add":""},{"Add":"// A basic SOC with the core, ram, and uart"},{"Add":"// Default 32KiB ram"},{"Add":""},{"Add":"`default_nettype none"},{"Add":"`timescale 1ps/1ps"},{"Add":""},{"Add":"module soc"},{"Add":"("},{"Add":" input logic clk_i,"},{"Add":" input logic rst_ni,"},{"Add":""},{"Add":" input logic uart_i,"},{"Add":" output logic uart_o"},{"Add":");"},{"Add":" uart uart_impl(.clk_i, .rst_ni, .uart_i, .uart_o);"},{"Add":""},{"Add":" soc_pkg::mem_in_t mem_in;"},{"Add":" soc_pkg::mem_out_t mem_out;"},{"Add":""},{"Add":" mem ram(.clk_i, .core_i(mem_in), .core_o(mem_out));"},{"Add":""},{"Add":" `ifndef SYNTHESIS"},{"Add":" initial begin"},{"Add":" if ($test$plusargs(\"trace\") != 0) begin"},{"Add":" $display(\"[%0t] Tracing to logs/vlt_dump.vcd...\\n\", $time);"},{"Add":" $dumpfile(\"logs/vlt_dump.vcd\");"},{"Add":" $dumpvars();"},{"Add":" end"},{"Add":" end"},{"Add":" `endif"},{"Add":""},{"Add":"endmodule"}]}},{"FileAdd":{"meta":{"basename":"mem.sv","metadata":0},"context":[{"change":0,"pos":1}],"contents":[{"Add":"// SPDX-License-Identifier: CERN-OHL-S-2.0"},{"Add":""},{"Add":"// A basic valid-ready ram, default 32KiB"},{"Add":""},{"Add":"`default_nettype none"},{"Add":"`timescale 1ps/1ps"},{"Add":""},{"Add":"// The core initiates a transfer by asserting valid, which stays high until the "},{"Add":"// peer asserts ready. All core outputs are stable over the valid period."},{"Add":"module mem"},{"Add":"("},{"Add":" input logic clk_i,"},{"Add":" "},{"Add":" input soc_pkg::mem_in_t core_i,"},{"Add":" output soc_pkg::mem_out_t core_o"},{"Add":");"},{"Add":""},{"Add":" logic [63:0] memory [0:soc_pkg::MEM_WORDS-1];"},{"Add":""},{"Add":" always_ff @(posedge clk_i) begin "},{"Add":" core_o.ready <= '0;"},{"Add":" "},{"Add":" if (core_i.valid) begin"},{"Add":" MemAddrFitsIntoPhys: assert(core_i.addr < (8*soc_pkg::MEM_WORDS));"},{"Add":""},{"Add":" core_o.rdata <= memory[core_i.addr]; "},{"Add":" core_o.ready <= 1'b1;"},{"Add":""},{"Add":" if (core_i.wen[0]) memory[core_i.addr][ 7: 0] <= core_i.wdata[ 7: 0];"},{"Add":" if (core_i.wen[1]) memory[core_i.addr][15: 8] <= core_i.wdata[15: 8];"},{"Add":" if (core_i.wen[2]) memory[core_i.addr][23:16] <= core_i.wdata[23:16];"},{"Add":" if (core_i.wen[3]) memory[core_i.addr][31:24] <= core_i.wdata[31:24];"},{"Add":" end"},{"Add":" end"},{"Add":""},{"Add":" `ifndef SYNTHESIS"},{"Add":" logic [200:0] mem_file;"},{"Add":" initial begin"},{"Add":" if ($value$plusargs(\"mem\", mem_file)) begin"},{"Add":" $display(\"[%0t] Initializing memory\\n\", $time);"},{"Add":" $readmemh(mem_file, memory);"},{"Add":" end"},{"Add":" end"},{"Add":" `endif"},{"Add":""},{"Add":"endmodule"}]}},{"FileAdd":{"meta":{"basename":"core","metadata":576},"context":[{"change":3,"pos":1}],"contents":[]}},{"FileAdd":{"meta":{"basename":"core_pkg.sv","metadata":0},"context":[{"change":0,"pos":2949}],"contents":[{"Add":"// SPDX-License-Identifier: CERN-OHL-S-2.0"},{"Add":"`default_nettype none"},{"Add":"`timescale 1ps/1ps"},{"Add":""},{"Add":"package core_pkg;"},{"Add":"// The core initiates a transfer by asserting valid, which stays high until the "},{"Add":"// peer asserts ready. All core outputs are stable over the valid period."},{"Add":"typedef struct packed {"},{"Add":" logic valid;"},{"Add":" "},{"Add":" logic [ 3:0] wen;"},{"Add":" logic [31:0] addr;"},{"Add":" logic [31:0] wdata;"},{"Add":"} core_out_t;"},{"Add":""},{"Add":"typedef struct packed {"},{"Add":" logic ready;"},{"Add":""},{"Add":" logic [31:0] rdata;"},{"Add":"} core_in_t; "},{"Add":""},{"Add":""},{"Add":"endpackage"}]}},{"Replacement":{"inode":{"change":3,"pos":1455},"path":"README.md","line":2,"ins":{"up_context":[{"change":3,"pos":1526}],"down_context":[{"change":3,"pos":1624}],"flag":"BLOCK","start":3487,"end":3572,"inode":{"change":3,"pos":1455}},"del":{"edges":[{"previous":"BLOCK","flag":"BLOCK | DELETED","from":{"change":3,"pos":1526},"to":{"change":3,"start":1526,"end":1624},"introduced_by":3}],"inode":{"change":3,"pos":1455}},"ins_contents":[{"Add":"The core targets RV64IAMS to reduce complexity while still being able to boot Linux."}],"del_contents":[{"Del":"The core targets RV32IAMS to fit on reasonably priced FPGAs while still being able to boot Linux.\n"}]}},{"Replacement":{"inode":{"change":3,"pos":1455},"path":"README.md","line":4,"ins":{"up_context":[{"change":3,"pos":1625}],"down_context":[{"change":3,"pos":1797}],"flag":"BLOCK","start":3573,"end":3744,"inode":{"change":3,"pos":1455}},"del":{"edges":[{"previous":"BLOCK","flag":"BLOCK | DELETED","from":{"change":3,"pos":1625},"to":{"change":3,"start":1625,"end":1797},"introduced_by":3}],"inode":{"change":3,"pos":1455}},"ins_contents":[{"Add":"A toolchain will need to be compiled from source, as the default extensions for RISC-V toolchains are GC, and the `lp64` ABI used is not compatible with the ABI they use."}],"del_contents":[{"Del":"A toolchain will need to be compiled from source, as the default extensions for RISC-V toolchains are GC, and the `ilp32` ABI used is not compatible with the ABI they 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