{"header":{"message":"Factored out memory interface","description":null,"timestamp":"2024-05-15T04:49:13.228716148Z","authors":[{}]},"hash":"MOJRQVF4Q7OM2AHWAFBZOXHP5I3ZUWWKTTH6LOI5IIKB4VHXHNNQC","authors":[{"key":"8Cqo1QjSCQ3F66Vh3nan9N8dv1MjQSAEz8RNwt2cTacK"}],"deps":{"hashes":[["MOJRQVF4Q7OM2AHWAFBZOXHP5I3ZUWWKTTH6LOI5IIKB4VHXHNNQC","Factored out memory interface"],["AA",null],["MTNLHQLQZKMX7PKQ3CDVBVFE3AGOTZHUY2WATLRBJWLFZBW6SXJQC","Focus on the hardware design by dropping alternative HDLS for Verilog"]],"deps":["MTNLHQLQZKMX7PKQ3CDVBVFE3AGOTZHUY2WATLRBJWLFZBW6SXJQC"],"known":[]},"hunks":[{"Edit":{"inode":{"change":2,"pos":18},"path":"rtl/soc.sv","line":24,"atom":{"NewVertex":{"up_context":[{"change":2,"pos":388}],"down_context":[{"change":2,"pos":388}],"flag":"BLOCK","start":2277,"end":2339,"inode":{"change":2,"pos":18}}},"contents":[{"Add":" mem memory();"},{"Add":" mem_impl memory_impl(clk, memory.impl);"}]}},{"Edit":{"inode":{"change":2,"pos":18},"path":"rtl/soc.sv","line":27,"atom":{"EdgeMap":{"edges":[{"previous":"BLOCK","flag":"BLOCK | DELETED","from":{"change":2,"pos":389},"to":{"change":2,"start":389,"end":929},"introduced_by":2}],"inode":{"change":2,"pos":18}}},"contents":[{"Del":" // Memory\n struct {\n bit [3:0] wen;\n bit [31:0] addr;\n bit [31:0] rdata;\n bit [31:0] wdata;\n } mem;\n\n logic [31:0] memory [0:MEM_WORDS-1];\n\n always_ff @(posedge clk) begin\n mem.rdata <= memory[mem.addr];\n if (mem.wen[0]) memory[mem.addr][ 7: 0] <= mem.wdata[ 7: 0];\n\t\tif (mem.wen[1]) memory[mem.addr][15: 8] <= mem.wdata[15: 8];\n\t\tif (mem.wen[2]) memory[mem.addr][23:16] <= mem.wdata[23:16];\n\t\tif (mem.wen[3]) memory[mem.addr][31:24] <= mem.wdata[31:24];\n end\n // End Memory\n\n"}]}},{"Edit":{"inode":{"change":2,"pos":18},"path":"rtl/soc.sv","line":34,"atom":{"EdgeMap":{"edges":[{"previous":"BLOCK","flag":"BLOCK | DELETED","from":{"change":2,"pos":1196},"to":{"change":2,"start":1196,"end":1361},"introduced_by":2}],"inode":{"change":2,"pos":18}}},"contents":[{"Del":" end\n if ($value$plusargs(\"mem\", mem_file)) begin\n $display(\"[%0t] Initializing memory\\n\", $time);\n $readmemh(mem_file, memory);\n"}]}},{"FileAdd":{"meta":{"basename":"mem.sv","metadata":0},"context":[{"change":2,"pos":1}],"contents":[{"Add":"// SPDX-License-Identifier: CERN-OHL-S-2.0"},{"Add":""},{"Add":"// A simple valid-ready memory interface that can handle a single memory transfer at a time"},{"Add":""},{"Add":"`default_nettype none"},{"Add":"`timescale 1ps/1ps"},{"Add":""},{"Add":"// The core initiates a transfer by asserting valid, which stays high until the "},{"Add":"// peer asserts ready. All core outputs are stable over the valid period."},{"Add":"// If the transfer is an instruction fetch, the core asserts instr."},{"Add":"interface mem;"},{"Add":" bit valid; "},{"Add":" bit ready; "},{"Add":" bit instr;"},{"Add":""},{"Add":" enum bit[3:0] {"},{"Add":" READ = 'b0000,"},{"Add":" WRITE_BYTE0 = 'b0001,"},{"Add":" WRITE_BYTE1 = 'b0010,"},{"Add":" WRITE_BYTE2 = 'b0100,"},{"Add":" WRITE_BYTE3 = 'b1000,"},{"Add":" WRITE_HWORD0 = 'b0011,"},{"Add":" WRITE_HWORD1 = 'b1100,"},{"Add":" WRITE_WORD = 'b1111"},{"Add":" } mode;"},{"Add":""},{"Add":" wire [31:0] addr;"},{"Add":" wire [31:0] rdata;"},{"Add":" wire [31:0] wdata;"},{"Add":""},{"Add":" modport core ("},{"Add":" output valid,"},{"Add":" input ready,"},{"Add":" output instr,"},{"Add":" output mode, "},{"Add":" output addr,"},{"Add":" input rdata,"},{"Add":" output wdata"},{"Add":" );"},{"Add":""},{"Add":" modport impl ( "},{"Add":" input valid,"},{"Add":" output ready,"},{"Add":" input instr,"},{"Add":" input mode,"},{"Add":" input addr,"},{"Add":" output rdata,"},{"Add":" input wdata"},{"Add":" );"},{"Add":"endinterface"},{"Add":""},{"Add":"/* verilator lint_off DECLFILENAME */"},{"Add":"module mem_impl"},{"Add":"#("},{"Add":" parameter integer MEM_WORDS = 4096"},{"Add":")"},{"Add":"("},{"Add":" input bit clk,"},{"Add":""},{"Add":" mem.impl mem"},{"Add":");"},{"Add":""},{"Add":" logic [31:0] memory [0:MEM_WORDS-1];"},{"Add":" logic [3:0] wen = mem.mode;"},{"Add":""},{"Add":" always_ff @(posedge clk) begin"},{"Add":" mem.ready <= '0;"},{"Add":" "},{"Add":" if (mem.valid) begin"},{"Add":" mem.rdata <= memory[mem.addr]; "},{"Add":" if (wen[0]) memory[mem.addr][ 7: 0] <= mem.wdata[ 7: 0];"},{"Add":" if (wen[1]) memory[mem.addr][15: 8] <= mem.wdata[15: 8];"},{"Add":" if (wen[2]) memory[mem.addr][23:16] <= mem.wdata[23:16];"},{"Add":" if (wen[3]) memory[mem.addr][31:24] <= mem.wdata[31:24];"},{"Add":" end"},{"Add":" end"},{"Add":""},{"Add":""},{"Add":" // synthesis translate off"},{"Add":" logic [200:0] mem_file;"},{"Add":" initial begin"},{"Add":" if ($value$plusargs(\"mem\", mem_file)) begin"},{"Add":" $display(\"[%0t] Initializing memory\\n\", $time);"},{"Add":" $readmemh(mem_file, memory);"},{"Add":" end"},{"Add":" end"},{"Add":" "},{"Add":""},{"Add":" phys_mem_addr: assert property(@(posedge clk) mem.addr < (4*MEM_WORDS));"},{"Add":""},{"Add":" // synthesis translate on"},{"Add":"endmodule"}]}},{"Replacement":{"inode":{"change":2,"pos":1916},"path":"Makefile","line":22,"ins":{"up_context":[{"change":2,"pos":2565}],"down_context":[{"change":2,"pos":2581}],"flag":"BLOCK","start":2342,"end":2362,"inode":{"change":2,"pos":1916}},"del":{"edges":[{"previous":"BLOCK","flag":"BLOCK | DELETED","from":{"change":2,"pos":2565},"to":{"change":2,"start":2565,"end":2581},"introduced_by":2}],"inode":{"change":2,"pos":1916}},"ins_contents":[{"Add":"# Generate depfiles"}],"del_contents":[{"Del":"# Generate deps\n"}]}},{"Replacement":{"inode":{"change":2,"pos":1916},"path":"Makefile","line":43,"ins":{"up_context":[{"change":2,"pos":3209}],"down_context":[{"change":2,"pos":3253}],"flag":"BLOCK","start":2363,"end":2413,"inode":{"change":2,"pos":1916}},"del":{"edges":[{"previous":"BLOCK","flag":"BLOCK | DELETED","from":{"change":2,"pos":3209},"to":{"change":2,"start":3209,"end":3253},"introduced_by":2}],"inode":{"change":2,"pos":1916}},"ins_contents":[{"Add":"\t$(VERILATOR) $(VERILATOR_FLAGS) rtl/soc.sv -Irtl"}],"del_contents":[{"Del":"\t$(VERILATOR) $(VERILATOR_FLAGS) rtl/soc.sv\n"}]}}],"owner":"nuudlman","repo":"barrel","token":"PigOA6BF5KD13FZuxHaLt5Sp81QfULekhAm1HWQuY3Q=","login":null}

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