@LLVM_UNITTEST_SOURCE_DIR@

//===-- ContextCompressionTest.cpp -------------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
#include "../tools/llvm-profgen/ProfileGenerator.h"
#include "llvm/DebugInfo/Symbolize/SymbolizableModule.h"
#include "gtest/gtest.h"
using namespace llvm;
using namespace sampleprof;
TEST(TestCompression, TestNoSizeLimit1) {
  SmallVector<std::string, 16> Context = {"a", "b", "c", "a", "b", "c"};
  SmallVector<std::string, 16> Expect = {"a", "b", "c"};
  CSProfileGenerator::compressRecursionContext(Context, -1);
  EXPECT_TRUE(std::equal(Context.begin(), Context.end(), Expect.begin()));
}
TEST(TestCompression, TestNoSizeLimit2) {
  SmallVector<std::string, 16> Context = {"m", "a", "a", "b", "c", "a",
                                          "b", "c", "b", "c", "d"};
  SmallVector<std::string, 16> Expect = {"m", "a", "b", "c", "d"};
  CSProfileGenerator::compressRecursionContext(Context, -1);
  EXPECT_TRUE(std::equal(Context.begin(), Context.end(), Expect.begin()));
}
TEST(TestCompression, TestMaxDedupSize) {
  SmallVector<std::string, 16> Context = {"m", "a", "a", "b", "c", "a",
                                          "b", "c", "b", "c", "d"};
  SmallVector<std::string, 16> Expect = {"m", "a", "b", "c",
                                         "a", "b", "c", "d"};
  CSProfileGenerator::compressRecursionContext(Context, 2);
  EXPECT_TRUE(std::equal(Context.begin(), Context.end(), Expect.begin()));
}

set(LLVM_LINK_COMPONENTS
  Support
  )
add_llvm_unittest(LLVMProfgenTests
    ContextCompressionTest.cpp
  )
target_link_libraries(LLVMProfgenTests PRIVATE LLVMTestingSupport)
add_dependencies(LLVMProfgenTests intrinsics_gen)
set_property(TARGET LLVMProfgenTests PROPERTY FOLDER "Tests/UnitTests/ToolTests")

//===---- X86TestBase.h -----------------------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
// Test fixture common to all X86 MCA tests.
//===----------------------------------------------------------------------===//
#ifndef LLVM_UNITTESTS_TOOLS_LLVMMCA_X86_X86TESTBASE_H
#define LLVM_UNITTESTS_TOOLS_LLVMMCA_X86_X86TESTBASE_H
#include "MCATestBase.h"
#include "llvm/ADT/SmallVector.h"
namespace llvm {
namespace mca {
class X86TestBase : public MCATestBase {
protected:
  X86TestBase();
  void getSimpleInsts(SmallVectorImpl<MCInst> &Insts, unsigned Repeats = 1);
};
} // end namespace mca
} // end namespace llvm
#endif

#include "X86TestBase.h"
#include "MCTargetDesc/X86MCTargetDesc.h"
#include "llvm/MC/MCInstBuilder.h"
#include "llvm/Support/TargetSelect.h"
using namespace llvm;
using namespace mca;
X86TestBase::X86TestBase() : MCATestBase("x86_64-unknown-linux", "skylake") {
  LLVMInitializeX86TargetInfo();
  LLVMInitializeX86TargetMC();
  LLVMInitializeX86Target();
  LLVMInitializeX86AsmPrinter();
}
void X86TestBase::getSimpleInsts(SmallVectorImpl<MCInst> &Insts,
                                 unsigned Repeats) {
  for (unsigned i = 0U; i < Repeats; ++i) {
    // vmulps  %xmm0, %xmm1, %xmm2
    Insts.push_back(MCInstBuilder(X86::VMULPSrr)
                        .addReg(X86::XMM2)
                        .addReg(X86::XMM1)
                        .addReg(X86::XMM0));
    // vhaddps %xmm2, %xmm2, %xmm3
    Insts.push_back(MCInstBuilder(X86::VHADDPSrr)
                        .addReg(X86::XMM3)
                        .addReg(X86::XMM2)
                        .addReg(X86::XMM2));
    // vhaddps %xmm3, %xmm3, %xmm4
    Insts.push_back(MCInstBuilder(X86::VHADDPSrr)
                        .addReg(X86::XMM4)
                        .addReg(X86::XMM3)
                        .addReg(X86::XMM3));
  }
}

#include "Views/SummaryView.h"
#include "X86TestBase.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/MCA/CustomBehaviour.h"
#include "llvm/MCA/IncrementalSourceMgr.h"
#include "llvm/MCA/InstrBuilder.h"
#include "llvm/MCA/Pipeline.h"
#include "llvm/Support/Format.h"
#include "llvm/Support/JSON.h"
#include "llvm/Support/raw_ostream.h"
#include <unordered_map>
using namespace llvm;
using namespace mca;
TEST_F(X86TestBase, TestResumablePipeline) {
  mca::Context MCA(*MRI, *STI);
  mca::IncrementalSourceMgr ISM;
  // Empty CustomBehaviour.
  auto CB = std::make_unique<mca::CustomBehaviour>(*STI, ISM, *MCII);
  auto PO = getDefaultPipelineOptions();
  auto P = MCA.createDefaultPipeline(PO, ISM, *CB);
  ASSERT_TRUE(P);
  SmallVector<MCInst> MCIs;
  getSimpleInsts(MCIs, /*Repeats=*/100);
  // Add views.
  auto SV = std::make_unique<SummaryView>(STI->getSchedModel(), MCIs,
                                          PO.DispatchWidth);
  P->addEventListener(SV.get());
  mca::InstrBuilder IB(*STI, *MCII, *MRI, MCIA.get());
  // Tile size = 7
  for (unsigned i = 0U, E = MCIs.size(); i < E;) {
    for (unsigned TE = i + 7; i < TE && i < E; ++i) {
      Expected<std::unique_ptr<mca::Instruction>> InstOrErr =
          IB.createInstruction(MCIs[i]);
      ASSERT_TRUE(bool(InstOrErr));
      ISM.addInst(std::move(InstOrErr.get()));
    }
    // Run the pipeline.
    Expected<unsigned> Cycles = P->run();
    if (!Cycles) {
      // Should be a stream pause error.
      ASSERT_TRUE(Cycles.errorIsA<mca::InstStreamPause>());
      llvm::consumeError(Cycles.takeError());
    }
  }
  ISM.endOfStream();
  // Has to terminate properly.
  Expected<unsigned> Cycles = P->run();
  ASSERT_TRUE(bool(Cycles));
  json::Value Result = SV->toJSON();
  auto *ResultObj = Result.getAsObject();
  ASSERT_TRUE(ResultObj);
  // Run the baseline.
  json::Object BaselineResult;
  auto E = runBaselineMCA(BaselineResult, MCIs);
  ASSERT_FALSE(bool(E)) << "Failed to run baseline";
  auto *BaselineObj = BaselineResult.getObject(SV->getNameAsString());
  ASSERT_TRUE(BaselineObj) << "Does not contain SummaryView result";
  // Compare the results.
  constexpr const char *Fields[] = {"Instructions", "TotalCycles", "TotaluOps",
                                    "BlockRThroughput"};
  for (const auto *F : Fields) {
    auto V = ResultObj->getInteger(F);
    auto BV = BaselineObj->getInteger(F);
    ASSERT_TRUE(V && BV);
    ASSERT_EQ(*BV, *V) << "Value of '" << F << "' does not match";
  }
}
TEST_F(X86TestBase, TestInstructionRecycling) {
  mca::Context MCA(*MRI, *STI);
  std::unordered_map<const mca::InstrDesc *, SmallPtrSet<mca::Instruction *, 2>>
      RecycledInsts;
  auto GetRecycledInst = [&](const mca::InstrDesc &Desc) -> mca::Instruction * {
    auto It = RecycledInsts.find(&Desc);
    if (It != RecycledInsts.end()) {
      auto &Insts = It->second;
      if (Insts.size()) {
        mca::Instruction *I = *Insts.begin();
        Insts.erase(I);
        return I;
      }
    }
    return nullptr;
  };
  auto AddRecycledInst = [&](mca::Instruction *I) {
    const mca::InstrDesc &D = I->getDesc();
    RecycledInsts[&D].insert(I);
  };
  mca::IncrementalSourceMgr ISM;
  ISM.setOnInstFreedCallback(AddRecycledInst);
  // Empty CustomBehaviour.
  auto CB = std::make_unique<mca::CustomBehaviour>(*STI, ISM, *MCII);
  auto PO = getDefaultPipelineOptions();
  auto P = MCA.createDefaultPipeline(PO, ISM, *CB);
  ASSERT_TRUE(P);
  SmallVector<MCInst> MCIs;
  getSimpleInsts(MCIs, /*Repeats=*/100);
  // Add views.
  auto SV = std::make_unique<SummaryView>(STI->getSchedModel(), MCIs,
                                          PO.DispatchWidth);
  P->addEventListener(SV.get());
  mca::InstrBuilder IB(*STI, *MCII, *MRI, MCIA.get());
  IB.setInstRecycleCallback(GetRecycledInst);
  // Tile size = 7
  for (unsigned i = 0U, E = MCIs.size(); i < E;) {
    for (unsigned TE = i + 7; i < TE && i < E; ++i) {
      Expected<std::unique_ptr<mca::Instruction>> InstOrErr =
          IB.createInstruction(MCIs[i]);
      if (!InstOrErr) {
        mca::Instruction *RecycledInst = nullptr;
        // Check if the returned instruction is a recycled
        // one.
        auto RemainingE = handleErrors(InstOrErr.takeError(),
                                       [&](const mca::RecycledInstErr &RC) {
                                         RecycledInst = RC.getInst();
                                       });
        ASSERT_FALSE(bool(RemainingE));
        ASSERT_TRUE(RecycledInst);
        ISM.addRecycledInst(RecycledInst);
      } else {
        ISM.addInst(std::move(InstOrErr.get()));
      }
    }
    // Run the pipeline.
    Expected<unsigned> Cycles = P->run();
    if (!Cycles) {
      // Should be a stream pause error.
      ASSERT_TRUE(Cycles.errorIsA<mca::InstStreamPause>());
      llvm::consumeError(Cycles.takeError());
    }
  }
  ISM.endOfStream();
  // Has to terminate properly.
  Expected<unsigned> Cycles = P->run();
  ASSERT_TRUE(bool(Cycles));
  json::Value Result = SV->toJSON();
  auto *ResultObj = Result.getAsObject();
  ASSERT_TRUE(ResultObj);
  // Run the baseline.
  json::Object BaselineResult;
  auto E = runBaselineMCA(BaselineResult, MCIs);
  ASSERT_FALSE(bool(E)) << "Failed to run baseline";
  auto *BaselineObj = BaselineResult.getObject(SV->getNameAsString());
  ASSERT_TRUE(BaselineObj) << "Does not contain SummaryView result";
  // Compare the results.
  constexpr const char *Fields[] = {"Instructions", "TotalCycles", "TotaluOps",
                                    "BlockRThroughput"};
  for (const auto *F : Fields) {
    auto V = ResultObj->getInteger(F);
    auto BV = BaselineObj->getInteger(F);
    ASSERT_TRUE(V && BV);
    ASSERT_EQ(*BV, *V) << "Value of '" << F << "' does not match";
  }
}

add_llvm_mca_unittest_includes(
  ${LLVM_MAIN_SRC_DIR}/lib/Target/X86
  ${LLVM_BINARY_DIR}/lib/Target/X86
  )
add_llvm_mca_unittest_sources(
  TestIncrementalMCA.cpp
  X86TestBase.cpp
  )
add_llvm_mca_unittest_link_components(
  X86
  )

//===---- MCATestBase.h -----------------------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
// Test fixture common to all MCA tests.
//===----------------------------------------------------------------------===//
#ifndef LLVM_UNITTESTS_TOOLS_LLVMMCA_MCATESTBASE_H
#define LLVM_UNITTESTS_TOOLS_LLVMMCA_MCATESTBASE_H
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/Triple.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstPrinter.h"
#include "llvm/MC/MCInstrAnalysis.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCObjectFileInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MCTargetOptions.h"
#include "llvm/MC/SubtargetFeature.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/MCA/Context.h"
#include "gtest/gtest.h"
namespace llvm {
namespace json {
class Object;
} // end namespace json
namespace mca {
class View;
class MCATestBase : public ::testing::Test {
protected:
  // Note: Subclass ctors are expected to perform target-specific
  // initializations.
  MCATestBase(StringRef TripleStr, StringRef CPUName, StringRef MAttr = "")
      : TheTriple(TripleStr), CPUName(CPUName), MAttr(MAttr) {}
  /// Factory function to create a Target.
  virtual const Target *getLLVMTarget() const;
  /// Factory function to create a MCTargetOptions instance. Returns an
  /// empty one by default.
  virtual MCTargetOptions getMCTargetOptions() { return MCTargetOptions(); }
  const Target *TheTarget;
  const Triple TheTriple;
  StringRef CPUName;
  StringRef MAttr;
  // MC components.
  std::unique_ptr<MCSubtargetInfo> STI;
  std::unique_ptr<MCRegisterInfo> MRI;
  std::unique_ptr<MCAsmInfo> MAI;
  std::unique_ptr<MCObjectFileInfo> MOFI;
  std::unique_ptr<MCContext> Ctx;
  std::unique_ptr<MCInstrInfo> MCII;
  std::unique_ptr<MCInstrAnalysis> MCIA;
  std::unique_ptr<MCInstPrinter> IP;
  static mca::PipelineOptions getDefaultPipelineOptions();
  void SetUp() override;
  /// Utility function to run MCA with (nearly) the same configuration as the
  /// `llvm-mca` tool to verify result correctness.
  /// This function only displays on SummaryView by default.
  virtual Error runBaselineMCA(json::Object &Result, ArrayRef<MCInst> Insts,
                               ArrayRef<mca::View *> Views = None,
                               const mca::PipelineOptions *PO = nullptr);
};
} // end namespace mca
} // end namespace llvm
#endif

#include "MCATestBase.h"
#include "Views/SummaryView.h"
#include "llvm/MCA/CustomBehaviour.h"
#include "llvm/MCA/InstrBuilder.h"
#include "llvm/MCA/Pipeline.h"
#include "llvm/MCA/SourceMgr.h"
#include "llvm/MCA/View.h"
#include "llvm/Support/JSON.h"
#include "llvm/Support/WithColor.h"
#include <string>
using namespace llvm;
using namespace mca;
const Target *MCATestBase::getLLVMTarget() const {
  std::string Error;
  return TargetRegistry::lookupTarget(TheTriple.getTriple(), Error);
}
mca::PipelineOptions MCATestBase::getDefaultPipelineOptions() {
  mca::PipelineOptions PO(/*MicroOpQueue=*/0, /*DecoderThroughput=*/0,
                          /*DispatchWidth=*/0,
                          /*RegisterFileSize=*/0,
                          /*LoadQueueSize=*/0, /*StoreQueueSize=*/0,
                          /*AssumeNoAlias=*/true,
                          /*EnableBottleneckAnalysis=*/false);
  return PO;
}
void MCATestBase::SetUp() {
  TheTarget = getLLVMTarget();
  ASSERT_NE(TheTarget, nullptr);
  StringRef TripleName = TheTriple.getTriple();
  STI.reset(TheTarget->createMCSubtargetInfo(TripleName, CPUName, MAttr));
  ASSERT_TRUE(STI);
  ASSERT_TRUE(STI->isCPUStringValid(CPUName));
  MRI.reset(TheTarget->createMCRegInfo(TripleName));
  ASSERT_TRUE(MRI);
  auto MCOptions = getMCTargetOptions();
  MAI.reset(TheTarget->createMCAsmInfo(*MRI, TripleName, MCOptions));
  ASSERT_TRUE(MAI);
  Ctx = std::make_unique<MCContext>(TheTriple, MAI.get(), MRI.get(), STI.get());
  MOFI.reset(TheTarget->createMCObjectFileInfo(*Ctx, /*PIC=*/false));
  Ctx->setObjectFileInfo(MOFI.get());
  MCII.reset(TheTarget->createMCInstrInfo());
  ASSERT_TRUE(MCII);
  MCIA.reset(TheTarget->createMCInstrAnalysis(MCII.get()));
  ASSERT_TRUE(MCIA);
  IP.reset(TheTarget->createMCInstPrinter(TheTriple, /*AssemblerDialect=*/0,
                                          *MAI, *MCII, *MRI));
  ASSERT_TRUE(IP);
}
Error MCATestBase::runBaselineMCA(json::Object &Result, ArrayRef<MCInst> Insts,
                                  ArrayRef<mca::View *> Views,
                                  const mca::PipelineOptions *PO) {
  mca::Context MCA(*MRI, *STI);
  mca::InstrBuilder IB(*STI, *MCII, *MRI, MCIA.get());
  SmallVector<std::unique_ptr<mca::Instruction>> LoweredInsts;
  for (const auto &MCI : Insts) {
    Expected<std::unique_ptr<mca::Instruction>> Inst =
        IB.createInstruction(MCI);
    if (!Inst) {
      if (auto NewE =
              handleErrors(Inst.takeError(),
                           [this](const mca::InstructionError<MCInst> &IE) {
                             std::string InstructionStr;
                             raw_string_ostream SS(InstructionStr);
                             WithColor::error() << IE.Message << '\n';
                             IP->printInst(&IE.Inst, 0, "", *STI, SS);
                             WithColor::note()
                                 << "instruction: " << InstructionStr << '\n';
                           })) {
        // Default case.
        return NewE;
      }
    } else {
      LoweredInsts.emplace_back(std::move(Inst.get()));
    }
  }
  mca::CircularSourceMgr SM(LoweredInsts, /*Iterations=*/1);
  // Empty CustomBehaviour.
  auto CB = std::make_unique<mca::CustomBehaviour>(*STI, SM, *MCII);
  mca::PipelineOptions ThePO = PO ? *PO : getDefaultPipelineOptions();
  auto P = MCA.createDefaultPipeline(ThePO, SM, *CB);
  SmallVector<std::unique_ptr<mca::View>, 1> DefaultViews;
  if (Views.empty()) {
    // By default, we only add SummaryView.
    auto SV = std::make_unique<SummaryView>(STI->getSchedModel(), Insts,
                                            ThePO.DispatchWidth);
    P->addEventListener(SV.get());
    DefaultViews.emplace_back(std::move(SV));
  } else {
    for (auto *V : Views)
      P->addEventListener(V);
  }
  // Run the pipeline.
  Expected<unsigned> Cycles = P->run();
  if (!Cycles)
    return Cycles.takeError();
  for (const auto *V : Views)
    Result[V->getNameAsString()] = V->toJSON();
  for (const auto &V : DefaultViews)
    Result[V->getNameAsString()] = V->toJSON();
  return Error::success();
}

set(LLVM_LINK_COMPONENTS
  MC
  MCA
  Object
  Support
  )
set(mca_root ${LLVM_MAIN_SRC_DIR}/tools/llvm-mca)
set(mca_includes
  ${CMAKE_CURRENT_SOURCE_DIR}
  ${mca_root}
  )
# Right now we only need SummaryView.
set(mca_views_sources
  SummaryView.cpp
  )
list(TRANSFORM mca_views_sources PREPEND "${mca_root}/Views/")
set(mca_sources
  MCATestBase.cpp
  ${mca_views_sources}
  )
function(add_llvm_mca_unittest_includes)
  set(mca_includes ${mca_includes} ${ARGV} PARENT_SCOPE)
endfunction()
function(add_llvm_mca_unittest_sources)
  set(sources ${ARGV})
  list(TRANSFORM sources PREPEND "${CMAKE_CURRENT_LIST_DIR}/")
  set(mca_sources ${mca_sources} ${sources} PARENT_SCOPE)
endfunction()
function(add_llvm_mca_unittest_link_components comps)
  set(LLVM_LINK_COMPONENTS ${LLVM_LINK_COMPONENTS} ${ARGV} PARENT_SCOPE)
endfunction()
if(LLVM_TARGETS_TO_BUILD MATCHES "X86")
  include(X86/CMakeLists.txt)
endif()
list(REMOVE_DUPLICATES LLVM_LINK_COMPONENTS)
include_directories(${mca_includes})
add_llvm_target_unittest(LLVMMCATests
  ${mca_sources}
  )
set_property(TARGET LLVMMCATests PROPERTY FOLDER "Tests/UnitTests/ToolTests")

//===-- TestBase.h ----------------------------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
// Test fixture common to all X86 tests.
//===----------------------------------------------------------------------===//
#ifndef LLVM_UNITTESTS_TOOLS_LLVMEXEGESIS_X86_TESTBASE_H
#define LLVM_UNITTESTS_TOOLS_LLVMEXEGESIS_X86_TESTBASE_H
#include "LlvmState.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/TargetSelect.h"
#include "gmock/gmock.h"
#include "gtest/gtest.h"
namespace llvm {
namespace exegesis {
void InitializeX86ExegesisTarget();
class X86TestBase : public ::testing::Test {
protected:
  X86TestBase() : State("x86_64-unknown-linux", "haswell") {}
  static void SetUpTestCase() {
    LLVMInitializeX86TargetInfo();
    LLVMInitializeX86TargetMC();
    LLVMInitializeX86Target();
    LLVMInitializeX86AsmPrinter();
    LLVMInitializeX86AsmParser();
    InitializeX86ExegesisTarget();
  }
  const LLVMState State;
};
} // namespace exegesis
} // namespace llvm
#endif

//===-- TargetTest.cpp -----------------------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
#include "Target.h"
#include <cassert>
#include <memory>
#include "MCTargetDesc/X86MCTargetDesc.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/TargetSelect.h"
#include "gmock/gmock.h"
#include "gtest/gtest.h"
#include "llvm/MC/MCInstPrinter.h"
namespace llvm {
bool operator==(const MCOperand &a, const MCOperand &b) {
  if (a.isImm() && b.isImm())
    return a.getImm() == b.getImm();
  if (a.isReg() && b.isReg())
    return a.getReg() == b.getReg();
  return false;
}
bool operator==(const MCInst &a, const MCInst &b) {
  if (a.getOpcode() != b.getOpcode())
    return false;
  if (a.getNumOperands() != b.getNumOperands())
    return false;
  for (unsigned I = 0; I < a.getNumOperands(); ++I) {
    if (!(a.getOperand(I) == b.getOperand(I)))
      return false;
  }
  return true;
}
} // namespace llvm
namespace llvm {
namespace exegesis {
void InitializeX86ExegesisTarget();
namespace {
using testing::AllOf;
using testing::ElementsAre;
using testing::ElementsAreArray;
using testing::Eq;
using testing::Gt;
using testing::Matcher;
using testing::NotNull;
using testing::Property;
using testing::SizeIs;
Matcher<MCOperand> IsImm(int64_t Value) {
  return AllOf(Property(&MCOperand::isImm, Eq(true)),
               Property(&MCOperand::getImm, Eq(Value)));
}
Matcher<MCOperand> IsReg(unsigned Reg) {
  return AllOf(Property(&MCOperand::isReg, Eq(true)),
               Property(&MCOperand::getReg, Eq(Reg)));
}
Matcher<MCInst> OpcodeIs(unsigned Opcode) {
  return Property(&MCInst::getOpcode, Eq(Opcode));
}
Matcher<MCInst> IsMovImmediate(unsigned Opcode, int64_t Reg, int64_t Value) {
  return AllOf(OpcodeIs(Opcode), ElementsAre(IsReg(Reg), IsImm(Value)));
}
Matcher<MCInst> IsMovValueToStack(unsigned Opcode, int64_t Value,
                                  size_t Offset) {
  return AllOf(OpcodeIs(Opcode),
               ElementsAre(IsReg(X86::RSP), IsImm(1), IsReg(0), IsImm(Offset),
                           IsReg(0), IsImm(Value)));
}
Matcher<MCInst> IsMovValueFromStack(unsigned Opcode, unsigned Reg) {
  return AllOf(OpcodeIs(Opcode),
               ElementsAre(IsReg(Reg), IsReg(X86::RSP), IsImm(1), IsReg(0),
                           IsImm(0), IsReg(0)));
}
Matcher<MCInst> IsStackAllocate(unsigned Size) {
  return AllOf(OpcodeIs(X86::SUB64ri8),
               ElementsAre(IsReg(X86::RSP), IsReg(X86::RSP), IsImm(Size)));
}
Matcher<MCInst> IsStackDeallocate(unsigned Size) {
  return AllOf(OpcodeIs(X86::ADD64ri8),
               ElementsAre(IsReg(X86::RSP), IsReg(X86::RSP), IsImm(Size)));
}
constexpr const char kTriple[] = "x86_64-unknown-linux";
class X86TargetTest : public ::testing::Test {
protected:
  X86TargetTest(const char *Features) : State(kTriple, "core2", Features) {}
  static void SetUpTestCase() {
    LLVMInitializeX86TargetInfo();
    LLVMInitializeX86Target();
    LLVMInitializeX86TargetMC();
    InitializeX86ExegesisTarget();
  }
  std::vector<MCInst> setRegTo(unsigned Reg, const APInt &Value) {
    return State.getExegesisTarget().setRegTo(State.getSubtargetInfo(), Reg,
                                              Value);
  }
  const Instruction &getInstr(unsigned OpCode) {
    return State.getIC().getInstr(OpCode);
  }
  LLVMState State;
};
class X86Core2TargetTest : public X86TargetTest {
public:
  X86Core2TargetTest() : X86TargetTest("") {}
};
class X86Core2AvxTargetTest : public X86TargetTest {
public:
  X86Core2AvxTargetTest() : X86TargetTest("+avx") {}
};
class X86Core2Avx512TargetTest : public X86TargetTest {
public:
  X86Core2Avx512TargetTest() : X86TargetTest("+avx512vl") {}
};
TEST_F(X86Core2TargetTest, NoHighByteRegs) {
  EXPECT_TRUE(State.getRATC().reservedRegisters().test(X86::AH));
}
TEST_F(X86Core2TargetTest, SetFlags) {
  const unsigned Reg = X86::EFLAGS;
  EXPECT_THAT(setRegTo(Reg, APInt(64, 0x1111222233334444ULL)),
              ElementsAre(IsStackAllocate(8),
                          IsMovValueToStack(X86::MOV32mi, 0x33334444UL, 0),
                          IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 4),
                          OpcodeIs(X86::POPF64)));
}
TEST_F(X86Core2TargetTest, SetRegToGR8Value) {
  const uint8_t Value = 0xFFU;
  const unsigned Reg = X86::AL;
  EXPECT_THAT(setRegTo(Reg, APInt(8, Value)),
              ElementsAre(IsMovImmediate(X86::MOV8ri, Reg, Value)));
}
TEST_F(X86Core2TargetTest, SetRegToGR16Value) {
  const uint16_t Value = 0xFFFFU;
  const unsigned Reg = X86::BX;
  EXPECT_THAT(setRegTo(Reg, APInt(16, Value)),
              ElementsAre(IsMovImmediate(X86::MOV16ri, Reg, Value)));
}
TEST_F(X86Core2TargetTest, SetRegToGR32Value) {
  const uint32_t Value = 0x7FFFFU;
  const unsigned Reg = X86::ECX;
  EXPECT_THAT(setRegTo(Reg, APInt(32, Value)),
              ElementsAre(IsMovImmediate(X86::MOV32ri, Reg, Value)));
}
TEST_F(X86Core2TargetTest, SetRegToGR64Value) {
  const uint64_t Value = 0x7FFFFFFFFFFFFFFFULL;
  const unsigned Reg = X86::RDX;
  EXPECT_THAT(setRegTo(Reg, APInt(64, Value)),
              ElementsAre(IsMovImmediate(X86::MOV64ri, Reg, Value)));
}
TEST_F(X86Core2TargetTest, SetRegToVR64Value) {
  EXPECT_THAT(setRegTo(X86::MM0, APInt(64, 0x1111222233334444ULL)),
              ElementsAre(IsStackAllocate(8),
                          IsMovValueToStack(X86::MOV32mi, 0x33334444UL, 0),
                          IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 4),
                          IsMovValueFromStack(X86::MMX_MOVQ64rm, X86::MM0),
                          IsStackDeallocate(8)));
}
TEST_F(X86Core2TargetTest, SetRegToVR128Value_Use_MOVDQUrm) {
  EXPECT_THAT(
      setRegTo(X86::XMM0, APInt(128, "11112222333344445555666677778888", 16)),
      ElementsAre(IsStackAllocate(16),
                  IsMovValueToStack(X86::MOV32mi, 0x77778888UL, 0),
                  IsMovValueToStack(X86::MOV32mi, 0x55556666UL, 4),
                  IsMovValueToStack(X86::MOV32mi, 0x33334444UL, 8),
                  IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 12),
                  IsMovValueFromStack(X86::MOVDQUrm, X86::XMM0),
                  IsStackDeallocate(16)));
}
TEST_F(X86Core2AvxTargetTest, SetRegToVR128Value_Use_VMOVDQUrm) {
  EXPECT_THAT(
      setRegTo(X86::XMM0, APInt(128, "11112222333344445555666677778888", 16)),
      ElementsAre(IsStackAllocate(16),
                  IsMovValueToStack(X86::MOV32mi, 0x77778888UL, 0),
                  IsMovValueToStack(X86::MOV32mi, 0x55556666UL, 4),
                  IsMovValueToStack(X86::MOV32mi, 0x33334444UL, 8),
                  IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 12),
                  IsMovValueFromStack(X86::VMOVDQUrm, X86::XMM0),
                  IsStackDeallocate(16)));
}
TEST_F(X86Core2Avx512TargetTest, SetRegToVR128Value_Use_VMOVDQU32Z128rm) {
  EXPECT_THAT(
      setRegTo(X86::XMM0, APInt(128, "11112222333344445555666677778888", 16)),
      ElementsAre(IsStackAllocate(16),
                  IsMovValueToStack(X86::MOV32mi, 0x77778888UL, 0),
                  IsMovValueToStack(X86::MOV32mi, 0x55556666UL, 4),
                  IsMovValueToStack(X86::MOV32mi, 0x33334444UL, 8),
                  IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 12),
                  IsMovValueFromStack(X86::VMOVDQU32Z128rm, X86::XMM0),
                  IsStackDeallocate(16)));
}
TEST_F(X86Core2AvxTargetTest, SetRegToVR256Value_Use_VMOVDQUYrm) {
  const char ValueStr[] =
      "1111111122222222333333334444444455555555666666667777777788888888";
  EXPECT_THAT(
      setRegTo(X86::YMM0, APInt(256, ValueStr, 16)),
      ElementsAreArray({IsStackAllocate(32),
                        IsMovValueToStack(X86::MOV32mi, 0x88888888UL, 0),
                        IsMovValueToStack(X86::MOV32mi, 0x77777777UL, 4),
                        IsMovValueToStack(X86::MOV32mi, 0x66666666UL, 8),
                        IsMovValueToStack(X86::MOV32mi, 0x55555555UL, 12),
                        IsMovValueToStack(X86::MOV32mi, 0x44444444UL, 16),
                        IsMovValueToStack(X86::MOV32mi, 0x33333333UL, 20),
                        IsMovValueToStack(X86::MOV32mi, 0x22222222UL, 24),
                        IsMovValueToStack(X86::MOV32mi, 0x11111111UL, 28),
                        IsMovValueFromStack(X86::VMOVDQUYrm, X86::YMM0),
                        IsStackDeallocate(32)}));
}
TEST_F(X86Core2Avx512TargetTest, SetRegToVR256Value_Use_VMOVDQU32Z256rm) {
  const char ValueStr[] =
      "1111111122222222333333334444444455555555666666667777777788888888";
  EXPECT_THAT(
      setRegTo(X86::YMM0, APInt(256, ValueStr, 16)),
      ElementsAreArray({IsStackAllocate(32),
                        IsMovValueToStack(X86::MOV32mi, 0x88888888UL, 0),
                        IsMovValueToStack(X86::MOV32mi, 0x77777777UL, 4),
                        IsMovValueToStack(X86::MOV32mi, 0x66666666UL, 8),
                        IsMovValueToStack(X86::MOV32mi, 0x55555555UL, 12),
                        IsMovValueToStack(X86::MOV32mi, 0x44444444UL, 16),
                        IsMovValueToStack(X86::MOV32mi, 0x33333333UL, 20),
                        IsMovValueToStack(X86::MOV32mi, 0x22222222UL, 24),
                        IsMovValueToStack(X86::MOV32mi, 0x11111111UL, 28),
                        IsMovValueFromStack(X86::VMOVDQU32Z256rm, X86::YMM0),
                        IsStackDeallocate(32)}));
}
TEST_F(X86Core2Avx512TargetTest, SetRegToVR512Value) {
  const char ValueStr[] =
      "1111111122222222333333334444444455555555666666667777777788888888"
      "99999999AAAAAAAABBBBBBBBCCCCCCCCDDDDDDDDEEEEEEEEFFFFFFFF00000000";
  EXPECT_THAT(
      setRegTo(X86::ZMM0, APInt(512, ValueStr, 16)),
      ElementsAreArray({IsStackAllocate(64),
                        IsMovValueToStack(X86::MOV32mi, 0x00000000UL, 0),
                        IsMovValueToStack(X86::MOV32mi, 0xFFFFFFFFUL, 4),
                        IsMovValueToStack(X86::MOV32mi, 0xEEEEEEEEUL, 8),
                        IsMovValueToStack(X86::MOV32mi, 0xDDDDDDDDUL, 12),
                        IsMovValueToStack(X86::MOV32mi, 0xCCCCCCCCUL, 16),
                        IsMovValueToStack(X86::MOV32mi, 0xBBBBBBBBUL, 20),
                        IsMovValueToStack(X86::MOV32mi, 0xAAAAAAAAUL, 24),
                        IsMovValueToStack(X86::MOV32mi, 0x99999999UL, 28),
                        IsMovValueToStack(X86::MOV32mi, 0x88888888UL, 32),
                        IsMovValueToStack(X86::MOV32mi, 0x77777777UL, 36),
                        IsMovValueToStack(X86::MOV32mi, 0x66666666UL, 40),
                        IsMovValueToStack(X86::MOV32mi, 0x55555555UL, 44),
                        IsMovValueToStack(X86::MOV32mi, 0x44444444UL, 48),
                        IsMovValueToStack(X86::MOV32mi, 0x33333333UL, 52),
                        IsMovValueToStack(X86::MOV32mi, 0x22222222UL, 56),
                        IsMovValueToStack(X86::MOV32mi, 0x11111111UL, 60),
                        IsMovValueFromStack(X86::VMOVDQU32Zrm, X86::ZMM0),
                        IsStackDeallocate(64)}));
}
// Note: We always put 80 bits on the stack independently of the size of the
// value. This uses a bit more space but makes the code simpler.
TEST_F(X86Core2TargetTest, SetRegToST0_32Bits) {
  EXPECT_THAT(setRegTo(X86::ST0, APInt(32, 0x11112222ULL)),
              ElementsAre(IsStackAllocate(10),
                          IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 0),
                          IsMovValueToStack(X86::MOV32mi, 0x00000000UL, 4),
                          IsMovValueToStack(X86::MOV16mi, 0x0000UL, 8),
                          OpcodeIs(X86::LD_F80m), IsStackDeallocate(10)));
}
TEST_F(X86Core2TargetTest, SetRegToST1_32Bits) {
  const MCInst CopySt0ToSt1 = MCInstBuilder(X86::ST_Frr).addReg(X86::ST1);
  EXPECT_THAT(setRegTo(X86::ST1, APInt(32, 0x11112222ULL)),
              ElementsAre(IsStackAllocate(10),
                          IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 0),
                          IsMovValueToStack(X86::MOV32mi, 0x00000000UL, 4),
                          IsMovValueToStack(X86::MOV16mi, 0x0000UL, 8),
                          OpcodeIs(X86::LD_F80m), CopySt0ToSt1,
                          IsStackDeallocate(10)));
}
TEST_F(X86Core2TargetTest, SetRegToST0_64Bits) {
  EXPECT_THAT(setRegTo(X86::ST0, APInt(64, 0x1111222233334444ULL)),
              ElementsAre(IsStackAllocate(10),
                          IsMovValueToStack(X86::MOV32mi, 0x33334444UL, 0),
                          IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 4),
                          IsMovValueToStack(X86::MOV16mi, 0x0000UL, 8),
                          OpcodeIs(X86::LD_F80m), IsStackDeallocate(10)));
}
TEST_F(X86Core2TargetTest, SetRegToST0_80Bits) {
  EXPECT_THAT(setRegTo(X86::ST0, APInt(80, "11112222333344445555", 16)),
              ElementsAre(IsStackAllocate(10),
                          IsMovValueToStack(X86::MOV32mi, 0x44445555UL, 0),
                          IsMovValueToStack(X86::MOV32mi, 0x22223333UL, 4),
                          IsMovValueToStack(X86::MOV16mi, 0x1111UL, 8),
                          OpcodeIs(X86::LD_F80m), IsStackDeallocate(10)));
}
TEST_F(X86Core2TargetTest, SetRegToFP0_80Bits) {
  EXPECT_THAT(setRegTo(X86::FP0, APInt(80, "11112222333344445555", 16)),
              ElementsAre(IsStackAllocate(10),
                          IsMovValueToStack(X86::MOV32mi, 0x44445555UL, 0),
                          IsMovValueToStack(X86::MOV32mi, 0x22223333UL, 4),
                          IsMovValueToStack(X86::MOV16mi, 0x1111UL, 8),
                          OpcodeIs(X86::LD_Fp80m), IsStackDeallocate(10)));
}
TEST_F(X86Core2TargetTest, SetRegToFP1_32Bits) {
  EXPECT_THAT(setRegTo(X86::FP1, APInt(32, 0x11112222ULL)),
              ElementsAre(IsStackAllocate(10),
                          IsMovValueToStack(X86::MOV32mi, 0x11112222UL, 0),
                          IsMovValueToStack(X86::MOV32mi, 0x00000000UL, 4),
                          IsMovValueToStack(X86::MOV16mi, 0x0000UL, 8),
                          OpcodeIs(X86::LD_Fp80m), IsStackDeallocate(10)));
}
TEST_F(X86Core2TargetTest, SetRegToFP1_4Bits) {
  EXPECT_THAT(setRegTo(X86::FP1, APInt(4, 0x1ULL)),
              ElementsAre(IsStackAllocate(10),
                          IsMovValueToStack(X86::MOV32mi, 0x00000001UL, 0),
                          IsMovValueToStack(X86::MOV32mi, 0x00000000UL, 4),
                          IsMovValueToStack(X86::MOV16mi, 0x0000UL, 8),
                          OpcodeIs(X86::LD_Fp80m), IsStackDeallocate(10)));
}
TEST_F(X86Core2Avx512TargetTest, FillMemoryOperands_ADD64rm) {
  const Instruction &I = getInstr(X86::ADD64rm);
  InstructionTemplate IT(&I);
  constexpr const int kOffset = 42;
  State.getExegesisTarget().fillMemoryOperands(IT, X86::RDI, kOffset);
  // Memory is operands 2-6.
  EXPECT_THAT(IT.getValueFor(I.Operands[2]), IsReg(X86::RDI));
  EXPECT_THAT(IT.getValueFor(I.Operands[3]), IsImm(1));
  EXPECT_THAT(IT.getValueFor(I.Operands[4]), IsReg(0));
  EXPECT_THAT(IT.getValueFor(I.Operands[5]), IsImm(kOffset));
  EXPECT_THAT(IT.getValueFor(I.Operands[6]), IsReg(0));
}
TEST_F(X86Core2Avx512TargetTest, FillMemoryOperands_VGATHERDPSZ128rm) {
  const Instruction &I = getInstr(X86::VGATHERDPSZ128rm);
  InstructionTemplate IT(&I);
  constexpr const int kOffset = 42;
  State.getExegesisTarget().fillMemoryOperands(IT, X86::RDI, kOffset);
  // Memory is operands 4-8.
  EXPECT_THAT(IT.getValueFor(I.Operands[4]), IsReg(X86::RDI));
  EXPECT_THAT(IT.getValueFor(I.Operands[5]), IsImm(1));
  EXPECT_THAT(IT.getValueFor(I.Operands[6]), IsReg(0));
  EXPECT_THAT(IT.getValueFor(I.Operands[7]), IsImm(kOffset));
  EXPECT_THAT(IT.getValueFor(I.Operands[8]), IsReg(0));
}
TEST_F(X86Core2TargetTest, AllowAsBackToBack) {
  EXPECT_TRUE(
      State.getExegesisTarget().allowAsBackToBack(getInstr(X86::ADD64rr)));
  EXPECT_FALSE(
      State.getExegesisTarget().allowAsBackToBack(getInstr(X86::LEA64r)));
}
} // namespace
} // namespace exegesis
} // namespace llvm

//===-- SnippetRepetitorTest.cpp --------------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
#include "../Common/AssemblerUtils.h"
#include "LlvmState.h"
#include "MCInstrDescView.h"
#include "RegisterAliasing.h"
#include "TestBase.h"
#include "X86InstrInfo.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
namespace llvm {
namespace exegesis {
void InitializeX86ExegesisTarget();
namespace {
using testing::ElementsAre;
using testing::Eq;
using testing::Field;
using testing::Property;
using testing::UnorderedElementsAre;
class X86SnippetRepetitorTest : public X86TestBase {
protected:
  void SetUp() override {
    TM = State.createTargetMachine();
    Context = std::make_unique<LLVMContext>();
    Mod = std::make_unique<Module>("X86SnippetRepetitorTest", *Context);
    Mod->setDataLayout(TM->createDataLayout());
    MMI = std::make_unique<MachineModuleInfo>(TM.get());
    MF = &createVoidVoidPtrMachineFunction("TestFn", Mod.get(), MMI.get());
  }
  void TestCommon(InstructionBenchmark::RepetitionModeE RepetitionMode) {
    const auto Repetitor = SnippetRepetitor::Create(RepetitionMode, State);
    const std::vector<MCInst> Instructions = {MCInstBuilder(X86::NOOP)};
    FunctionFiller Sink(*MF, {X86::EAX});
    const auto Fill =
        Repetitor->Repeat(Instructions, kMinInstructions, kLoopBodySize);
    Fill(Sink);
  }
  static constexpr const unsigned kMinInstructions = 3;
  static constexpr const unsigned kLoopBodySize = 5;
  std::unique_ptr<LLVMTargetMachine> TM;
  std::unique_ptr<LLVMContext> Context;
  std::unique_ptr<Module> Mod;
  std::unique_ptr<MachineModuleInfo> MMI;
  MachineFunction *MF = nullptr;
};
static auto HasOpcode = [](unsigned Opcode) {
  return Property(&MachineInstr::getOpcode, Eq(Opcode));
};
static auto LiveReg = [](unsigned Reg) {
  return Field(&MachineBasicBlock::RegisterMaskPair::PhysReg, Eq(Reg));
};
TEST_F(X86SnippetRepetitorTest, Duplicate) {
  TestCommon(InstructionBenchmark::Duplicate);
  // Duplicating creates a single basic block that repeats the instructions.
  ASSERT_EQ(MF->getNumBlockIDs(), 1u);
  EXPECT_THAT(MF->getBlockNumbered(0)->instrs(),
              ElementsAre(HasOpcode(X86::NOOP), HasOpcode(X86::NOOP),
                          HasOpcode(X86::NOOP), HasOpcode(X86::RET64)));
}
TEST_F(X86SnippetRepetitorTest, Loop) {
  TestCommon(InstructionBenchmark::Loop);
  // Duplicating creates an entry block, a loop body and a ret block.
  ASSERT_EQ(MF->getNumBlockIDs(), 3u);
  const auto &LoopBlock = *MF->getBlockNumbered(1);
  EXPECT_THAT(LoopBlock.instrs(),
              ElementsAre(HasOpcode(X86::NOOP), HasOpcode(X86::NOOP),
                          HasOpcode(X86::NOOP), HasOpcode(X86::NOOP),
                          HasOpcode(X86::NOOP), HasOpcode(X86::ADD64ri8),
                          HasOpcode(X86::JCC_1)));
  EXPECT_THAT(LoopBlock.liveins(),
              UnorderedElementsAre(
                  LiveReg(X86::EAX),
                  LiveReg(State.getExegesisTarget().getLoopCounterRegister(
                      State.getTargetMachine().getTargetTriple()))));
  EXPECT_THAT(MF->getBlockNumbered(2)->instrs(),
              ElementsAre(HasOpcode(X86::RET64)));
}
} // namespace
} // namespace exegesis
} // namespace llvm

//===-- SnippetGeneratorTest.cpp --------------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
#include "../Common/AssemblerUtils.h"
#include "LlvmState.h"
#include "MCInstrDescView.h"
#include "ParallelSnippetGenerator.h"
#include "RegisterAliasing.h"
#include "SerialSnippetGenerator.h"
#include "TestBase.h"
#include "X86InstrInfo.h"
#include <unordered_set>
namespace llvm {
namespace exegesis {
void InitializeX86ExegesisTarget();
namespace {
using testing::AnyOf;
using testing::ElementsAre;
using testing::Gt;
using testing::HasSubstr;
using testing::Not;
using testing::SizeIs;
using testing::UnorderedElementsAre;
MATCHER(IsInvalid, "") { return !arg.isValid(); }
MATCHER(IsReg, "") { return arg.isReg(); }
template <typename SnippetGeneratorT>
class X86SnippetGeneratorTest : public X86TestBase {
protected:
  X86SnippetGeneratorTest() : Generator(State, SnippetGenerator::Options()),
	                      InstrInfo(State.getInstrInfo()) {}
  std::vector<CodeTemplate> checkAndGetCodeTemplates(unsigned Opcode) {
    randomGenerator().seed(0); // Initialize seed.
    const Instruction &Instr = State.getIC().getInstr(Opcode);
    auto CodeTemplateOrError = Generator.generateCodeTemplates(
        &Instr, State.getRATC().emptyRegisters());
    EXPECT_FALSE(CodeTemplateOrError.takeError()); // Valid configuration.
    return std::move(CodeTemplateOrError.get());
  }
  SnippetGeneratorT Generator;
  const MCInstrInfo &InstrInfo;
};
using X86SerialSnippetGeneratorTest = X86SnippetGeneratorTest<SerialSnippetGenerator>;
using X86ParallelSnippetGeneratorTest =
    X86SnippetGeneratorTest<ParallelSnippetGenerator>;
TEST_F(X86SerialSnippetGeneratorTest, ImplicitSelfDependencyThroughImplicitReg) {
  // - ADC16i16
  // - Op0 Explicit Use Immediate
  // - Op1 Implicit Def Reg(AX)
  // - Op2 Implicit Def Reg(EFLAGS)
  // - Op3 Implicit Use Reg(AX)
  // - Op4 Implicit Use Reg(EFLAGS)
  // - Var0 [Op0]
  // - hasAliasingImplicitRegisters (execution is always serial)
  // - hasAliasingRegisters
  const unsigned Opcode = X86::ADC16i16;
  EXPECT_THAT(InstrInfo.get(Opcode).getImplicitDefs()[0], X86::AX);
  EXPECT_THAT(InstrInfo.get(Opcode).getImplicitDefs()[1], X86::EFLAGS);
  EXPECT_THAT(InstrInfo.get(Opcode).getImplicitUses()[0], X86::AX);
  EXPECT_THAT(InstrInfo.get(Opcode).getImplicitUses()[1], X86::EFLAGS);
  const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
  ASSERT_THAT(CodeTemplates, SizeIs(1));
  const auto &CT = CodeTemplates[0];
  EXPECT_THAT(CT.Execution, ExecutionMode::ALWAYS_SERIAL_IMPLICIT_REGS_ALIAS);
  ASSERT_THAT(CT.Instructions, SizeIs(1));
  const InstructionTemplate &IT = CT.Instructions[0];
  EXPECT_THAT(IT.getOpcode(), Opcode);
  ASSERT_THAT(IT.getVariableValues(), SizeIs(1)); // Imm.
  EXPECT_THAT(IT.getVariableValues()[0], IsInvalid()) << "Immediate is not set";
}
TEST_F(X86SerialSnippetGeneratorTest, ImplicitSelfDependencyThroughTiedRegs) {
  // - ADD16ri
  // - Op0 Explicit Def RegClass(GR16)
  // - Op1 Explicit Use RegClass(GR16) TiedToOp0
  // - Op2 Explicit Use Immediate
  // - Op3 Implicit Def Reg(EFLAGS)
  // - Var0 [Op0,Op1]
  // - Var1 [Op2]
  // - hasTiedRegisters (execution is always serial)
  // - hasAliasingRegisters
  const unsigned Opcode = X86::ADD16ri;
  EXPECT_THAT(InstrInfo.get(Opcode).getImplicitDefs()[0], X86::EFLAGS);
  const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
  ASSERT_THAT(CodeTemplates, SizeIs(1));
  const auto &CT = CodeTemplates[0];
  EXPECT_THAT(CT.Execution, ExecutionMode::ALWAYS_SERIAL_TIED_REGS_ALIAS);
  ASSERT_THAT(CT.Instructions, SizeIs(1));
  const InstructionTemplate &IT = CT.Instructions[0];
  EXPECT_THAT(IT.getOpcode(), Opcode);
  ASSERT_THAT(IT.getVariableValues(), SizeIs(2));
  EXPECT_THAT(IT.getVariableValues()[0], IsInvalid()) << "Operand 1 is not set";
  EXPECT_THAT(IT.getVariableValues()[1], IsInvalid()) << "Operand 2 is not set";
}
TEST_F(X86SerialSnippetGeneratorTest, ImplicitSelfDependencyThroughExplicitRegs) {
  // - VXORPSrr
  // - Op0 Explicit Def RegClass(VR128)
  // - Op1 Explicit Use RegClass(VR128)
  // - Op2 Explicit Use RegClass(VR128)
  // - Var0 [Op0]
  // - Var1 [Op1]
  // - Var2 [Op2]
  // - hasAliasingRegisters
  const unsigned Opcode = X86::VXORPSrr;
  const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
  ASSERT_THAT(CodeTemplates, SizeIs(1));
  const auto &CT = CodeTemplates[0];
  EXPECT_THAT(CT.Execution, ExecutionMode::SERIAL_VIA_EXPLICIT_REGS);
  ASSERT_THAT(CT.Instructions, SizeIs(1));
  const InstructionTemplate &IT = CT.Instructions[0];
  EXPECT_THAT(IT.getOpcode(), Opcode);
  ASSERT_THAT(IT.getVariableValues(), SizeIs(3));
  EXPECT_THAT(IT.getVariableValues(),
              AnyOf(ElementsAre(IsReg(), IsInvalid(), IsReg()),
                    ElementsAre(IsReg(), IsReg(), IsInvalid())))
      << "Op0 is either set to Op1 or to Op2";
}
TEST_F(X86SerialSnippetGeneratorTest,
       ImplicitSelfDependencyThroughExplicitRegsForbidAll) {
  // - VXORPSrr
  // - Op0 Explicit Def RegClass(VR128)
  // - Op1 Explicit Use RegClass(VR128)
  // - Op2 Explicit Use RegClass(VR128)
  // - Var0 [Op0]
  // - Var1 [Op1]
  // - Var2 [Op2]
  // - hasAliasingRegisters
  const unsigned Opcode = X86::VXORPSrr;
  randomGenerator().seed(0); // Initialize seed.
  const Instruction &Instr = State.getIC().getInstr(Opcode);
  auto AllRegisters = State.getRATC().emptyRegisters();
  AllRegisters.flip();
  auto Error =
      Generator.generateCodeTemplates(&Instr, AllRegisters).takeError();
  EXPECT_TRUE((bool)Error);
  consumeError(std::move(Error));
}
TEST_F(X86SerialSnippetGeneratorTest, DependencyThroughOtherOpcode) {
  // - CMP64rr
  // - Op0 Explicit Use RegClass(GR64)
  // - Op1 Explicit Use RegClass(GR64)
  // - Op2 Implicit Def Reg(EFLAGS)
  // - Var0 [Op0]
  // - Var1 [Op1]
  const unsigned Opcode = X86::CMP64rr;
  const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
  ASSERT_THAT(CodeTemplates, SizeIs(Gt(1U))) << "Many templates are available";
  for (const auto &CT : CodeTemplates) {
    EXPECT_THAT(CT.Execution, ExecutionMode::SERIAL_VIA_NON_MEMORY_INSTR);
    ASSERT_THAT(CT.Instructions, SizeIs(2));
    const InstructionTemplate &IT = CT.Instructions[0];
    EXPECT_THAT(IT.getOpcode(), Opcode);
    ASSERT_THAT(IT.getVariableValues(), SizeIs(2));
    EXPECT_THAT(IT.getVariableValues(),
                AnyOf(ElementsAre(IsReg(), IsInvalid()),
                      ElementsAre(IsInvalid(), IsReg())));
    EXPECT_THAT(CT.Instructions[1].getOpcode(), Not(Opcode));
    // TODO: check that the two instructions alias each other.
  }
}
TEST_F(X86SerialSnippetGeneratorTest, LAHF) {
  // - LAHF
  // - Op0 Implicit Def Reg(AH)
  // - Op1 Implicit Use Reg(EFLAGS)
  const unsigned Opcode = X86::LAHF;
  const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
  ASSERT_THAT(CodeTemplates, SizeIs(Gt(1U))) << "Many templates are available";
  for (const auto &CT : CodeTemplates) {
    EXPECT_THAT(CT.Execution, ExecutionMode::SERIAL_VIA_NON_MEMORY_INSTR);
    ASSERT_THAT(CT.Instructions, SizeIs(2));
    const InstructionTemplate &IT = CT.Instructions[0];
    EXPECT_THAT(IT.getOpcode(), Opcode);
    ASSERT_THAT(IT.getVariableValues(), SizeIs(0));
  }
}
TEST_F(X86SerialSnippetGeneratorTest, VCVTUSI642SDZrrb_Int) {
  // - VCVTUSI642SDZrrb_Int
  // - Op0 Explicit Def RegClass(VR128X)
  // - Op1 Explicit Use RegClass(VR128X)
  // - Op2 Explicit Use STATIC_ROUNDING
  // - Op2 Explicit Use RegClass(GR64)
  // - Op4 Implicit Use Reg(MXSCR)
  const unsigned Opcode = X86::VCVTUSI642SDZrrb_Int;
  const Instruction &Instr = State.getIC().getInstr(Opcode);
  std::vector<BenchmarkCode> Configs;
  auto Error = Generator.generateConfigurations(
      &Instr, Configs, State.getRATC().emptyRegisters());
  ASSERT_FALSE(Error);
  ASSERT_THAT(Configs, SizeIs(1));
  const BenchmarkCode &BC = Configs[0];
  ASSERT_THAT(BC.Key.Instructions, SizeIs(1));
  ASSERT_TRUE(BC.Key.Instructions[0].getOperand(3).isImm());
}
TEST_F(X86ParallelSnippetGeneratorTest, SerialInstruction) {
  // - CDQ
  // - Op0 Implicit Def Reg(EAX)
  // - Op1 Implicit Def Reg(EDX)
  // - Op2 Implicit Use Reg(EAX)
  // - hasAliasingImplicitRegisters (execution is always serial)
  // - hasAliasingRegisters
  const unsigned Opcode = X86::CDQ;
  const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
  ASSERT_THAT(CodeTemplates, SizeIs(1));
  const auto &CT = CodeTemplates[0];
  EXPECT_THAT(CT.Info, HasSubstr("serial"));
  EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
  ASSERT_THAT(CT.Instructions, SizeIs(1));
  const InstructionTemplate &IT = CT.Instructions[0];
  EXPECT_THAT(IT.getOpcode(), Opcode);
  ASSERT_THAT(IT.getVariableValues(), SizeIs(0));
}
TEST_F(X86ParallelSnippetGeneratorTest, StaticRenaming) {
  // CMOV32rr has tied variables, we enumerate the possible values to execute
  // as many in parallel as possible.
  // - CMOV32rr
  // - Op0 Explicit Def RegClass(GR32)
  // - Op1 Explicit Use RegClass(GR32) TiedToOp0
  // - Op2 Explicit Use RegClass(GR32)
  // - Op3 Explicit Use Immediate
  // - Op3 Implicit Use Reg(EFLAGS)
  // - Var0 [Op0,Op1]
  // - Var1 [Op2]
  // - hasTiedRegisters (execution is always serial)
  // - hasAliasingRegisters
  const unsigned Opcode = X86::CMOV32rr;
  const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
  ASSERT_THAT(CodeTemplates, SizeIs(1));
  const auto &CT = CodeTemplates[0];
  EXPECT_THAT(CT.Info, HasSubstr("static renaming"));
  EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
  constexpr const unsigned kInstructionCount = 15;
  ASSERT_THAT(CT.Instructions, SizeIs(kInstructionCount));
  std::unordered_set<unsigned> AllDefRegisters;
  for (const auto &IT : CT.Instructions) {
    ASSERT_THAT(IT.getVariableValues(), SizeIs(3));
    AllDefRegisters.insert(IT.getVariableValues()[0].getReg());
  }
  EXPECT_THAT(AllDefRegisters, SizeIs(kInstructionCount))
      << "Each instruction writes to a different register";
}
TEST_F(X86ParallelSnippetGeneratorTest, NoTiedVariables) {
  // CMOV_GR32 has no tied variables, we make sure def and use are different
  // from each other.
  // - CMOV_GR32
  // - Op0 Explicit Def RegClass(GR32)
  // - Op1 Explicit Use RegClass(GR32)
  // - Op2 Explicit Use RegClass(GR32)
  // - Op3 Explicit Use Immediate
  // - Op4 Implicit Use Reg(EFLAGS)
  // - Var0 [Op0]
  // - Var1 [Op1]
  // - Var2 [Op2]
  // - Var3 [Op3]
  // - hasAliasingRegisters
  const unsigned Opcode = X86::CMOV_GR32;
  const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
  ASSERT_THAT(CodeTemplates, SizeIs(1));
  const auto &CT = CodeTemplates[0];
  EXPECT_THAT(CT.Info, HasSubstr("no tied variables"));
  EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
  ASSERT_THAT(CT.Instructions, SizeIs(1));
  const InstructionTemplate &IT = CT.Instructions[0];
  EXPECT_THAT(IT.getOpcode(), Opcode);
  ASSERT_THAT(IT.getVariableValues(), SizeIs(4));
  EXPECT_THAT(IT.getVariableValues()[0].getReg(),
              Not(IT.getVariableValues()[1].getReg()))
      << "Def is different from first Use";
  EXPECT_THAT(IT.getVariableValues()[0].getReg(),
              Not(IT.getVariableValues()[2].getReg()))
      << "Def is different from second Use";
  EXPECT_THAT(IT.getVariableValues()[3], IsInvalid());
}
TEST_F(X86ParallelSnippetGeneratorTest, MemoryUse) {
  // Mov32rm reads from memory.
  // - MOV32rm
  // - Op0 Explicit Def RegClass(GR32)
  // - Op1 Explicit Use Memory RegClass(GR8)
  // - Op2 Explicit Use Memory
  // - Op3 Explicit Use Memory RegClass(GRH8)
  // - Op4 Explicit Use Memory
  // - Op5 Explicit Use Memory RegClass(SEGMENT_REG)
  // - Var0 [Op0]
  // - Var1 [Op1]
  // - Var2 [Op2]
  // - Var3 [Op3]
  // - Var4 [Op4]
  // - Var5 [Op5]
  // - hasMemoryOperands
  // - hasAliasingRegisters
  const unsigned Opcode = X86::MOV32rm;
  const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
  ASSERT_THAT(CodeTemplates, SizeIs(1));
  const auto &CT = CodeTemplates[0];
  EXPECT_THAT(CT.Info, HasSubstr("no tied variables"));
  EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
  ASSERT_THAT(CT.Instructions,
              SizeIs(ParallelSnippetGenerator::kMinNumDifferentAddresses));
  const InstructionTemplate &IT = CT.Instructions[0];
  EXPECT_THAT(IT.getOpcode(), Opcode);
  ASSERT_THAT(IT.getVariableValues(), SizeIs(6));
  EXPECT_EQ(IT.getVariableValues()[2].getImm(), 1);
  EXPECT_EQ(IT.getVariableValues()[3].getReg(), 0u);
  EXPECT_EQ(IT.getVariableValues()[4].getImm(), 0);
  EXPECT_EQ(IT.getVariableValues()[5].getReg(), 0u);
}
TEST_F(X86ParallelSnippetGeneratorTest, MOV16ms) {
  const unsigned Opcode = X86::MOV16ms;
  const Instruction &Instr = State.getIC().getInstr(Opcode);
  std::vector<BenchmarkCode> Benchmarks;
  auto Err = Generator.generateConfigurations(&Instr, Benchmarks,
                                              State.getRATC().emptyRegisters());
  EXPECT_TRUE((bool)Err);
  EXPECT_THAT(toString(std::move(Err)),
              testing::HasSubstr("no available registers"));
}
TEST_F(X86ParallelSnippetGeneratorTest,
       AvoidSerializingThroughImplicitRegisters) {
  // MULX32rr implicitly uses EDX. We should not select that register to avoid
  // serialization.
  const unsigned Opcode = X86::MULX32rr;
  randomGenerator().seed(0); // Initialize seed.
  const Instruction &Instr = State.getIC().getInstr(Opcode);
  // Forbid all registers but RDX/EDX/DX/DH/DL. The only option would be to
  // choose that register, but that would serialize the instruction, so we
  // should be returning an error.
  auto AllRegisters = State.getRATC().emptyRegisters();
  AllRegisters.flip();
  AllRegisters.reset(X86::RDX);
  AllRegisters.reset(X86::EDX);
  AllRegisters.reset(X86::DX);
  AllRegisters.reset(X86::DH);
  AllRegisters.reset(X86::DL);
  auto Err = Generator.generateCodeTemplates(&Instr, AllRegisters);
  EXPECT_FALSE((bool)Err);
  EXPECT_THAT(toString(Err.takeError()),
              testing::HasSubstr("no available registers"));
}
class X86FakeSnippetGenerator : public SnippetGenerator {
public:
  X86FakeSnippetGenerator(const LLVMState &State, const Options &Opts)
      : SnippetGenerator(State, Opts) {}
  const Instruction &getInstr(unsigned Opcode) {
    return State.getIC().getInstr(Opcode);
  }
  InstructionTemplate getInstructionTemplate(unsigned Opcode) {
    return {&getInstr(Opcode)};
  }
private:
  Expected<std::vector<CodeTemplate>>
  generateCodeTemplates(InstructionTemplate, const BitVector &) const override {
    return make_error<StringError>("not implemented", inconvertibleErrorCode());
  }
};
using X86FakeSnippetGeneratorTest = X86SnippetGeneratorTest<X86FakeSnippetGenerator>;
testing::Matcher<const RegisterValue &> IsRegisterValue(unsigned Reg,
                                                        APInt Value) {
  return testing::AllOf(testing::Field(&RegisterValue::Register, Reg),
                        testing::Field(&RegisterValue::Value, Value));
}
TEST_F(X86FakeSnippetGeneratorTest, MemoryUse_Movsb) {
  // MOVSB writes to scratch memory register.
  // - MOVSB
  // - Op0 Explicit Use Memory RegClass(GR8)
  // - Op1 Explicit Use Memory RegClass(GR8)
  // - Op2 Explicit Use Memory RegClass(SEGMENT_REG)
  // - Op3 Implicit Def Reg(EDI)
  // - Op4 Implicit Def Reg(ESI)
  // - Op5 Implicit Use Reg(EDI)
  // - Op6 Implicit Use Reg(ESI)
  // - Op7 Implicit Use Reg(DF)
  // - Var0 [Op0]
  // - Var1 [Op1]
  // - Var2 [Op2]
  // - hasMemoryOperands
  // - hasAliasingImplicitRegisters (execution is always serial)
  // - hasAliasingRegisters
  const unsigned Opcode = X86::MOVSB;
  const Instruction &Instr = State.getIC().getInstr(Opcode);
  std::vector<BenchmarkCode> Benchmarks;
  auto Error = Generator.generateConfigurations(
      &Instr, Benchmarks, State.getRATC().emptyRegisters());
  EXPECT_TRUE((bool)Error);
  consumeError(std::move(Error));
}
TEST_F(X86FakeSnippetGeneratorTest, ComputeRegisterInitialValuesAdd16ri) {
  // ADD16ri:
  // explicit def 0       : reg RegClass=GR16
  // explicit use 1       : reg RegClass=GR16 | TIED_TO:0
  // explicit use 2       : imm
  // implicit def         : EFLAGS
  InstructionTemplate IT = Generator.getInstructionTemplate(X86::ADD16ri);
  IT.getValueFor(IT.getInstr().Variables[0]) = MCOperand::createReg(X86::AX);
  std::vector<InstructionTemplate> Snippet;
  Snippet.push_back(std::move(IT));
  const auto RIV = Generator.computeRegisterInitialValues(Snippet);
  EXPECT_THAT(RIV, ElementsAre(IsRegisterValue(X86::AX, APInt())));
}
TEST_F(X86FakeSnippetGeneratorTest, ComputeRegisterInitialValuesAdd64rr) {
  // ADD64rr:
  //  mov64ri rax, 42
  //  add64rr rax, rax, rbx
  // -> only rbx needs defining.
  std::vector<InstructionTemplate> Snippet;
  {
    InstructionTemplate Mov = Generator.getInstructionTemplate(X86::MOV64ri);
    Mov.getValueFor(Mov.getInstr().Variables[0]) =
        MCOperand::createReg(X86::RAX);
    Mov.getValueFor(Mov.getInstr().Variables[1]) = MCOperand::createImm(42);
    Snippet.push_back(std::move(Mov));
  }
  {
    InstructionTemplate Add = Generator.getInstructionTemplate(X86::ADD64rr);
    Add.getValueFor(Add.getInstr().Variables[0]) =
        MCOperand::createReg(X86::RAX);
    Add.getValueFor(Add.getInstr().Variables[1]) =
        MCOperand::createReg(X86::RBX);
    Snippet.push_back(std::move(Add));
  }
  const auto RIV = Generator.computeRegisterInitialValues(Snippet);
  EXPECT_THAT(RIV, ElementsAre(IsRegisterValue(X86::RBX, APInt())));
}
} // namespace
} // namespace exegesis
} // namespace llvm

//===-- SnippetFileTest.cpp -------------------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
#include "SnippetFile.h"
#include "LlvmState.h"
#include "TestBase.h"
#include "X86InstrInfo.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/Error.h"
#include "llvm/Support/FileSystem.h"
#include "llvm/Support/Path.h"
#include "llvm/Support/TargetSelect.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Testing/Support/SupportHelpers.h"
#include "gmock/gmock.h"
#include "gtest/gtest.h"
namespace llvm {
namespace exegesis {
void InitializeX86ExegesisTarget();
namespace {
using testing::AllOf;
using testing::ElementsAre;
using testing::Eq;
using testing::Field;
using testing::Property;
using testing::SizeIs;
using llvm::unittest::TempDir;
class X86SnippetFileTest : public X86TestBase {
protected:
  Expected<std::vector<BenchmarkCode>> TestCommon(StringRef Contents) {
    TempDir TestDirectory("SnippetFileTestDir", /*Unique*/ true);
    SmallString<64> Filename(TestDirectory.path());
    sys::path::append(Filename, "snippet.s");
    errs() << Filename << "-------\n";
    {
      std::error_code EC;
      raw_fd_ostream FOS(Filename, EC);
      FOS << Contents;
      EXPECT_FALSE(EC);
    }
    return readSnippets(State, Filename);
  }
};
// FIXME: Refactor these to ../Common/Matchers.h
static auto HasOpcode = [](unsigned Opcode) {
  return Property(&MCInst::getOpcode, Eq(Opcode));
};
MATCHER_P2(RegisterInitialValueIs, Reg, Val, "") {
  if (arg.Register == Reg &&
      arg.Value.getLimitedValue() == static_cast<uint64_t>(Val))
    return true;
  *result_listener << "expected: {" << Reg << ", " << Val << "} ";
  *result_listener << "actual: {" << arg.Register << ", "
                   << arg.Value.getLimitedValue() << "}";
  return false;
}
TEST_F(X86SnippetFileTest, Works) {
  auto Snippets = TestCommon(R"(
    # LLVM-EXEGESIS-DEFREG RAX 0f
    # LLVM-EXEGESIS-DEFREG SIL 0
    # LLVM-EXEGESIS-LIVEIN RDI
    # LLVM-EXEGESIS-LIVEIN DL
    incq %rax
  )");
  EXPECT_FALSE((bool)Snippets.takeError());
  ASSERT_THAT(*Snippets, SizeIs(1));
  const auto &Snippet = (*Snippets)[0];
  ASSERT_THAT(Snippet.Key.Instructions, ElementsAre(HasOpcode(X86::INC64r)));
  ASSERT_THAT(Snippet.Key.RegisterInitialValues,
              ElementsAre(RegisterInitialValueIs(X86::RAX, 15),
                          RegisterInitialValueIs(X86::SIL, 0)));
  ASSERT_THAT(Snippet.LiveIns, ElementsAre(X86::RDI, X86::DL));
}
TEST_F(X86SnippetFileTest, BadDefregParam) {
  auto Error = TestCommon(R"(
    # LLVM-EXEGESIS-DEFREG DOESNOEXIST 0
    incq %rax
  )")
                   .takeError();
  EXPECT_TRUE((bool)Error);
  consumeError(std::move(Error));
}
TEST_F(X86SnippetFileTest, NoDefregValue) {
  auto Error = TestCommon(R"(
    # LLVM-EXEGESIS-DEFREG RAX
    incq %rax
  )")
                   .takeError();
  EXPECT_TRUE((bool)Error);
  consumeError(std::move(Error));
}
TEST_F(X86SnippetFileTest, MissingParam) {
  auto Error = TestCommon(R"(
    # LLVM-EXEGESIS-LIVEIN
    incq %rax
  )")
                   .takeError();
  EXPECT_TRUE((bool)Error);
  consumeError(std::move(Error));
}
TEST_F(X86SnippetFileTest, NoAsmStreamer) {
  auto Snippets = TestCommon(R"(
    .cv_fpo_proc foo 4
  )");
  EXPECT_FALSE((bool)Snippets.takeError());
}
} // namespace
} // namespace exegesis
} // namespace llvm

//===-- SchedClassResolutionTest.cpp ----------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
#include "SchedClassResolution.h"
#include <cassert>
#include <memory>
#include "TestBase.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/TargetSelect.h"
#include "gmock/gmock.h"
#include "gtest/gtest.h"
namespace llvm {
namespace exegesis {
namespace {
using testing::Pair;
using testing::UnorderedElementsAre;
class X86SchedClassResolutionTest : public X86TestBase {
protected:
  X86SchedClassResolutionTest() : STI(State.getSubtargetInfo()) {
    // Compute the ProxResIdx of ports uses in tests.
    const auto &SM = STI.getSchedModel();
    for (unsigned I = 0, E = SM.getNumProcResourceKinds(); I < E; ++I) {
      const std::string Name = SM.getProcResource(I)->Name;
      if (Name == "HWPort0") {
        P0Idx = I;
      } else if (Name == "HWPort1") {
        P1Idx = I;
      } else if (Name == "HWPort5") {
        P5Idx = I;
      } else if (Name == "HWPort6") {
        P6Idx = I;
      } else if (Name == "HWPort05") {
        P05Idx = I;
      } else if (Name == "HWPort0156") {
        P0156Idx = I;
      }
    }
    EXPECT_NE(P0Idx, 0);
    EXPECT_NE(P1Idx, 0);
    EXPECT_NE(P5Idx, 0);
    EXPECT_NE(P6Idx, 0);
    EXPECT_NE(P05Idx, 0);
    EXPECT_NE(P0156Idx, 0);
  }
protected:
  const MCSubtargetInfo &STI;
  uint16_t P0Idx = 0;
  uint16_t P1Idx = 0;
  uint16_t P5Idx = 0;
  uint16_t P6Idx = 0;
  uint16_t P05Idx = 0;
  uint16_t P0156Idx = 0;
};
TEST_F(X86SchedClassResolutionTest, ComputeIdealizedProcResPressure_2P0) {
  const auto Pressure =
      computeIdealizedProcResPressure(STI.getSchedModel(), {{P0Idx, 2}});
  EXPECT_THAT(Pressure, UnorderedElementsAre(Pair(P0Idx, 2.0)));
}
TEST_F(X86SchedClassResolutionTest, ComputeIdealizedProcResPressure_2P05) {
  const auto Pressure =
      computeIdealizedProcResPressure(STI.getSchedModel(), {{P05Idx, 2}});
  EXPECT_THAT(Pressure,
              UnorderedElementsAre(Pair(P0Idx, 1.0), Pair(P5Idx, 1.0)));
}
TEST_F(X86SchedClassResolutionTest, ComputeIdealizedProcResPressure_2P05_2P0156) {
  const auto Pressure = computeIdealizedProcResPressure(
      STI.getSchedModel(), {{P05Idx, 2}, {P0156Idx, 2}});
  EXPECT_THAT(Pressure,
              UnorderedElementsAre(Pair(P0Idx, 1.0), Pair(P1Idx, 1.0),
                                   Pair(P5Idx, 1.0), Pair(P6Idx, 1.0)));
}
TEST_F(X86SchedClassResolutionTest,
       ComputeIdealizedProcResPressure_1P1_1P05_2P0156) {
  const auto Pressure = computeIdealizedProcResPressure(
      STI.getSchedModel(), {{P1Idx, 1}, {P05Idx, 1}, {P0156Idx, 2}});
  EXPECT_THAT(Pressure,
              UnorderedElementsAre(Pair(P0Idx, 1.0), Pair(P1Idx, 1.0),
                                   Pair(P5Idx, 1.0), Pair(P6Idx, 1.0)));
}
} // namespace
} // namespace exegesis
} // namespace llvm

//===-- X86RegisterAliasingTest.cpp --------------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
#include "RegisterAliasing.h"
#include <cassert>
#include <memory>
#include "TestBase.h"
#include "X86InstrInfo.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/TargetSelect.h"
#include "gmock/gmock.h"
#include "gtest/gtest.h"
namespace llvm {
namespace exegesis {
namespace {
class X86RegisterAliasingTest : public X86TestBase {};
TEST_F(X86RegisterAliasingTest, TrackSimpleRegister) {
  const auto &RegInfo = State.getRegInfo();
  const RegisterAliasingTracker tracker(RegInfo, X86::EAX);
  std::set<MCPhysReg> ActualAliasedRegisters;
  for (unsigned I : tracker.aliasedBits().set_bits())
    ActualAliasedRegisters.insert(static_cast<MCPhysReg>(I));
  const std::set<MCPhysReg> ExpectedAliasedRegisters = {
      X86::AL, X86::AH, X86::AX, X86::EAX, X86::HAX, X86::RAX};
  ASSERT_THAT(ActualAliasedRegisters, ExpectedAliasedRegisters);
  for (MCPhysReg aliased : ExpectedAliasedRegisters) {
    ASSERT_THAT(tracker.getOrigin(aliased), X86::EAX);
  }
}
TEST_F(X86RegisterAliasingTest, TrackRegisterClass) {
  // The alias bits for GR8_ABCD_LRegClassID are the union of the alias bits for
  // AL, BL, CL and DL.
  const auto &RegInfo = State.getRegInfo();
  const BitVector NoReservedReg(RegInfo.getNumRegs());
  const RegisterAliasingTracker RegClassTracker(
      RegInfo, NoReservedReg, RegInfo.getRegClass(X86::GR8_ABCD_LRegClassID));
  BitVector sum(RegInfo.getNumRegs());
  sum |= RegisterAliasingTracker(RegInfo, X86::AL).aliasedBits();
  sum |= RegisterAliasingTracker(RegInfo, X86::BL).aliasedBits();
  sum |= RegisterAliasingTracker(RegInfo, X86::CL).aliasedBits();
  sum |= RegisterAliasingTracker(RegInfo, X86::DL).aliasedBits();
  ASSERT_THAT(RegClassTracker.aliasedBits(), sum);
}
TEST_F(X86RegisterAliasingTest, TrackRegisterClassCache) {
  // Fetching twice the same tracker yields the same pointers.
  const auto &RegInfo = State.getRegInfo();
  const BitVector NoReservedReg(RegInfo.getNumRegs());
  RegisterAliasingTrackerCache Cache(RegInfo, NoReservedReg);
  ASSERT_THAT(&Cache.getRegister(X86::AX), &Cache.getRegister(X86::AX));
  ASSERT_THAT(&Cache.getRegisterClass(X86::GR8_ABCD_LRegClassID),
              &Cache.getRegisterClass(X86::GR8_ABCD_LRegClassID));
}
} // namespace
} // namespace exegesis
} // namespace llvm

add_llvm_exegesis_unittest_includes(
  ${LLVM_MAIN_SRC_DIR}/lib/Target/X86
  ${LLVM_BINARY_DIR}/lib/Target/X86
  ${LLVM_MAIN_SRC_DIR}/tools/llvm-exegesis/lib
  )
add_llvm_exegesis_unittest_sources(
  AssemblerTest.cpp
  BenchmarkResultTest.cpp
  RegisterAliasingTest.cpp
  SchedClassResolutionTest.cpp
  SnippetFileTest.cpp
  SnippetGeneratorTest.cpp
  SnippetRepetitorTest.cpp
  TargetTest.cpp
  )
add_llvm_exegesis_unittest_link_components(
  Core
  Codegen
  MC
  MCParser
  Object
  Support
  Symbolize
  X86
  )
add_llvm_exegesis_unittest_link_libraries(
  LLVMExegesisX86
  )

//===-- BenchmarkResultTest.cpp ---------------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
#include "BenchmarkResult.h"
#include "X86InstrInfo.h"
#include "llvm/ADT/SmallString.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/Error.h"
#include "llvm/Support/FileSystem.h"
#include "llvm/Support/Path.h"
#include "llvm/Support/TargetSelect.h"
#include "llvm/Support/YAMLTraits.h"
#include "llvm/Support/raw_ostream.h"
#include "gmock/gmock.h"
#include "gtest/gtest.h"
using ::testing::AllOf;
using ::testing::Eq;
using ::testing::get;
using ::testing::Pointwise;
using ::testing::Property;
namespace llvm {
namespace exegesis {
static std::string Dump(const MCInst &McInst) {
  std::string Buffer;
  raw_string_ostream OS(Buffer);
  McInst.print(OS);
  return Buffer;
}
MATCHER(EqMCInst, "") {
  const std::string Lhs = Dump(get<0>(arg));
  const std::string Rhs = Dump(get<1>(arg));
  if (Lhs != Rhs) {
    *result_listener << Lhs << " <=> " << Rhs;
    return false;
  }
  return true;
}
namespace {
TEST(BenchmarkResultTest, WriteToAndReadFromDisk) {
  LLVMInitializeX86TargetInfo();
  LLVMInitializeX86Target();
  LLVMInitializeX86TargetMC();
  // Read benchmarks.
  const LLVMState State("x86_64-unknown-linux", "haswell");
  ExitOnError ExitOnErr;
  InstructionBenchmark ToDisk;
  ToDisk.Key.Instructions.push_back(MCInstBuilder(X86::XOR32rr)
                                        .addReg(X86::AL)
                                        .addReg(X86::AH)
                                        .addImm(123)
                                        .addDFPImm(bit_cast<uint64_t>(0.5)));
  ToDisk.Key.Config = "config";
  ToDisk.Key.RegisterInitialValues = {
      RegisterValue{X86::AL, APInt(8, "-1", 10)},
      RegisterValue{X86::AH, APInt(8, "123", 10)}};
  ToDisk.Mode = InstructionBenchmark::Latency;
  ToDisk.CpuName = "cpu_name";
  ToDisk.LLVMTriple = "llvm_triple";
  ToDisk.NumRepetitions = 1;
  ToDisk.Measurements.push_back(BenchmarkMeasure{"a", 1, 1});
  ToDisk.Measurements.push_back(BenchmarkMeasure{"b", 2, 2});
  ToDisk.Error = "error";
  ToDisk.Info = "info";
  SmallString<64> Filename;
  std::error_code EC;
  EC = sys::fs::createUniqueDirectory("BenchmarkResultTestDir", Filename);
  ASSERT_FALSE(EC);
  sys::path::append(Filename, "data.yaml");
  errs() << Filename << "-------\n";
  ExitOnErr(ToDisk.writeYaml(State, Filename));
  {
    // One-element version.
    const auto FromDisk =
        ExitOnErr(InstructionBenchmark::readYaml(State, Filename));
    EXPECT_THAT(FromDisk.Key.Instructions,
                Pointwise(EqMCInst(), ToDisk.Key.Instructions));
    EXPECT_EQ(FromDisk.Key.Config, ToDisk.Key.Config);
    EXPECT_EQ(FromDisk.Mode, ToDisk.Mode);
    EXPECT_EQ(FromDisk.CpuName, ToDisk.CpuName);
    EXPECT_EQ(FromDisk.LLVMTriple, ToDisk.LLVMTriple);
    EXPECT_EQ(FromDisk.NumRepetitions, ToDisk.NumRepetitions);
    EXPECT_THAT(FromDisk.Measurements, ToDisk.Measurements);
    EXPECT_THAT(FromDisk.Error, ToDisk.Error);
    EXPECT_EQ(FromDisk.Info, ToDisk.Info);
  }
  {
    // Vector version.
    const auto FromDiskVector =
        ExitOnErr(InstructionBenchmark::readYamls(State, Filename));
    ASSERT_EQ(FromDiskVector.size(), size_t{1});
    const auto FromDisk = FromDiskVector[0];
    EXPECT_THAT(FromDisk.Key.Instructions,
                Pointwise(EqMCInst(), ToDisk.Key.Instructions));
    EXPECT_EQ(FromDisk.Key.Config, ToDisk.Key.Config);
    EXPECT_EQ(FromDisk.Mode, ToDisk.Mode);
    EXPECT_EQ(FromDisk.CpuName, ToDisk.CpuName);
    EXPECT_EQ(FromDisk.LLVMTriple, ToDisk.LLVMTriple);
    EXPECT_EQ(FromDisk.NumRepetitions, ToDisk.NumRepetitions);
    EXPECT_THAT(FromDisk.Measurements, ToDisk.Measurements);
    EXPECT_THAT(FromDisk.Error, ToDisk.Error);
    EXPECT_EQ(FromDisk.Info, ToDisk.Info);
  }
}
TEST(BenchmarkResultTest, PerInstructionStats) {
  PerInstructionStats Stats;
  Stats.push(BenchmarkMeasure{"a", 0.5, 0.0});
  Stats.push(BenchmarkMeasure{"a", 1.5, 0.0});
  Stats.push(BenchmarkMeasure{"a", -1.0, 0.0});
  Stats.push(BenchmarkMeasure{"a", 0.0, 0.0});
  EXPECT_EQ(Stats.min(), -1.0);
  EXPECT_EQ(Stats.max(), 1.5);
  EXPECT_EQ(Stats.avg(), 0.25); // (0.5+1.5-1.0+0.0) / 4
}
} // namespace
} // namespace exegesis
} // namespace llvm

//===-- AssemblerTest.cpp ---------------------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
#include "../Common/AssemblerUtils.h"
#include "X86InstrInfo.h"
namespace llvm {
namespace exegesis {
void InitializeX86ExegesisTarget();
namespace {
using X86::EAX;
using X86::MOV32ri;
using X86::MOV64ri32;
using X86::RAX;
using X86::XOR32rr;
class X86MachineFunctionGeneratorTest
    : public MachineFunctionGeneratorBaseTest {
protected:
  X86MachineFunctionGeneratorTest()
      : MachineFunctionGeneratorBaseTest("x86_64-unknown-linux", "haswell") {}
  static void SetUpTestCase() {
    LLVMInitializeX86TargetInfo();
    LLVMInitializeX86TargetMC();
    LLVMInitializeX86Target();
    LLVMInitializeX86AsmPrinter();
    InitializeX86ExegesisTarget();
  }
};
TEST_F(X86MachineFunctionGeneratorTest, DISABLED_JitFunction) {
  Check({}, MCInst(), 0xc3);
}
TEST_F(X86MachineFunctionGeneratorTest, DISABLED_JitFunctionXOR32rr_X86) {
  Check({{EAX, APInt(32, 1)}},
        MCInstBuilder(XOR32rr).addReg(EAX).addReg(EAX).addReg(EAX),
        // mov eax, 1
        0xb8, 0x01, 0x00, 0x00, 0x00,
        // xor eax, eax
        0x31, 0xc0, 0xc3);
}
TEST_F(X86MachineFunctionGeneratorTest, DISABLED_JitFunctionMOV64ri) {
  Check({}, MCInstBuilder(MOV64ri32).addReg(RAX).addImm(42), 0x48, 0xc7, 0xc0,
        0x2a, 0x00, 0x00, 0x00, 0xc3);
}
TEST_F(X86MachineFunctionGeneratorTest, DISABLED_JitFunctionMOV32ri) {
  Check({}, MCInstBuilder(MOV32ri).addReg(EAX).addImm(42), 0xb8, 0x2a, 0x00,
        0x00, 0x00, 0xc3);
}
} // namespace
} // namespace exegesis
} // namespace llvm

//===-- RegisterValueTest.cpp -----------------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
#include "RegisterValue.h"
#include "gmock/gmock.h"
#include "gtest/gtest.h"
namespace llvm {
namespace exegesis {
namespace {
#define CHECK(EXPECTED, ACTUAL)                                                \
  EXPECT_EQ(APInt(SizeInBits, EXPECTED, 16),                                   \
            bitcastFloatValue(Semantic, PredefinedValues::ACTUAL))
TEST(RegisterValueTest, Half) {
  const size_t SizeInBits = 16;
  const auto &Semantic = APFloatBase::IEEEhalf();
  CHECK("0000", POS_ZERO);
  CHECK("8000", NEG_ZERO);
  CHECK("3C00", ONE);
  CHECK("4000", TWO);
  CHECK("7C00", INF);
  CHECK("7E00", QNAN);
  CHECK("7BFF", LARGEST);
  CHECK("0400", SMALLEST_NORM);
  CHECK("0001", SMALLEST);
  CHECK("0001", ULP);
  CHECK("3C01", ONE_PLUS_ULP);
}
TEST(RegisterValueTest, Single) {
  const size_t SizeInBits = 32;
  const auto &Semantic = APFloatBase::IEEEsingle();
  CHECK("00000000", POS_ZERO);
  CHECK("80000000", NEG_ZERO);
  CHECK("3F800000", ONE);
  CHECK("40000000", TWO);
  CHECK("7F800000", INF);
  CHECK("7FC00000", QNAN);
  CHECK("7F7FFFFF", LARGEST);
  CHECK("00800000", SMALLEST_NORM);
  CHECK("00000001", SMALLEST);
  CHECK("00000001", ULP);
  CHECK("3F800001", ONE_PLUS_ULP);
}
TEST(RegisterValueTest, Double) {
  const size_t SizeInBits = 64;
  const auto &Semantic = APFloatBase::IEEEdouble();
  CHECK("0000000000000000", POS_ZERO);
  CHECK("8000000000000000", NEG_ZERO);
  CHECK("3FF0000000000000", ONE);
  CHECK("4000000000000000", TWO);
  CHECK("7FF0000000000000", INF);
  CHECK("7FF8000000000000", QNAN);
  CHECK("7FEFFFFFFFFFFFFF", LARGEST);
  CHECK("0010000000000000", SMALLEST_NORM);
  CHECK("0000000000000001", SMALLEST);
  CHECK("0000000000000001", ULP);
  CHECK("3FF0000000000001", ONE_PLUS_ULP);
}
} // namespace
} // namespace exegesis
} // namespace llvm

//===-- TestBase.h ----------------------------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
// Test fixture common to all PowerPC tests.
//===----------------------------------------------------------------------===//
#ifndef LLVM_UNITTESTS_TOOLS_LLVMEXEGESIS_POWERPC_TESTBASE_H
#define LLVM_UNITTESTS_TOOLS_LLVMEXEGESIS_POWERPC_TESTBASE_H
#include "LlvmState.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/TargetSelect.h"
#include "gmock/gmock.h"
#include "gtest/gtest.h"
namespace llvm {
namespace exegesis {
void InitializePowerPCExegesisTarget();
class PPCTestBase : public ::testing::Test {
protected:
  PPCTestBase() : State("powerpc64le-unknown-linux", "ppc64le") {}
  static void SetUpTestCase() {
    LLVMInitializePowerPCTargetInfo();
    LLVMInitializePowerPCTargetMC();
    LLVMInitializePowerPCTarget();
    InitializePowerPCExegesisTarget();
  }
  const LLVMState State;
};
} // namespace exegesis
} // namespace llvm
#endif

//===-- TargetTest.cpp ---------------------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
#include "Target.h"
#include <cassert>
#include <memory>
#include "MCTargetDesc/PPCMCTargetDesc.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/TargetSelect.h"
#include "gmock/gmock.h"
#include "gtest/gtest.h"
namespace llvm{
namespace exegesis {
void InitializePowerPCExegesisTarget();
namespace {
using testing::NotNull;
using testing::IsEmpty;
using testing::Not;
constexpr const char kTriple[] = "powerpc64le-unknown-linux";
class PowerPCTargetTest : public ::testing::Test {
protected:
  PowerPCTargetTest()
      : ExegesisTarget_(ExegesisTarget::lookup(Triple(kTriple))) {
    EXPECT_THAT(ExegesisTarget_, NotNull());
    std::string error;
    Target_ = TargetRegistry::lookupTarget(kTriple, error);
    EXPECT_THAT(Target_, NotNull());
  }
  static void SetUpTestCase() {
    LLVMInitializePowerPCTargetInfo();
    LLVMInitializePowerPCTarget();
    LLVMInitializePowerPCTargetMC();
    InitializePowerPCExegesisTarget();
  }
  const Target *Target_;
  const ExegesisTarget *const ExegesisTarget_;
};
TEST_F(PowerPCTargetTest, SetRegToConstant) {
  const std::unique_ptr<MCSubtargetInfo> STI(
      Target_->createMCSubtargetInfo(kTriple, "generic", ""));
  const auto Insts = ExegesisTarget_->setRegTo(*STI, PPC::X0, APInt());
  EXPECT_THAT(Insts, Not(IsEmpty()));
}
TEST_F(PowerPCTargetTest, DefaultPfmCounters) {
  const std::string Expected = "CYCLES";
  EXPECT_EQ(ExegesisTarget_->getPfmCounters("").CycleCounter, Expected);
  EXPECT_EQ(ExegesisTarget_->getPfmCounters("unknown_cpu").CycleCounter,
            Expected);
}
} // namespace
} // namespace exegesis
} // namespace llvm

//===-- SnippetGeneratorTest.cpp --------------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
#include "../Common/AssemblerUtils.h"
#include "LlvmState.h"
#include "MCInstrDescView.h"
#include "PPCInstrInfo.h"
#include "ParallelSnippetGenerator.h"
#include "RegisterAliasing.h"
#include "SerialSnippetGenerator.h"
#include "TestBase.h"
#include <unordered_set>
namespace llvm {
namespace exegesis {
namespace {
using testing::AnyOf;
using testing::ElementsAre;
using testing::HasSubstr;
using testing::SizeIs;
MATCHER(IsInvalid, "") { return !arg.isValid(); }
MATCHER(IsReg, "") { return arg.isReg(); }
template <typename SnippetGeneratorT>
class PPCSnippetGeneratorTest : public PPCTestBase {
protected:
  PPCSnippetGeneratorTest() : Generator(State, SnippetGenerator::Options()) {}
  std::vector<CodeTemplate> checkAndGetCodeTemplates(unsigned Opcode) {
    randomGenerator().seed(0); // Initialize seed.
    const Instruction &Instr = State.getIC().getInstr(Opcode);
    auto CodeTemplateOrError = Generator.generateCodeTemplates(
        &Instr, State.getRATC().emptyRegisters());
    EXPECT_FALSE(CodeTemplateOrError.takeError()); // Valid configuration.
    return std::move(CodeTemplateOrError.get());
  }
  SnippetGeneratorT Generator;
};
using PPCSerialSnippetGeneratorTest = PPCSnippetGeneratorTest<SerialSnippetGenerator>;
using PPCParallelSnippetGeneratorTest =
    PPCSnippetGeneratorTest<ParallelSnippetGenerator>;
TEST_F(PPCSerialSnippetGeneratorTest, ImplicitSelfDependencyThroughExplicitRegs) {
  // - ADD8
  // - Op0 Explicit Def RegClass(G8RC)
  // - Op1 Explicit Use RegClass(G8RC)
  // - Op2 Explicit Use RegClass(G8RC)
  // - Var0 [Op0]
  // - Var1 [Op1]
  // - Var2 [Op2]
  // - hasAliasingRegisters
  const unsigned Opcode = PPC::ADD8;
  const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
  ASSERT_THAT(CodeTemplates, SizeIs(1));
  const auto &CT = CodeTemplates[0];
  EXPECT_THAT(CT.Execution, ExecutionMode::SERIAL_VIA_EXPLICIT_REGS);
  ASSERT_THAT(CT.Instructions, SizeIs(1));
  const InstructionTemplate &IT = CT.Instructions[0];
  EXPECT_THAT(IT.getOpcode(), Opcode);
  ASSERT_THAT(IT.getVariableValues(), SizeIs(3));
  EXPECT_THAT(IT.getVariableValues(),
              AnyOf(ElementsAre(IsReg(), IsInvalid(), IsReg()),
                    ElementsAre(IsReg(), IsReg(), IsInvalid())))
      << "Op0 is either set to Op1 or to Op2";
}
TEST_F(PPCSerialSnippetGeneratorTest, ImplicitSelfDependencyThroughTiedRegs) {
  // - RLDIMI
  // - Op0 Explicit Def RegClass(G8RC)
  // - Op1 Explicit Use RegClass(G8RC) TiedToOp0
  // - Op2 Explicit Use RegClass(G8RC)
  // - Op3 Explicit Use Immediate
  // - Op4 Explicit Use Immediate
  // - Var0 [Op0,Op1]
  // - Var1 [Op2]
  // - Var2 [Op3]
  // - Var3 [Op4]
  // - hasTiedRegisters (execution is always serial)
  // - hasAliasingRegisters
  // - RLDIMI
  const unsigned Opcode = PPC::RLDIMI;
  const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
  ASSERT_THAT(CodeTemplates, SizeIs(1));
  const auto &CT = CodeTemplates[0];
  EXPECT_THAT(CT.Execution, ExecutionMode::ALWAYS_SERIAL_TIED_REGS_ALIAS);
  ASSERT_THAT(CT.Instructions, SizeIs(1));
  const InstructionTemplate &IT = CT.Instructions[0];
  EXPECT_THAT(IT.getOpcode(), Opcode);
  ASSERT_THAT(IT.getVariableValues(), SizeIs(4));
  EXPECT_THAT(IT.getVariableValues()[2], IsInvalid()) << "Operand 1 is not set";
  EXPECT_THAT(IT.getVariableValues()[3], IsInvalid()) << "Operand 2 is not set";
}
TEST_F(PPCParallelSnippetGeneratorTest, MemoryUse) {
  // - LDX
  // - Op0 Explicit Def RegClass(G8RC)
  // - Op1 Explicit Use Memory RegClass(GPRC)
  // - Op2 Explicit Use Memory RegClass(VSSRC)
  // - Var0 [Op0]
  // - Var1 [Op1]
  // - Var2 [Op2]
  // - hasMemoryOperands
  // - hasAliasingRegisters
  const unsigned Opcode = PPC::LDX;
  const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
  ASSERT_THAT(CodeTemplates, SizeIs(1));
  const auto &CT = CodeTemplates[0];
  EXPECT_THAT(CT.Info, HasSubstr("instruction has no tied variables picking "
                                 "Uses different from defs"));
  EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
  ASSERT_THAT(CT.Instructions,
              SizeIs(ParallelSnippetGenerator::kMinNumDifferentAddresses));
  const InstructionTemplate &IT = CT.Instructions[0];
  EXPECT_THAT(IT.getOpcode(), Opcode);
  ASSERT_THAT(IT.getVariableValues(), SizeIs(3));
  EXPECT_EQ(IT.getVariableValues()[1].getReg(), PPC::X1);
  EXPECT_EQ(IT.getVariableValues()[2].getReg(), PPC::X13);
}
} // namespace
} // namespace exegesis
} // namespace llvm

add_llvm_exegesis_unittest_includes(
  ${LLVM_MAIN_SRC_DIR}/lib/Target/PowerPC
  ${LLVM_BINARY_DIR}/lib/Target/PowerPC
  ${LLVM_MAIN_SRC_DIR}/tools/llvm-exegesis/lib
  )
add_llvm_exegesis_unittest_link_components(
  MC
  MCParser
  Object
  Support
  Symbolize
  PowerPC
  )
add_llvm_exegesis_unittest_sources(
  AnalysisTest.cpp
  SnippetGeneratorTest.cpp
  TargetTest.cpp
  )
add_llvm_exegesis_unittest_link_libraries(
  LLVMExegesisPowerPC)

//===-- PPCAnalysisTest.cpp ---------------------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
#include "Analysis.h"
#include <cassert>
#include <memory>
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/TargetSelect.h"
#include "gmock/gmock.h"
#include "gtest/gtest.h"
namespace llvm{
namespace exegesis {
namespace {
using testing::Pair;
using testing::UnorderedElementsAre;
class PPCAnalysisTest : public ::testing::Test {
protected:
  PPCAnalysisTest() {
    const std::string TT = "powerpc64le-unknown-linux";
    std::string error;
    const Target *const TheTarget = TargetRegistry::lookupTarget(TT, error);
    if (!TheTarget) {
      errs() << error << "\n";
      return;
    }
    STI.reset(TheTarget->createMCSubtargetInfo(TT, "pwr9", ""));
    // Compute the ProxResIdx of ports uses in tests.
    const auto &SM = STI->getSchedModel();
    for (unsigned I = 0, E = SM.getNumProcResourceKinds(); I < E; ++I) {
      const std::string Name = SM.getProcResource(I)->Name;
      if (Name == "ALU") {
        ALUIdx = I;
      } else if (Name == "ALUE") {
        ALUEIdx = I;
      } else if (Name == "ALUO") {
        ALUOIdx = I;
      } else if (Name == "IP_AGEN") {
        IPAGENIdx = I;
      }
    }
    EXPECT_NE(ALUIdx, 0);
    EXPECT_NE(ALUEIdx, 0);
    EXPECT_NE(ALUOIdx, 0);
    EXPECT_NE(IPAGENIdx, 0);
  }
  static void SetUpTestCase() {
    LLVMInitializePowerPCTargetInfo();
    LLVMInitializePowerPCTarget();
    LLVMInitializePowerPCTargetMC();
  }
protected:
  std::unique_ptr<const MCSubtargetInfo> STI;
  uint16_t ALUIdx = 0;
  uint16_t ALUEIdx = 0;
  uint16_t ALUOIdx = 0;
  uint16_t IPAGENIdx = 0;
};
TEST_F(PPCAnalysisTest, ComputeIdealizedProcResPressure_2ALU) {
  const auto Pressure =
      computeIdealizedProcResPressure(STI->getSchedModel(), {{ALUIdx, 2}});
  EXPECT_THAT(Pressure, UnorderedElementsAre(Pair(ALUIdx, 2.0)));
}
TEST_F(PPCAnalysisTest, ComputeIdealizedProcResPressure_1ALUE) {
  const auto Pressure =
      computeIdealizedProcResPressure(STI->getSchedModel(), {{ALUEIdx, 2}});
  EXPECT_THAT(Pressure, UnorderedElementsAre(Pair(ALUEIdx, 2.0)));
}
TEST_F(PPCAnalysisTest, ComputeIdealizedProcResPressure_1ALU1IPAGEN) {
  const auto Pressure =
      computeIdealizedProcResPressure(STI->getSchedModel(), {{ALUIdx, 1}, {IPAGENIdx, 1}});
  EXPECT_THAT(Pressure, UnorderedElementsAre(Pair(ALUIdx, 1.0),Pair(IPAGENIdx, 1)));
}
} // namespace
} // namespace exegesis
} // namespace llvm

//===-- PerfHelperTest.cpp --------------------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
#include "PerfHelper.h"
#include "llvm/Config/config.h"
#include "gmock/gmock.h"
#include "gtest/gtest.h"
namespace llvm {
namespace exegesis {
namespace pfm {
namespace {
using ::testing::IsEmpty;
using ::testing::Not;
TEST(PerfHelperTest, FunctionalTest) {
#ifdef HAVE_LIBPFM
  ASSERT_FALSE(pfmInitialize());
  PerfEvent Event("CYCLES:u");
  ASSERT_TRUE(Event.valid());
  EXPECT_EQ(Event.name(), "CYCLES:u");
  EXPECT_THAT(Event.getPfmEventString(), Not(IsEmpty()));
  Counter Cnt(std::move(Event));
  Cnt.start();
  Cnt.stop();
  Cnt.read();
  pfmTerminate();
#else
  ASSERT_TRUE(pfmInitialize());
#endif
}
} // namespace
} // namespace pfm
} // namespace exegesis
} // namespace llvm

//===-- TestBase.h ----------------------------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
// Test fixture common to all Mips tests.
//===----------------------------------------------------------------------===//
#ifndef LLVM_UNITTESTS_TOOLS_LLVMEXEGESIS_MIPS_TESTBASE_H
#define LLVM_UNITTESTS_TOOLS_LLVMEXEGESIS_MIPS_TESTBASE_H
#include "LlvmState.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/TargetSelect.h"
#include "gmock/gmock.h"
#include "gtest/gtest.h"
namespace llvm {
namespace exegesis {
void InitializeMipsExegesisTarget();
class MipsTestBase : public ::testing::Test {
protected:
  MipsTestBase() : State("mips-unknown-linux", "mips32") {}
  static void SetUpTestCase() {
    LLVMInitializeMipsTargetInfo();
    LLVMInitializeMipsTargetMC();
    LLVMInitializeMipsTarget();
    InitializeMipsExegesisTarget();
  }
  const LLVMState State;
};
} // namespace exegesis
} // namespace llvm
#endif

//===-- TargetTest.cpp ------------------------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
#include "Target.h"
#include <cassert>
#include <memory>
#include "MCTargetDesc/MipsMCTargetDesc.h"
#include "TestBase.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/TargetSelect.h"
#include "gmock/gmock.h"
#include "gtest/gtest.h"
namespace llvm {
namespace exegesis {
namespace {
using testing::AllOf;
using testing::ElementsAre;
using testing::Eq;
using testing::Matcher;
using testing::Property;
Matcher<MCOperand> IsImm(int64_t Value) {
  return AllOf(Property(&MCOperand::isImm, Eq(true)),
               Property(&MCOperand::getImm, Eq(Value)));
}
Matcher<MCOperand> IsReg(unsigned Reg) {
  return AllOf(Property(&MCOperand::isReg, Eq(true)),
               Property(&MCOperand::getReg, Eq(Reg)));
}
Matcher<MCInst> OpcodeIs(unsigned Opcode) {
  return Property(&MCInst::getOpcode, Eq(Opcode));
}
Matcher<MCInst> IsLoadLow16BitImm(unsigned Reg, int64_t Value, bool IsGPR32) {
  const unsigned ZeroReg = IsGPR32 ? Mips::ZERO : Mips::ZERO_64;
  const unsigned ORi = IsGPR32 ? Mips::ORi : Mips::ORi64;
  return AllOf(OpcodeIs(ORi),
               ElementsAre(IsReg(Reg), IsReg(ZeroReg), IsImm(Value)));
}
Matcher<MCInst> IsLoadHigh16BitImm(unsigned Reg, int64_t Value, bool IsGPR32) {
  const unsigned LUi = IsGPR32 ? Mips::LUi : Mips::LUi64;
  return AllOf(OpcodeIs(LUi), ElementsAre(IsReg(Reg), IsImm(Value)));
}
Matcher<MCInst> IsShift(unsigned Reg, uint16_t Amount, bool IsGPR32) {
  const unsigned SLL = IsGPR32 ? Mips::SLL : Mips::SLL64_64;
  return AllOf(OpcodeIs(SLL),
               ElementsAre(IsReg(Reg), IsReg(Reg), IsImm(Amount)));
}
class MipsTargetTest : public MipsTestBase {
protected:
  std::vector<MCInst> setRegTo(unsigned Reg, const APInt &Value) {
    return State.getExegesisTarget().setRegTo(State.getSubtargetInfo(), Reg,
                                              Value);
  }
};
TEST_F(MipsTargetTest, SetGPR32RegTo16BitValue) {
  const uint16_t Value = 0xFFFFU;
  const unsigned Reg = Mips::T0;
  EXPECT_THAT(setRegTo(Reg, APInt(16, Value)),
              ElementsAre(IsLoadLow16BitImm(Reg, Value, true)));
}
TEST_F(MipsTargetTest, SetGPR64RegTo16BitValue) {
  const uint16_t Value = 0xFFFFU;
  const unsigned Reg = Mips::T0_64;
  EXPECT_THAT(setRegTo(Reg, APInt(16, Value)),
              ElementsAre(IsLoadLow16BitImm(Reg, Value, false)));
}
TEST_F(MipsTargetTest, SetGPR32RegTo32BitValue) {
  const uint32_t Value0 = 0xFFFF0000UL;
  const unsigned Reg0 = Mips::T0;
  EXPECT_THAT(setRegTo(Reg0, APInt(32, Value0)),
              ElementsAre(IsLoadHigh16BitImm(Reg0, 0xFFFFU, true)));
  const uint32_t Value1 = 0xFFFFFFFFUL;
  const unsigned Reg1 = Mips::T1;
  EXPECT_THAT(setRegTo(Reg1, APInt(32, Value1)),
              ElementsAre(IsLoadHigh16BitImm(Reg1, 0xFFFFU, true),
                          IsLoadLow16BitImm(Reg1, 0xFFFFU, true)));
}
TEST_F(MipsTargetTest, SetGPR64RegTo32BitValue) {
  const uint32_t Value0 = 0x7FFF0000UL;
  const unsigned Reg0 = Mips::T0_64;
  EXPECT_THAT(setRegTo(Reg0, APInt(32, Value0)),
              ElementsAre(IsLoadHigh16BitImm(Reg0, 0x7FFFU, false)));
  const uint32_t Value1 = 0x7FFFFFFFUL;
  const unsigned Reg1 = Mips::T1_64;
  EXPECT_THAT(setRegTo(Reg1, APInt(32, Value1)),
              ElementsAre(IsLoadHigh16BitImm(Reg1, 0x7FFFU, false),
                          IsLoadLow16BitImm(Reg1, 0xFFFFU, false)));
  const uint32_t Value2 = 0xFFFF0000UL;
  const unsigned Reg2 = Mips::T2_64;
  EXPECT_THAT(setRegTo(Reg2, APInt(32, Value2)),
              ElementsAre(IsLoadLow16BitImm(Reg2, 0xFFFFU, false),
                          IsShift(Reg2, 16, false)));
  const uint32_t Value3 = 0xFFFFFFFFUL;
  const unsigned Reg3 = Mips::T3_64;
  EXPECT_THAT(setRegTo(Reg3, APInt(32, Value3)),
              ElementsAre(IsLoadLow16BitImm(Reg3, 0xFFFFU, false),
                          IsShift(Reg3, 16, false),
                          IsLoadLow16BitImm(Reg3, 0xFFFFU, false)));
}
TEST_F(MipsTargetTest, DefaultPfmCounters) {
  const std::string Expected = "CYCLES";
  EXPECT_EQ(State.getExegesisTarget().getPfmCounters("").CycleCounter,
            Expected);
  EXPECT_EQ(
      State.getExegesisTarget().getPfmCounters("unknown_cpu").CycleCounter,
      Expected);
}
} // namespace
} // namespace exegesis
} // namespace llvm

//===-- SnippetGeneratorTest.cpp --------------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
#include "../Common/AssemblerUtils.h"
#include "LlvmState.h"
#include "MCInstrDescView.h"
#include "MipsInstrInfo.h"
#include "ParallelSnippetGenerator.h"
#include "RegisterAliasing.h"
#include "SerialSnippetGenerator.h"
#include "TestBase.h"
#include <unordered_set>
namespace llvm {
namespace exegesis {
namespace {
using testing::AnyOf;
using testing::ElementsAre;
using testing::HasSubstr;
using testing::SizeIs;
MATCHER(IsInvalid, "") { return !arg.isValid(); }
MATCHER(IsReg, "") { return arg.isReg(); }
template <typename SnippetGeneratorT>
class MipsSnippetGeneratorTest : public MipsTestBase {
protected:
  MipsSnippetGeneratorTest() : Generator(State, SnippetGenerator::Options()) {}
  std::vector<CodeTemplate> checkAndGetCodeTemplates(unsigned Opcode) {
    randomGenerator().seed(0); // Initialize seed.
    const Instruction &Instr = State.getIC().getInstr(Opcode);
    auto CodeTemplateOrError = Generator.generateCodeTemplates(
        &Instr, State.getRATC().emptyRegisters());
    EXPECT_FALSE(CodeTemplateOrError.takeError()); // Valid configuration.
    return std::move(CodeTemplateOrError.get());
  }
  SnippetGeneratorT Generator;
};
using MipsSerialSnippetGeneratorTest = MipsSnippetGeneratorTest<SerialSnippetGenerator>;
using MipsParallelSnippetGeneratorTest =
    MipsSnippetGeneratorTest<ParallelSnippetGenerator>;
TEST_F(MipsSerialSnippetGeneratorTest, ImplicitSelfDependencyThroughExplicitRegs) {
  // - ADD
  // - Op0 Explicit Def RegClass(GPR32)
  // - Op1 Explicit Use RegClass(GPR32)
  // - Op2 Explicit Use RegClass(GPR32)
  // - Var0 [Op0]
  // - Var1 [Op1]
  // - Var2 [Op2]
  // - hasAliasingRegisters
  const unsigned Opcode = Mips::ADD;
  const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
  ASSERT_THAT(CodeTemplates, SizeIs(1));
  const auto &CT = CodeTemplates[0];
  EXPECT_THAT(CT.Execution, ExecutionMode::SERIAL_VIA_EXPLICIT_REGS);
  ASSERT_THAT(CT.Instructions, SizeIs(1));
  const InstructionTemplate &IT = CT.Instructions[0];
  EXPECT_THAT(IT.getOpcode(), Opcode);
  ASSERT_THAT(IT.getVariableValues(), SizeIs(3));
  EXPECT_THAT(IT.getVariableValues(),
              AnyOf(ElementsAre(IsReg(), IsInvalid(), IsReg()),
                    ElementsAre(IsReg(), IsReg(), IsInvalid())))
      << "Op0 is either set to Op1 or to Op2";
}
TEST_F(MipsSerialSnippetGeneratorTest,
       ImplicitSelfDependencyThroughExplicitRegsForbidAll) {
  // - XOR
  // - Op0 Explicit Def RegClass(GPR32)
  // - Op1 Explicit Use RegClass(GPR32)
  // - Op2 Explicit Use RegClass(GPR32)
  // - Var0 [Op0]
  // - Var1 [Op1]
  // - Var2 [Op2]
  // - hasAliasingRegisters
  randomGenerator().seed(0); // Initialize seed.
  const Instruction &Instr = State.getIC().getInstr(Mips::XOR);
  auto AllRegisters = State.getRATC().emptyRegisters();
  AllRegisters.flip();
  auto Error =
      Generator.generateCodeTemplates(&Instr, AllRegisters).takeError();
  EXPECT_TRUE((bool)Error);
  consumeError(std::move(Error));
}
TEST_F(MipsParallelSnippetGeneratorTest, MemoryUse) {
  // LB reads from memory.
  // - LB
  // - Op0 Explicit Def RegClass(GPR32)
  // - Op1 Explicit Use Memory RegClass(MSA128F16)
  // - Op2 Explicit Use Memory
  // - Var0 [Op0]
  // - Var1 [Op1]
  // - Var2 [Op2]
  // - hasMemoryOperands
  const unsigned Opcode = Mips::LB;
  const auto CodeTemplates = checkAndGetCodeTemplates(Opcode);
  ASSERT_THAT(CodeTemplates, SizeIs(1));
  const auto &CT = CodeTemplates[0];
  EXPECT_THAT(CT.Info,
              HasSubstr("instruction is parallel, repeating a random one."));
  EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN);
  ASSERT_THAT(CT.Instructions,
              SizeIs(ParallelSnippetGenerator::kMinNumDifferentAddresses));
  const InstructionTemplate &IT = CT.Instructions[0];
  EXPECT_THAT(IT.getOpcode(), Opcode);
  ASSERT_THAT(IT.getVariableValues(), SizeIs(3));
  EXPECT_EQ(IT.getVariableValues()[0].getReg(), 0u);
  EXPECT_EQ(IT.getVariableValues()[2].getImm(), 0);
}
} // namespace
} // namespace exegesis
} // namespace llvm

//===-- RegisterAliasingTest.cpp --------------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
#include "RegisterAliasing.h"
#include <cassert>
#include <memory>
#include "MipsInstrInfo.h"
#include "TestBase.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/TargetSelect.h"
#include "gmock/gmock.h"
#include "gtest/gtest.h"
namespace llvm {
namespace exegesis {
namespace {
class MipsRegisterAliasingTest : public MipsTestBase {};
TEST_F(MipsRegisterAliasingTest, TrackSimpleRegister) {
  const auto &RegInfo = State.getRegInfo();
  const RegisterAliasingTracker tracker(RegInfo, Mips::T0_64);
  std::set<MCPhysReg> ActualAliasedRegisters;
  for (unsigned I : tracker.aliasedBits().set_bits())
    ActualAliasedRegisters.insert(static_cast<MCPhysReg>(I));
  const std::set<MCPhysReg> ExpectedAliasedRegisters = {Mips::T0, Mips::T0_64};
  ASSERT_THAT(ActualAliasedRegisters, ExpectedAliasedRegisters);
  for (MCPhysReg aliased : ExpectedAliasedRegisters) {
    ASSERT_THAT(tracker.getOrigin(aliased), Mips::T0_64);
  }
}
TEST_F(MipsRegisterAliasingTest, TrackRegisterClass) {
  // The alias bits for
  // GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID
  // are the union of the alias bits for ZERO_64, V0_64, V1_64 and S1_64.
  const auto &RegInfo = State.getRegInfo();
  const BitVector NoReservedReg(RegInfo.getNumRegs());
  const RegisterAliasingTracker RegClassTracker(
      RegInfo, NoReservedReg,
      RegInfo.getRegClass(
          Mips::GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClassID));
  BitVector sum(RegInfo.getNumRegs());
  sum |= RegisterAliasingTracker(RegInfo, Mips::ZERO_64).aliasedBits();
  sum |= RegisterAliasingTracker(RegInfo, Mips::V0_64).aliasedBits();
  sum |= RegisterAliasingTracker(RegInfo, Mips::V1_64).aliasedBits();
  sum |= RegisterAliasingTracker(RegInfo, Mips::S1_64).aliasedBits();
  ASSERT_THAT(RegClassTracker.aliasedBits(), sum);
}
TEST_F(MipsRegisterAliasingTest, TrackRegisterClassCache) {
  // Fetching the same tracker twice yields the same pointers.
  const auto &RegInfo = State.getRegInfo();
  const BitVector NoReservedReg(RegInfo.getNumRegs());
  RegisterAliasingTrackerCache Cache(RegInfo, NoReservedReg);
  ASSERT_THAT(&Cache.getRegister(Mips::T0), &Cache.getRegister(Mips::T0));
  ASSERT_THAT(&Cache.getRegisterClass(Mips::ACC64RegClassID),
              &Cache.getRegisterClass(Mips::ACC64RegClassID));
}
} // namespace
} // namespace exegesis
} // namespace llvm

add_llvm_exegesis_unittest_includes(
  ${LLVM_MAIN_SRC_DIR}/lib/Target/Mips
  ${LLVM_BINARY_DIR}/lib/Target/Mips
  ${LLVM_MAIN_SRC_DIR}/tools/llvm-exegesis/lib
  )
add_llvm_exegesis_unittest_link_components(
  MC
  MCParser
  Object
  Support
  Symbolize
  Mips
  )
add_llvm_exegesis_unittest_sources(
  BenchmarkResultTest.cpp
  RegisterAliasingTest.cpp
  SnippetGeneratorTest.cpp
  TargetTest.cpp
  )
add_llvm_exegesis_unittest_link_libraries(
  LLVMExegesisMips)

//===-- BenchmarkResultTest.cpp ---------------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
#include "BenchmarkResult.h"
#include "MipsInstrInfo.h"
#include "TestBase.h"
#include "llvm/ADT/SmallString.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/Error.h"
#include "llvm/Support/Path.h"
#include "llvm/Support/TargetSelect.h"
#include "llvm/Support/YAMLTraits.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Testing/Support/SupportHelpers.h"
#include "gmock/gmock.h"
#include "gtest/gtest.h"
using ::testing::AllOf;
using ::testing::Eq;
using ::testing::get;
using ::testing::Pointwise;
using ::testing::Property;
using llvm::unittest::TempDir;
namespace llvm {
namespace exegesis {
static std::string Dump(const MCInst &McInst) {
  std::string Buffer;
  raw_string_ostream OS(Buffer);
  McInst.print(OS);
  return Buffer;
}
MATCHER(EqMCInst, "") {
  const std::string Lhs = Dump(get<0>(arg));
  const std::string Rhs = Dump(get<1>(arg));
  if (Lhs != Rhs) {
    *result_listener << Lhs << " <=> " << Rhs;
    return false;
  }
  return true;
}
namespace {
class MipsBenchmarkResultTest : public MipsTestBase {};
TEST_F(MipsBenchmarkResultTest, WriteToAndReadFromDisk) {
  ExitOnError ExitOnErr;
  InstructionBenchmark ToDisk;
  ToDisk.Key.Instructions.push_back(MCInstBuilder(Mips::XOR)
                                        .addReg(Mips::T0)
                                        .addReg(Mips::T1)
                                        .addReg(Mips::T2));
  ToDisk.Key.Config = "config";
  ToDisk.Key.RegisterInitialValues = {
      RegisterValue{Mips::T1, APInt(8, "123", 10)},
      RegisterValue{Mips::T2, APInt(8, "456", 10)}};
  ToDisk.Mode = InstructionBenchmark::Latency;
  ToDisk.CpuName = "cpu_name";
  ToDisk.LLVMTriple = "llvm_triple";
  ToDisk.NumRepetitions = 1;
  ToDisk.Measurements.push_back(BenchmarkMeasure{"a", 1, 1});
  ToDisk.Measurements.push_back(BenchmarkMeasure{"b", 2, 2});
  ToDisk.Error = "error";
  ToDisk.Info = "info";
  TempDir TestDirectory("BenchmarkResultTestDir", /*Unique*/ true);
  SmallString<64> Filename(TestDirectory.path());
  sys::path::append(Filename, "data.yaml");
  errs() << Filename << "-------\n";
  ExitOnErr(ToDisk.writeYaml(State, Filename));
  {
    // One-element version.
    const auto FromDisk =
        ExitOnErr(InstructionBenchmark::readYaml(State, Filename));
    EXPECT_THAT(FromDisk.Key.Instructions,
                Pointwise(EqMCInst(), ToDisk.Key.Instructions));
    EXPECT_EQ(FromDisk.Key.Config, ToDisk.Key.Config);
    EXPECT_EQ(FromDisk.Mode, ToDisk.Mode);
    EXPECT_EQ(FromDisk.CpuName, ToDisk.CpuName);
    EXPECT_EQ(FromDisk.LLVMTriple, ToDisk.LLVMTriple);
    EXPECT_EQ(FromDisk.NumRepetitions, ToDisk.NumRepetitions);
    EXPECT_THAT(FromDisk.Measurements, ToDisk.Measurements);
    EXPECT_THAT(FromDisk.Error, ToDisk.Error);
    EXPECT_EQ(FromDisk.Info, ToDisk.Info);
  }
  {
    // Vector version.
    const auto FromDiskVector =
        ExitOnErr(InstructionBenchmark::readYamls(State, Filename));
    ASSERT_EQ(FromDiskVector.size(), size_t{1});
    const auto FromDisk = FromDiskVector[0];
    EXPECT_THAT(FromDisk.Key.Instructions,
                Pointwise(EqMCInst(), ToDisk.Key.Instructions));
    EXPECT_EQ(FromDisk.Key.Config, ToDisk.Key.Config);
    EXPECT_EQ(FromDisk.Mode, ToDisk.Mode);
    EXPECT_EQ(FromDisk.CpuName, ToDisk.CpuName);
    EXPECT_EQ(FromDisk.LLVMTriple, ToDisk.LLVMTriple);
    EXPECT_EQ(FromDisk.NumRepetitions, ToDisk.NumRepetitions);
    EXPECT_THAT(FromDisk.Measurements, ToDisk.Measurements);
    EXPECT_THAT(FromDisk.Error, ToDisk.Error);
    EXPECT_EQ(FromDisk.Info, ToDisk.Info);
  }
}
TEST_F(MipsBenchmarkResultTest, PerInstructionStats) {
  PerInstructionStats Stats;
  Stats.push(BenchmarkMeasure{"a", 0.5, 0.0});
  Stats.push(BenchmarkMeasure{"a", 1.5, 0.0});
  Stats.push(BenchmarkMeasure{"a", -1.0, 0.0});
  Stats.push(BenchmarkMeasure{"a", 0.0, 0.0});
  EXPECT_EQ(Stats.min(), -1.0);
  EXPECT_EQ(Stats.max(), 1.5);
  EXPECT_EQ(Stats.avg(), 0.25); // (0.5+1.5-1.0+0.0) / 4
}
} // namespace
} // namespace exegesis
} // namespace llvm

//===-- AssemblerUtils.h ----------------------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_UNITTESTS_TOOLS_LLVMEXEGESIS_ASSEMBLERUTILS_H
#define LLVM_UNITTESTS_TOOLS_LLVMEXEGESIS_ASSEMBLERUTILS_H
#include "Assembler.h"
#include "BenchmarkRunner.h"
#include "Target.h"
#include "llvm/ADT/ArrayRef.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/TargetInstrInfo.h"
#include "llvm/CodeGen/TargetSubtargetInfo.h"
#include "llvm/MC/MCInstBuilder.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/Host.h"
#include "llvm/Support/TargetSelect.h"
#include "gmock/gmock.h"
#include "gtest/gtest.h"
namespace llvm {
namespace exegesis {
class MachineFunctionGeneratorBaseTest : public ::testing::Test {
protected:
  MachineFunctionGeneratorBaseTest(const std::string &TT,
                                   const std::string &CpuName)
      : TT(TT), CpuName(CpuName),
        CanExecute(Triple(TT).getArch() ==
                   Triple(sys::getProcessTriple()).getArch()),
        ET(ExegesisTarget::lookup(Triple(TT))) {
    assert(ET);
    if (!CanExecute) {
      outs() << "Skipping execution, host:" << sys::getProcessTriple()
             << ", target:" << TT << "\n";
    }
  }
  template <class... Bs>
  inline void Check(ArrayRef<RegisterValue> RegisterInitialValues, MCInst Inst,
                    Bs... Bytes) {
    ExecutableFunction Function =
        (Inst.getOpcode() == 0)
            ? assembleToFunction(RegisterInitialValues, [](FunctionFiller &) {})
            : assembleToFunction(RegisterInitialValues,
                                 [Inst](FunctionFiller &Filler) {
                                   Filler.getEntry().addInstruction(Inst);
                                 });
    ASSERT_THAT(Function.getFunctionBytes().str(),
                testing::ElementsAre(Bytes...));
    if (CanExecute) {
      BenchmarkRunner::ScratchSpace Scratch;
      Function(Scratch.ptr());
    }
  }
private:
  std::unique_ptr<LLVMTargetMachine> createTargetMachine() {
    std::string Error;
    const Target *TheTarget = TargetRegistry::lookupTarget(TT, Error);
    EXPECT_TRUE(TheTarget) << Error << " " << TT;
    const TargetOptions Options;
    TargetMachine *TM = TheTarget->createTargetMachine(TT, CpuName, "", Options,
                                                       Reloc::Model::Static);
    EXPECT_TRUE(TM) << TT << " " << CpuName;
    return std::unique_ptr<LLVMTargetMachine>(
        static_cast<LLVMTargetMachine *>(TM));
  }
  ExecutableFunction
  assembleToFunction(ArrayRef<RegisterValue> RegisterInitialValues,
                     FillFunction Fill) {
    SmallString<256> Buffer;
    raw_svector_ostream AsmStream(Buffer);
    EXPECT_FALSE(assembleToStream(*ET, createTargetMachine(), /*LiveIns=*/{},
                                  RegisterInitialValues, Fill, AsmStream));
    return ExecutableFunction(createTargetMachine(),
                              getObjectFromBuffer(AsmStream.str()));
  }
  const std::string TT;
  const std::string CpuName;
  const bool CanExecute;
  const ExegesisTarget *const ET;
};
} // namespace exegesis
} // namespace llvm
#endif

//===-- ClusteringTest.cpp --------------------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
#include "Clustering.h"
#include "BenchmarkResult.h"
#include "llvm/Support/Error.h"
#include "llvm/Support/raw_ostream.h"
#include "gmock/gmock.h"
#include "gtest/gtest.h"
namespace llvm {
namespace exegesis {
namespace {
using testing::Field;
using testing::UnorderedElementsAre;
using testing::UnorderedElementsAreArray;
static const auto HasPoints = [](const std::vector<int> &Indices) {
  return Field(&InstructionBenchmarkClustering::Cluster::PointIndices,
                 UnorderedElementsAreArray(Indices));
};
TEST(ClusteringTest, Clusters3D) {
  std::vector<InstructionBenchmark> Points(6);
  // Cluster around (x=0, y=1, z=2): points {0, 3}.
  Points[0].Measurements = {
      {"x", 0.01, 0.0}, {"y", 1.02, 0.0}, {"z", 1.98, 0.0}};
  Points[3].Measurements = {
      {"x", -0.01, 0.0}, {"y", 1.02, 0.0}, {"z", 1.98, 0.0}};
  // Cluster around (x=1, y=1, z=2): points {1, 4}.
  Points[1].Measurements = {
      {"x", 1.01, 0.0}, {"y", 1.02, 0.0}, {"z", 1.98, 0.0}};
  Points[4].Measurements = {
      {"x", 0.99, 0.0}, {"y", 1.02, 0.0}, {"z", 1.98, 0.0}};
  // Cluster around (x=0, y=0, z=0): points {5}, marked as noise.
  Points[5].Measurements = {
      {"x", 0.0, 0.0}, {"y", 0.01, 0.0}, {"z", -0.02, 0.0}};
  // Error cluster: points {2}
  Points[2].Error = "oops";
  auto Clustering = InstructionBenchmarkClustering::create(
      Points, InstructionBenchmarkClustering::ModeE::Dbscan, 2, 0.25);
  ASSERT_TRUE((bool)Clustering);
  EXPECT_THAT(Clustering.get().getValidClusters(),
              UnorderedElementsAre(HasPoints({0, 3}), HasPoints({1, 4})));
  EXPECT_THAT(Clustering.get().getCluster(
                  InstructionBenchmarkClustering::ClusterId::noise()),
              HasPoints({5}));
  EXPECT_THAT(Clustering.get().getCluster(
                  InstructionBenchmarkClustering::ClusterId::error()),
              HasPoints({2}));
  EXPECT_EQ(Clustering.get().getClusterIdForPoint(2),
            InstructionBenchmarkClustering::ClusterId::error());
  EXPECT_EQ(Clustering.get().getClusterIdForPoint(5),
            InstructionBenchmarkClustering::ClusterId::noise());
  EXPECT_EQ(Clustering.get().getClusterIdForPoint(0),
            Clustering.get().getClusterIdForPoint(3));
  EXPECT_EQ(Clustering.get().getClusterIdForPoint(1),
            Clustering.get().getClusterIdForPoint(4));
}
TEST(ClusteringTest, Clusters3D_InvalidSize) {
  std::vector<InstructionBenchmark> Points(6);
  Points[0].Measurements = {
      {"x", 0.01, 0.0}, {"y", 1.02, 0.0}, {"z", 1.98, 0.0}};
  Points[1].Measurements = {{"y", 1.02, 0.0}, {"z", 1.98, 0.0}};
  auto Error =
      InstructionBenchmarkClustering::create(
          Points, InstructionBenchmarkClustering::ModeE::Dbscan, 2, 0.25)
          .takeError();
  ASSERT_TRUE((bool)Error);
  consumeError(std::move(Error));
}
TEST(ClusteringTest, Clusters3D_InvalidOrder) {
  std::vector<InstructionBenchmark> Points(6);
  Points[0].Measurements = {{"x", 0.01, 0.0}, {"y", 1.02, 0.0}};
  Points[1].Measurements = {{"y", 1.02, 0.0}, {"x", 1.98, 0.0}};
  auto Error =
      InstructionBenchmarkClustering::create(
          Points, InstructionBenchmarkClustering::ModeE::Dbscan, 2, 0.25)
          .takeError();
  ASSERT_TRUE((bool)Error);
  consumeError(std::move(Error));
}
TEST(ClusteringTest, Ordering) {
  ASSERT_LT(InstructionBenchmarkClustering::ClusterId::makeValid(1),
            InstructionBenchmarkClustering::ClusterId::makeValid(2));
  ASSERT_LT(InstructionBenchmarkClustering::ClusterId::makeValid(2),
            InstructionBenchmarkClustering::ClusterId::noise());
  ASSERT_LT(InstructionBenchmarkClustering::ClusterId::makeValid(2),
            InstructionBenchmarkClustering::ClusterId::error());
  ASSERT_LT(InstructionBenchmarkClustering::ClusterId::noise(),
            InstructionBenchmarkClustering::ClusterId::error());
}
TEST(ClusteringTest, Ordering1) {
  std::vector<InstructionBenchmark> Points(3);
  Points[0].Measurements = {
      {"x", 0.0, 0.0}};
  Points[1].Measurements = {
      {"x", 1.0, 0.0}};
  Points[2].Measurements = {
      {"x", 2.0, 0.0}};
  auto Clustering = InstructionBenchmarkClustering::create(
      Points, InstructionBenchmarkClustering::ModeE::Dbscan, 2, 1.1);
  ASSERT_TRUE((bool)Clustering);
  EXPECT_THAT(Clustering.get().getValidClusters(),
              UnorderedElementsAre(HasPoints({0, 1, 2})));
}
TEST(ClusteringTest, Ordering2) {
  std::vector<InstructionBenchmark> Points(3);
  Points[0].Measurements = {
      {"x", 0.0, 0.0}};
  Points[1].Measurements = {
      {"x", 2.0, 0.0}};
  Points[2].Measurements = {
      {"x", 1.0, 0.0}};
  auto Clustering = InstructionBenchmarkClustering::create(
      Points, InstructionBenchmarkClustering::ModeE::Dbscan, 2, 1.1);
  ASSERT_TRUE((bool)Clustering);
  EXPECT_THAT(Clustering.get().getValidClusters(),
              UnorderedElementsAre(HasPoints({0, 1, 2})));
}
} // namespace
} // namespace exegesis
} // namespace llvm

set(exegesis_includes
  ${LLVM_MAIN_SRC_DIR}/tools/llvm-exegesis/lib
  )
set(LLVM_LINK_COMPONENTS
  MC
  MCParser
  Object
  Support
  Symbolize
  )
set(exegesis_sources
  BenchmarkRunnerTest.cpp
  ClusteringTest.cpp
  PerfHelperTest.cpp
  RegisterValueTest.cpp
  )
set(exegesis_link_libraries LLVMExegesis)
function(add_llvm_exegesis_unittest_includes)
  set(exegesis_includes ${exegesis_includes} ${ARGV} PARENT_SCOPE)
endfunction()
function(add_llvm_exegesis_unittest_sources)
  set(sources ${ARGV})
  list(TRANSFORM sources PREPEND "${CMAKE_CURRENT_LIST_DIR}/")
  set(exegesis_sources ${exegesis_sources} ${sources} PARENT_SCOPE)
endfunction()
function(add_llvm_exegesis_unittest_link_components comps)
  set(LLVM_LINK_COMPONENTS ${LLVM_LINK_COMPONENTS} ${ARGV} PARENT_SCOPE)
endfunction()
function(add_llvm_exegesis_unittest_link_libraries libs)
  set(exegesis_link_libraries ${exegesis_link_libraries} ${ARGV} PARENT_SCOPE)
endfunction()
if(LLVM_TARGETS_TO_BUILD MATCHES "X86")
  include(X86/CMakeLists.txt)
endif()
if(LLVM_TARGETS_TO_BUILD MATCHES "ARM")
  include(ARM/CMakeLists.txt)
endif()
if(LLVM_TARGETS_TO_BUILD MATCHES "AArch64")
  include(AArch64/CMakeLists.txt)
endif()
if(LLVM_TARGETS_TO_BUILD MATCHES "PowerPC")
  include(PowerPC/CMakeLists.txt)
endif()
if(LLVM_TARGETS_TO_BUILD MATCHES "Mips")
  include(Mips/CMakeLists.txt)
endif()
include_directories(${exegesis_includes})
list(REMOVE_DUPLICATES LLVM_LINK_COMPONENTS)
add_llvm_target_unittest(LLVMExegesisTests
  ${exegesis_sources}
  )
target_link_libraries(LLVMExegesisTests PRIVATE ${exegesis_link_libraries})
set_property(TARGET LLVMExegesisTests PROPERTY FOLDER "Tests/UnitTests/ToolTests")

//===-- BenchmarkRunnerTest.cpp ---------------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
#include "BenchmarkRunner.h"
#include "gmock/gmock.h"
#include "gtest/gtest.h"
namespace llvm {
namespace exegesis {
namespace {
TEST(ScratchSpaceTest, Works) {
  BenchmarkRunner::ScratchSpace Space;
  EXPECT_EQ(reinterpret_cast<intptr_t>(Space.ptr()) %
                BenchmarkRunner::ScratchSpace::kAlignment,
            0u);
  Space.ptr()[0] = 42;
  Space.ptr()[BenchmarkRunner::ScratchSpace::kSize - 1] = 43;
  Space.clear();
  EXPECT_EQ(Space.ptr()[0], 0);
  EXPECT_EQ(Space.ptr()[BenchmarkRunner::ScratchSpace::kSize - 1], 0);
}
} // namespace
} // namespace exegesis
} // namespace llvm

add_llvm_exegesis_unittest_includes(
  ${LLVM_MAIN_SRC_DIR}/lib/Target/ARM
  ${LLVM_BINARY_DIR}/lib/Target/ARM
  ${LLVM_MAIN_SRC_DIR}/tools/llvm-exegesis/lib
  )
add_llvm_exegesis_unittest_link_components(
  Core
  MC
  MCParser
  Object
  Support
  Symbolize
  ARM
  )
add_llvm_exegesis_unittest_sources(
  AssemblerTest.cpp
  )

//===-- AssemblerTest.cpp ---------------------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
#include "../Common/AssemblerUtils.h"
#include "ARMInstrInfo.h"
namespace llvm {
namespace exegesis {
namespace {
class ARMMachineFunctionGeneratorTest
    : public MachineFunctionGeneratorBaseTest {
protected:
  ARMMachineFunctionGeneratorTest()
      : MachineFunctionGeneratorBaseTest("armv7-none-linux-gnueabi", "") {}
  static void SetUpTestCase() {
    LLVMInitializeARMTargetInfo();
    LLVMInitializeARMTargetMC();
    LLVMInitializeARMTarget();
    LLVMInitializeARMAsmPrinter();
  }
};
TEST_F(ARMMachineFunctionGeneratorTest, DISABLED_JitFunction) {
  Check({}, MCInst(), 0x1e, 0xff, 0x2f, 0xe1);
}
TEST_F(ARMMachineFunctionGeneratorTest, DISABLED_JitFunctionADDrr) {
  Check({{ARM::R0, APInt()}},
        MCInstBuilder(ARM::ADDrr)
            .addReg(ARM::R0)
            .addReg(ARM::R0)
            .addReg(ARM::R0)
            .addImm(ARMCC::AL)
            .addReg(0)
            .addReg(0),
        0x00, 0x00, 0x80, 0xe0, 0x1e, 0xff, 0x2f, 0xe1);
}
} // namespace
} // namespace exegesis
} // namespace llvm

//===-- TargetTest.cpp ------------------------------------------*- C++ -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
#include "Target.h"
#include <cassert>
#include <memory>
#include "MCTargetDesc/AArch64MCTargetDesc.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Support/TargetSelect.h"
#include "gmock/gmock.h"
#include "gtest/gtest.h"
namespace llvm {
namespace exegesis {
void InitializeAArch64ExegesisTarget();
namespace {
using testing::Gt;
using testing::IsEmpty;
using testing::Not;
using testing::NotNull;
constexpr const char kTriple[] = "aarch64-unknown-linux";
class AArch64TargetTest : public ::testing::Test {
protected:
  AArch64TargetTest()
      : ExegesisTarget_(ExegesisTarget::lookup(Triple(kTriple))) {
    EXPECT_THAT(ExegesisTarget_, NotNull());
    std::string error;
    Target_ = TargetRegistry::lookupTarget(kTriple, error);
    EXPECT_THAT(Target_, NotNull());
    STI_.reset(
        Target_->createMCSubtargetInfo(kTriple, "generic", /*no features*/ ""));
  }
  static void SetUpTestCase() {
    LLVMInitializeAArch64TargetInfo();
    LLVMInitializeAArch64Target();
    LLVMInitializeAArch64TargetMC();
    InitializeAArch64ExegesisTarget();
  }
  std::vector<MCInst> setRegTo(unsigned Reg, const APInt &Value) {
    return ExegesisTarget_->setRegTo(*STI_, Reg, Value);
  }
  const Target *Target_;
  const ExegesisTarget *const ExegesisTarget_;
  std::unique_ptr<MCSubtargetInfo> STI_;
};
TEST_F(AArch64TargetTest, SetRegToConstant) {
  // The AArch64 target currently doesn't know how to set register values.
  const auto Insts = setRegTo(AArch64::X0, APInt());
  EXPECT_THAT(Insts, Not(IsEmpty()));
}
TEST_F(AArch64TargetTest, DefaultPfmCounters) {
  const std::string Expected = "CPU_CYCLES";
  EXPECT_EQ(ExegesisTarget_->getPfmCounters("").CycleCounter, Expected);
  EXPECT_EQ(ExegesisTarget_->getPfmCounters("unknown_cpu").CycleCounter,
            Expected);
}
} // namespace
} // namespace exegesis
} // namespace llvm

add_llvm_exegesis_unittest_includes(
  ${LLVM_MAIN_SRC_DIR}/lib/Target/AArch64
  ${LLVM_BINARY_DIR}/lib/Target/AArch64
  ${LLVM_MAIN_SRC_DIR}/tools/llvm-exegesis/lib
  )
add_llvm_exegesis_unittest_link_components(
  MC
  MCParser
  Object
  Support
  Symbolize
  AArch64
  )
add_llvm_exegesis_unittest_sources(
  TargetTest.cpp
  )
add_llvm_exegesis_unittest_link_libraries(
  LLVMExegesisAArch64)

//===- llvm/unittests/llvm-cfi-verify/GraphBuilder.cpp --------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
#include "../tools/llvm-cfi-verify/lib/GraphBuilder.h"
#include "../tools/llvm-cfi-verify/lib/FileAnalysis.h"
#include "gmock/gmock.h"
#include "gtest/gtest.h"
#include "llvm/BinaryFormat/ELF.h"
#include "llvm/DebugInfo/Symbolize/SymbolizableModule.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCDisassembler/MCDisassembler.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstPrinter.h"
#include "llvm/MC/MCInstrAnalysis.h"
#include "llvm/MC/MCInstrDesc.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCObjectFileInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/TargetRegistry.h"
#include "llvm/Object/Binary.h"
#include "llvm/Object/COFF.h"
#include "llvm/Object/ELFObjectFile.h"
#include "llvm/Object/ObjectFile.h"
#include "llvm/Support/Casting.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Error.h"
#include "llvm/Support/MemoryBuffer.h"
#include "llvm/Support/TargetSelect.h"
#include "llvm/Support/raw_ostream.h"
#include <cstdlib>
#include <sstream>
using Instr = ::llvm::cfi_verify::FileAnalysis::Instr;
using ::testing::AllOf;
using ::testing::Each;
using ::testing::ElementsAre;
using ::testing::Eq;
using ::testing::Field;
using ::testing::IsEmpty;
using ::testing::Matches;
using ::testing::Pair;
using ::testing::PrintToString;
using ::testing::Property;
using ::testing::SizeIs;
using ::testing::UnorderedElementsAre;
using ::testing::Value;
namespace llvm {
namespace cfi_verify {
// Printing helpers for gtest.
std::string HexStringifyContainer(const std::vector<uint64_t> &C) {
  std::stringstream Stream;
  if (C.empty()) {
    return "{ }";
  }
  Stream << "{ ";
  const auto &LastElemIt = std::end(C) - 1;
  for (auto It = std::begin(C); It != LastElemIt; ++It) {
    Stream << "0x" << std::hex << *It << ", ";
  }
  Stream << "0x" << std::hex << *LastElemIt << " }";
  return Stream.str();
}
void PrintTo(const ConditionalBranchNode &BranchNode, ::std::ostream *os) {
  *os << "ConditionalBranchNode<Address: 0x" << std::hex << BranchNode.Address
      << ", Target: 0x" << BranchNode.Target << ", Fallthrough: 0x"
      << BranchNode.Fallthrough
      << ", CFIProtection: " << BranchNode.CFIProtection << ">";
}
void PrintTo(const GraphResult &Result, ::std::ostream *os) {
  *os << "Result BaseAddress: 0x" << std::hex << Result.BaseAddress << "\n";
  if (Result.ConditionalBranchNodes.empty())
    *os << "  (No conditional branch nodes)\n";
  for (const auto &Node : Result.ConditionalBranchNodes) {
    *os << "  ";
    PrintTo(Node, os);
    *os << "\n    Fallthrough Path: " << std::hex
        << HexStringifyContainer(Result.flattenAddress(Node.Fallthrough))
        << "\n";
    *os << "    Target Path: " << std::hex
        << HexStringifyContainer(Result.flattenAddress(Node.Target)) << "\n";
  }
  if (Result.OrphanedNodes.empty())
    *os << "  (No orphaned nodes)";
  for (const auto &Orphan : Result.OrphanedNodes) {
    *os << "  Orphan (0x" << std::hex << Orphan
        << ") Path: " << HexStringifyContainer(Result.flattenAddress(Orphan))
        << "\n";
  }
}
namespace {
class ELFx86TestFileAnalysis : public FileAnalysis {
public:
  ELFx86TestFileAnalysis()
      : FileAnalysis(Triple("x86_64--"), SubtargetFeatures()) {}
  // Expose this method publicly for testing.
  void parseSectionContents(ArrayRef<uint8_t> SectionBytes,
                            object::SectionedAddress Address) {
    FileAnalysis::parseSectionContents(SectionBytes, Address);
  }
  Error initialiseDisassemblyMembers() {
    return FileAnalysis::initialiseDisassemblyMembers();
  }
};
class BasicGraphBuilderTest : public ::testing::Test {
protected:
  void SetUp() override {
    IgnoreDWARFFlag = true;
    SuccessfullyInitialised = true;
    if (auto Err = Analysis.initialiseDisassemblyMembers()) {
      handleAllErrors(std::move(Err), [&](const UnsupportedDisassembly &E) {
        SuccessfullyInitialised = false;
        outs()
            << "Note: CFIVerifyTests are disabled due to lack of x86 support "
               "on this build.\n";
      });
    }
  }
  bool SuccessfullyInitialised;
  ELFx86TestFileAnalysis Analysis;
};
MATCHER_P2(HasPath, Result, Matcher, "has path " + PrintToString(Matcher)) {
  const auto &Path = Result.flattenAddress(arg);
  *result_listener << "the path is " << PrintToString(Path);
  return Matches(Matcher)(Path);
}
TEST_F(BasicGraphBuilderTest, BuildFlowGraphTestSinglePathFallthroughUd2) {
  if (!SuccessfullyInitialised)
    return;
  Analysis.parseSectionContents(
      {
          0x75, 0x02, // 0: jne 4 [+2]
          0x0f, 0x0b, // 2: ud2
          0xff, 0x10, // 4: callq *(%rax)
      },
      {0xDEADBEEF, 0x0});
  const auto Result =
      GraphBuilder::buildFlowGraph(Analysis, {0xDEADBEEF + 4, 0x0});
  EXPECT_THAT(Result.OrphanedNodes, IsEmpty());
  EXPECT_THAT(Result.ConditionalBranchNodes, SizeIs(1));
  EXPECT_THAT(Result.ConditionalBranchNodes,
              Each(Field(&ConditionalBranchNode::CFIProtection, Eq(true))));
  EXPECT_THAT(
      Result.ConditionalBranchNodes,
      Contains(AllOf(Field(&ConditionalBranchNode::Address, Eq(0xDEADBEEF)),
                     Field(&ConditionalBranchNode::Target,
                           HasPath(Result, ElementsAre(0xDEADBEEF + 4))),
                     Field(&ConditionalBranchNode::Fallthrough,
                           HasPath(Result, ElementsAre(0xDEADBEEF + 2))))))
      << PrintToString(Result);
}
TEST_F(BasicGraphBuilderTest, BuildFlowGraphTestSinglePathJumpUd2) {
  if (!SuccessfullyInitialised)
    return;
  Analysis.parseSectionContents(
      {
          0x75, 0x02, // 0: jne 4 [+2]
          0xff, 0x10, // 2: callq *(%rax)
          0x0f, 0x0b, // 4: ud2
      },
      {0xDEADBEEF, 0x0});
  const auto Result =
      GraphBuilder::buildFlowGraph(Analysis, {0xDEADBEEF + 2, 0x0});
  EXPECT_THAT(Result.OrphanedNodes, IsEmpty());
  EXPECT_THAT(Result.ConditionalBranchNodes, SizeIs(1));
  EXPECT_THAT(Result.ConditionalBranchNodes,
              Each(Field(&ConditionalBranchNode::CFIProtection, Eq(true))));
  EXPECT_THAT(
      Result.ConditionalBranchNodes,
      Contains(AllOf(Field(&ConditionalBranchNode::Address, Eq(0xDEADBEEF)),
                     Field(&ConditionalBranchNode::Target,
                           HasPath(Result, ElementsAre(0xDEADBEEF + 4))),
                     Field(&ConditionalBranchNode::Fallthrough,
                           HasPath(Result, ElementsAre(0xDEADBEEF + 2))))))
      << PrintToString(Result);
}
TEST_F(BasicGraphBuilderTest, BuildFlowGraphTestDualPathDualUd2) {
  if (!SuccessfullyInitialised)
    return;
  Analysis.parseSectionContents(
      {
          0x75, 0x03, // 0: jne 5 [+3]
          0x90,       // 2: nop
          0xff, 0x10, // 3: callq *(%rax)
          0x0f, 0x0b, // 5: ud2
          0x75, 0xf9, // 7: jne 2 [-7]
          0x0f, 0x0b, // 9: ud2
      },
      {0xDEADBEEF, 0x0});
  const auto Result =
      GraphBuilder::buildFlowGraph(Analysis, {0xDEADBEEF + 3, 0x0});
  EXPECT_THAT(Result.OrphanedNodes, IsEmpty());
  EXPECT_THAT(Result.ConditionalBranchNodes, SizeIs(2));
  EXPECT_THAT(Result.ConditionalBranchNodes,
              Each(Field(&ConditionalBranchNode::CFIProtection, Eq(true))));
  EXPECT_THAT(
      Result.ConditionalBranchNodes,
      Contains(AllOf(
          Field(&ConditionalBranchNode::Address, Eq(0xDEADBEEF)),
          Field(&ConditionalBranchNode::Fallthrough,
                HasPath(Result, ElementsAre(0xDEADBEEF + 2, 0xDEADBEEF + 3))),
          Field(&ConditionalBranchNode::Target,
                HasPath(Result, ElementsAre(0xDEADBEEF + 5))))))
      << PrintToString(Result);
  EXPECT_THAT(
      Result.ConditionalBranchNodes,
      Contains(AllOf(
          Field(&ConditionalBranchNode::Address, Eq(0xDEADBEEF + 7)),
          Field(&ConditionalBranchNode::Fallthrough,
                HasPath(Result, ElementsAre(0xDEADBEEF + 9))),
          Field(&ConditionalBranchNode::Target,
                HasPath(Result, ElementsAre(0xDEADBEEF + 2, 0xDEADBEEF + 3))))))
      << PrintToString(Result);
}
TEST_F(BasicGraphBuilderTest, BuildFlowGraphTestDualPathSingleUd2) {
  if (!SuccessfullyInitialised)
    return;
  Analysis.parseSectionContents(
      {
          0x75, 0x05, // 0: jne 7 [+5]
          0x90,       // 2: nop
          0xff, 0x10, // 3: callq *(%rax)
          0x75, 0xfb, // 5: jne 2 [-5]
          0x0f, 0x0b, // 7: ud2
      },
      {0xDEADBEEF, 0x0});
  GraphResult Result =
      GraphBuilder::buildFlowGraph(Analysis, {0xDEADBEEF + 3, 0x0});
  EXPECT_THAT(Result.OrphanedNodes, IsEmpty());
  EXPECT_THAT(Result.ConditionalBranchNodes, SizeIs(2));
  EXPECT_THAT(Result.ConditionalBranchNodes,
              Each(Field(&ConditionalBranchNode::CFIProtection, Eq(true))));
  EXPECT_THAT(
      Result.ConditionalBranchNodes,
      Contains(AllOf(
          Field(&ConditionalBranchNode::Address, Eq(0xDEADBEEF)),
          Field(&ConditionalBranchNode::Fallthrough,
                HasPath(Result, ElementsAre(0xDEADBEEF + 2, 0xDEADBEEF + 3))),
          Field(&ConditionalBranchNode::Target,
                HasPath(Result, ElementsAre(0xDEADBEEF + 7))))))
      << PrintToString(Result);
  EXPECT_THAT(
      Result.ConditionalBranchNodes,
      Contains(AllOf(
          Field(&ConditionalBranchNode::Address, Eq(0xDEADBEEF + 5)),
          Field(&ConditionalBranchNode::Fallthrough,
                HasPath(Result, ElementsAre(0xDEADBEEF + 7))),
          Field(&ConditionalBranchNode::Target,
                HasPath(Result, ElementsAre(0xDEADBEEF + 2, 0xDEADBEEF + 3))))))
      << PrintToString(Result);
}
TEST_F(BasicGraphBuilderTest, BuildFlowGraphFailures) {
  if (!SuccessfullyInitialised)
    return;
  Analysis.parseSectionContents(
      {
          0x90,       // 0: nop
          0x75, 0xfe, // 1: jne 1 [-2]
      },
      {0xDEADBEEF, 0x0});
  GraphResult Result =
      GraphBuilder::buildFlowGraph(Analysis, {0xDEADBEEF, 0x0});
  EXPECT_THAT(Result.OrphanedNodes, IsEmpty());
  EXPECT_THAT(Result.ConditionalBranchNodes, IsEmpty());
  Result = GraphBuilder::buildFlowGraph(Analysis, {0xDEADBEEF + 1, 0x0});
  EXPECT_THAT(Result.OrphanedNodes, IsEmpty());
  EXPECT_THAT(Result.ConditionalBranchNodes, IsEmpty());
  Result = GraphBuilder::buildFlowGraph(Analysis, {0xDEADC0DE, 0x0});
  EXPECT_THAT(Result.OrphanedNodes, IsEmpty());
  EXPECT_THAT(Result.ConditionalBranchNodes, IsEmpty());
}
TEST_F(BasicGraphBuilderTest, BuildFlowGraphNoXrefs) {
  if (!SuccessfullyInitialised)
    return;
  Analysis.parseSectionContents(
      {
          0xeb, 0xfe, // 0: jmp 0 [-2]
          0xff, 0x10, // 2: callq *(%rax)
      },
      {0xDEADBEEF, 0x0});
  GraphResult Result =
      GraphBuilder::buildFlowGraph(Analysis, {0xDEADBEEF + 2, 0x0});
  EXPECT_THAT(Result.ConditionalBranchNodes, IsEmpty());
  EXPECT_THAT(Result.OrphanedNodes, ElementsAre(0xDEADBEEF + 2));
  EXPECT_THAT(Result.IntermediateNodes, IsEmpty());
}
TEST_F(BasicGraphBuilderTest, BuildFlowGraphConditionalInfiniteLoop) {
  if (!SuccessfullyInitialised)
    return;
  Analysis.parseSectionContents(
      {
          0x75, 0xfe, // 0: jne 0 [-2]
          0xff, 0x10, // 2: callq *(%rax)
      },
      {0xDEADBEEF, 0x0});
  GraphResult Result =
      GraphBuilder::buildFlowGraph(Analysis, {0xDEADBEEF + 2, 0x0});
  EXPECT_THAT(Result.OrphanedNodes, IsEmpty());
  EXPECT_THAT(Result.ConditionalBranchNodes, SizeIs(1));
  EXPECT_THAT(
      Result.ConditionalBranchNodes,
      Each(AllOf(Field(&ConditionalBranchNode::CFIProtection, Eq(false)),
                 Field(&ConditionalBranchNode::Target,
                       HasPath(Result, ElementsAre(0xDEADBEEF))),
                 Field(&ConditionalBranchNode::Fallthrough,
                       HasPath(Result, ElementsAre(0xDEADBEEF + 2))))))
      << PrintToString(Result);
}
TEST_F(BasicGraphBuilderTest, BuildFlowGraphUnconditionalInfiniteLoop) {
  if (!SuccessfullyInitialised)
    return;
  Analysis.parseSectionContents(
      {
          0x75, 0x02, // 0: jne 4 [+2]
          0xeb, 0xfc, // 2: jmp 0 [-4]
          0xff, 0x10, // 4: callq *(%rax)
      },
      {0xDEADBEEF, 0x0});
  GraphResult Result =
      GraphBuilder::buildFlowGraph(Analysis, {0xDEADBEEF + 4, 0x0});
  EXPECT_THAT(Result.OrphanedNodes, IsEmpty());
  EXPECT_THAT(Result.ConditionalBranchNodes, SizeIs(1));
  EXPECT_THAT(
      Result.ConditionalBranchNodes,
      Contains(
          AllOf(Field(&ConditionalBranchNode::Address, Eq(0xDEADBEEF)),
                Field(&ConditionalBranchNode::Fallthrough,
                      HasPath(Result, ElementsAre(0xDEADBEEF + 2, 0xDEADBEEF))),
                Field(&ConditionalBranchNode::Target,
                      HasPath(Result, ElementsAre(0xDEADBEEF + 4))))))
      << PrintToString(Result);
}
TEST_F(BasicGraphBuilderTest, BuildFlowGraphNoFlowsToIndirection) {
  if (!SuccessfullyInitialised)
    return;
  Analysis.parseSectionContents(
      {
          0x75, 0x00, // 0: jne 2 [+0]
          0xeb, 0xfc, // 2: jmp 0 [-4]
          0xff, 0x10, // 4: callq *(%rax)
      },
      {0xDEADBEEF, 0x0});
  GraphResult Result =
      GraphBuilder::buildFlowGraph(Analysis, {0xDEADBEEF + 4, 0x0});
  EXPECT_THAT(Result.OrphanedNodes, ElementsAre(0xDEADBEEF + 4));
  EXPECT_THAT(Result.ConditionalBranchNodes, IsEmpty());
}
TEST_F(BasicGraphBuilderTest, BuildFlowGraphLengthExceededUpwards) {
  if (!SuccessfullyInitialised)
    return;
  Analysis.parseSectionContents(
      {
          0x75, 0x06, // 0: jne 8 [+6]
          0x90,       // 2: nop
          0x90,       // 3: nop
          0x90,       // 4: nop
          0x90,       // 5: nop
          0xff, 0x10, // 6: callq *(%rax)
          0x0f, 0x0b, // 8: ud2
      },
      {0xDEADBEEF, 0x0});
  uint64_t PrevSearchLengthForConditionalBranch =
      SearchLengthForConditionalBranch;
  SearchLengthForConditionalBranch = 2;
  GraphResult Result =
      GraphBuilder::buildFlowGraph(Analysis, {0xDEADBEEF + 6, 0x0});
  EXPECT_THAT(Result.OrphanedNodes, SizeIs(1));
  EXPECT_THAT(Result.OrphanedNodes,
              Each(HasPath(Result, ElementsAre(0xDEADBEEF + 4, 0xDEADBEEF + 5,
                                               0xDEADBEEF + 6))))
      << PrintToString(Result);
  EXPECT_THAT(Result.ConditionalBranchNodes, IsEmpty());
  SearchLengthForConditionalBranch = PrevSearchLengthForConditionalBranch;
}
TEST_F(BasicGraphBuilderTest, BuildFlowGraphLengthExceededDownwards) {
  if (!SuccessfullyInitialised)
    return;
  Analysis.parseSectionContents(
      {
          0x75, 0x02, // 0: jne 4 [+2]
          0xff, 0x10, // 2: callq *(%rax)
          0x90,       // 4: nop
          0x90,       // 5: nop
          0x90,       // 6: nop
          0x90,       // 7: nop
          0x0f, 0x0b, // 8: ud2
      },
      {0xDEADBEEF, 0x0});
  uint64_t PrevSearchLengthForUndef = SearchLengthForUndef;
  SearchLengthForUndef = 2;
  GraphResult Result =
      GraphBuilder::buildFlowGraph(Analysis, {0xDEADBEEF + 2, 0x0});
  EXPECT_THAT(Result.OrphanedNodes, IsEmpty());
  EXPECT_THAT(
      Result.ConditionalBranchNodes,
      Each(AllOf(
          Field(&ConditionalBranchNode::CFIProtection, Eq(false)),
          Field(&ConditionalBranchNode::Address, Eq(0xDEADBEEF)),
          Field(&ConditionalBranchNode::Target,
                HasPath(Result, ElementsAre(0xDEADBEEF + 4, 0xDEADBEEF + 5))),
          Field(&ConditionalBranchNode::Fallthrough,
                HasPath(Result, ElementsAre(0xDEADBEEF + 2))))))
      << PrintToString(Result);
  SearchLengthForUndef = PrevSearchLengthForUndef;
}
// This test ensures when avoiding doing repeated work we still generate the
// paths correctly. We don't need to recalculate the flow from 0x2 -> 0x3 as it
// should only need to be generated once.
TEST_F(BasicGraphBuilderTest, BuildFlowGraphWithRepeatedWork) {
  if (!SuccessfullyInitialised)
    return;
  Analysis.parseSectionContents(
      {
          0x75, 0x05, // 0: jne 7 [+5]
          0x90,       // 2: nop
          0xff, 0x10, // 3: callq *(%rax)
          0x75, 0xfb, // 5: jne 2 [-5]
          0x0f, 0x0b, // 7: ud2
      },
      {0xDEADBEEF, 0x0});
  GraphResult Result =
      GraphBuilder::buildFlowGraph(Analysis, {0xDEADBEEF + 3, 0x0});
  EXPECT_THAT(Result.OrphanedNodes, IsEmpty());
  EXPECT_THAT(Result.ConditionalBranchNodes, SizeIs(2));
  EXPECT_THAT(
      Result.ConditionalBranchNodes,
      Contains(AllOf(
          Field(&ConditionalBranchNode::CFIProtection, Eq(true)),
          Field(&ConditionalBranchNode::Address, Eq(0xDEADBEEF)),
          Field(&ConditionalBranchNode::Target,
                HasPath(Result, ElementsAre(0xDEADBEEF + 7))),
          Field(&ConditionalBranchNode::Fallthrough,
                HasPath(Result, ElementsAre(0xDEADBEEF + 2, 0xDEADBEEF + 3))))))
      << PrintToString(Result);
  EXPECT_THAT(
      Result.ConditionalBranchNodes,
      Contains(AllOf(
          Field(&ConditionalBranchNode::CFIProtection, Eq(true)),
          Field(&ConditionalBranchNode::Address, Eq(0xDEADBEEF + 5)),
          Field(&ConditionalBranchNode::Target,
                HasPath(Result, ElementsAre(0xDEADBEEF + 2, 0xDEADBEEF + 3))),
          Field(&ConditionalBranchNode::Fallthrough,
                HasPath(Result, ElementsAre(0xDEADBEEF + 7))))))
      << PrintToString(Result);
  EXPECT_THAT(Result.IntermediateNodes, SizeIs(1));
  EXPECT_THAT(Result.IntermediateNodes,
              UnorderedElementsAre(Pair(0xDEADBEEF + 2, 0xDEADBEEF + 3)));
}
TEST_F(BasicGraphBuilderTest, BuildFlowGraphComplexExample) {
  if (!SuccessfullyInitialised)
    return;
  // The following code has this graph:
  //  +----------+      +--------------+
  //  |    20    | <--- |      0       |
  //  +----------+      +--------------+
  //    |                 |
  //    v                 v
  //  +----------+      +--------------+
  //  |    21    |      |      2       |
  //  +----------+      +--------------+
  //    |                 |
  //    v                 v
  //  +----------+      +--------------+
  //  | 22 (ud2) |  +-> |      7       |
  //  +----------+  |   +--------------+
  //    ^           |     |
  //    |           |     v
  //  +----------+  |   +--------------+
  //  |    4     |  |   |      8       |
  //  +----------+  |   +--------------+
  //    |           |     |
  //    v           |     v
  //  +----------+  |   +--------------+    +------------+
  //  |    6     | -+   | 9 (indirect) | <- |     13     |
  //  +----------+      +--------------+    +------------+
  //                      ^                   |
  //                      |                   v
  //                    +--------------+    +------------+
  //                    |      11      |    | 15 (error) |
  //                    +--------------+    +------------+
  // Or, in image format: https://i.imgur.com/aX5fCoi.png
  Analysis.parseSectionContents(
      {
          0x75, 0x12,                   // 0: jne 20 [+18]
          0xeb, 0x03,                   // 2: jmp 7 [+3]
          0x75, 0x10,                   // 4: jne 22 [+16]
          0x90,                         // 6: nop
          0x90,                         // 7: nop
          0x90,                         // 8: nop
          0xff, 0x10,                   // 9: callq *(%rax)
          0xeb, 0xfc,                   // 11: jmp 9 [-4]
          0x75, 0xfa,                   // 13: jne 9 [-6]
          0xe8, 0x78, 0x56, 0x34, 0x12, // 15: callq OUTOFBOUNDS [+0x12345678]
          0x90,                         // 20: nop
          0x90,                         // 21: nop
          0x0f, 0x0b,                   // 22: ud2
      },
      {0x1000, 0x0});
  uint64_t PrevSearchLengthForUndef = SearchLengthForUndef;
  SearchLengthForUndef = 5;
  GraphResult Result =
      GraphBuilder::buildFlowGraph(Analysis, {0x1000 + 9, 0x0});
  EXPECT_THAT(Result.OrphanedNodes, SizeIs(1));
  EXPECT_THAT(Result.ConditionalBranchNodes, SizeIs(3));
  EXPECT_THAT(
      Result.OrphanedNodes,
      Each(AllOf(Eq(0x1000u + 11),
                 HasPath(Result, ElementsAre(0x1000 + 11, 0x1000 + 9)))))
      << PrintToString(Result);
  EXPECT_THAT(Result.ConditionalBranchNodes,
              Contains(AllOf(
                  Field(&ConditionalBranchNode::CFIProtection, Eq(true)),
                  Field(&ConditionalBranchNode::Address, Eq(0x1000u)),
                  Field(&ConditionalBranchNode::Target,
                        HasPath(Result, ElementsAre(0x1000 + 20, 0x1000 + 21,
                                                    0x1000 + 22))),
                  Field(&ConditionalBranchNode::Fallthrough,
                        HasPath(Result, ElementsAre(0x1000 + 2, 0x1000 + 7,
                                                    0x1000 + 8, 0x1000 + 9))))))
      << PrintToString(Result);
  EXPECT_THAT(Result.ConditionalBranchNodes,
              Contains(AllOf(
                  Field(&ConditionalBranchNode::CFIProtection, Eq(true)),
                  Field(&ConditionalBranchNode::Address, Eq(0x1000u + 4)),
                  Field(&ConditionalBranchNode::Target,
                        HasPath(Result, ElementsAre(0x1000 + 22))),
                  Field(&ConditionalBranchNode::Fallthrough,
                        HasPath(Result, ElementsAre(0x1000 + 6, 0x1000 + 7,
                                                    0x1000 + 8, 0x1000 + 9))))))
      << PrintToString(Result);
  EXPECT_THAT(
      Result.ConditionalBranchNodes,
      Contains(AllOf(Field(&ConditionalBranchNode::CFIProtection, Eq(false)),
                     Field(&ConditionalBranchNode::Address, Eq(0x1000u + 13)),
                     Field(&ConditionalBranchNode::Target,
                           HasPath(Result, ElementsAre(0x1000 + 9))),
                     Field(&ConditionalBranchNode::Fallthrough,
                           HasPath(Result, ElementsAre(0x1000 + 15))))))
      << PrintToString(Result);
  SearchLengthForUndef = PrevSearchLengthForUndef;
}
} // anonymous namespace
} // end namespace cfi_verify
} // end namespace llvm