{"owner":"nuudlman","repo":"llvm","channel":"main","channels":["main"],"can_delete":true,"inode":{"File":{"path":[{"basename":"clang","pos":"7OVOGA6QKF5OI.EJBFAJQ","meta":576},{"basename":"test","pos":"7OVOGA6QKF5OI.RXSO6JQ","meta":576},{"basename":"CodeGen","pos":"7OVOGA6QKF5OI.GFHJKKY","meta":576},{"basename":"aarch64-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c","pos":"7OVOGA6QKF5OI.G4QYWLA","meta":0}],"file":"// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s -mvscale-min=1 -mvscale-max=1 | FileCheck %s -D#VBITS=128 --check-prefixes=CHECK128\n// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s -mvscale-min=2 -mvscale-max=2 | FileCheck %s -D#VBITS=256 --check-prefixes=CHECK,CHECK256\n// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s -mvscale-min=4 -mvscale-max=4 | FileCheck %s -D#VBITS=512 --check-prefixes=CHECK,CHECK512\n// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s -mvscale-min=8 -mvscale-max=8 | FileCheck %s -D#VBITS=1024 --check-prefixes=CHECK,CHECK1024\n// RUN: %clang_cc1 -no-opaque-pointers -triple aarch64-none-linux-gnu -target-feature +sve -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s -mvscale-min=16 -mvscale-max=16 | FileCheck %s -D#VBITS=2048 --check-prefixes=CHECK,CHECK2048\n\n// REQUIRES: aarch64-registered-target\n\n// Examples taken from section \"3.7.3.3 Behavior specific to SVE\n// vectors\" of the SVE ACLE (Version 00bet6) that can be found at\n// https://developer.arm.com/documentation/100987/latest\n//\n// Example has been expanded to work with mutiple values of\n// -mvscale-{min,max}.\n\n#include \n\n// Page 27, item 1\n#if __ARM_FEATURE_SVE_BITS == 256 && __ARM_FEATURE_SVE_VECTOR_OPERATORS\n// CHECK256-LABEL: @x256 ={{.*}} local_unnamed_addr global <4 x i64> , align 16\ntypedef svint64_t vec256 __attribute__((arm_sve_vector_bits(256)));\nvec256 x256 = {0, 1, 2, 3};\n#endif\n\n#if __ARM_FEATURE_SVE_BITS == 512 && __ARM_FEATURE_SVE_VECTOR_OPERATORS\n// CHECK512-LABEL: @x512 ={{.*}} local_unnamed_addr global <8 x i64> , align 16\ntypedef svint64_t vec512 __attribute__((arm_sve_vector_bits(512)));\nvec512 x512 = {0, 1, 2, 3, 3 , 2 , 1, 0};\n#endif\n\n#if __ARM_FEATURE_SVE_BITS == 1024 && __ARM_FEATURE_SVE_VECTOR_OPERATORS\n// CHECK1024-LABEL: @x1024 ={{.*}} local_unnamed_addr global <16 x i64> , align 16\ntypedef svint64_t vec1024 __attribute__((arm_sve_vector_bits(1024)));\nvec1024 x1024 = {0, 1, 2, 3, 3 , 2 , 1, 0, 0, 1, 2, 3, 3 , 2 , 1, 0};\n#endif\n\n#if __ARM_FEATURE_SVE_BITS == 2048 && __ARM_FEATURE_SVE_VECTOR_OPERATORS\n// CHECK2048-LABEL: @x2048 ={{.*}} local_unnamed_addr global <32 x i64> , align 16\ntypedef svint64_t vec2048 __attribute__((arm_sve_vector_bits(2048)));\nvec2048 x2048 = {0, 1, 2, 3, 3 , 2 , 1, 0, 0, 1, 2, 3, 3 , 2 , 1, 0,\n 0, 1, 2, 3, 3 , 2 , 1, 0, 0, 1, 2, 3, 3 , 2 , 1, 0};\n#endif\n\n// Page 27, item 2. We can not change the ABI of existing vector\n// types, including vec_int8. That's why in the SVE ACLE, VLST is\n// distinct from, but mostly interchangeable with, the corresponding\n// GNUT. VLST is treated for ABI purposes like an SVE type but GNUT\n// continues to be a normal GNU vector type, with base Armv8-A PCS\n// rules.\n#if __ARM_FEATURE_SVE_BITS && __ARM_FEATURE_SVE_VECTOR_OPERATORS\n#define N __ARM_FEATURE_SVE_BITS\ntypedef int8_t vec_int8 __attribute__((vector_size(N / 8)));\n// CHECK128-LABEL: define{{.*}} <16 x i8> @f2(<16 x i8> noundef %x)\n// CHECK128-NEXT: entry:\n// CHECK128-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)\n// CHECK128-NEXT: [[CASTSCALABLESVE:%.*]] = tail call @llvm.vector.insert.nxv16i8.v16i8( undef, <16 x i8> [[X:%.*]], i64 0)\n// CHECK128-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.asrd.nxv16i8( [[TMP0]], [[CASTSCALABLESVE]], i32 1)\n// CHECK128-NEXT: [[CASTFIXEDSVE:%.*]] = tail call <16 x i8> @llvm.vector.extract.v16i8.nxv16i8( [[TMP1]], i64 0)\n// CHECK128-NEXT: ret <16 x i8> [[CASTFIXEDSVE]]\n\n// CHECK-LABEL: define{{.*}} void @f2(\n// CHECK-SAME: <[[#div(VBITS,8)]] x i8>* noalias nocapture writeonly sret(<[[#div(VBITS,8)]] x i8>) align 16 %agg.result, <[[#div(VBITS,8)]] x i8>* nocapture noundef readonly %0)\n// CHECK-NEXT: entry:\n// CHECK-NEXT: [[X:%.*]] = load <[[#div(VBITS,8)]] x i8>, <[[#div(VBITS,8)]] x i8>* [[TMP0:%.*]], align 16, [[TBAA6:!tbaa !.*]]\n// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)\n// CHECK-NEXT: [[CASTSCALABLESVE:%.*]] = tail call @llvm.vector.insert.nxv16i8.v[[#div(VBITS,8)]]i8( undef, <[[#div(VBITS,8)]] x i8> [[X]], i64 0)\n// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.aarch64.sve.asrd.nxv16i8( [[TMP1]], [[CASTSCALABLESVE]], i32 1)\n// CHECK-NEXT: [[CASTFIXEDSVE:%.*]] = tail call <[[#div(VBITS,8)]] x i8> @llvm.vector.extract.v[[#div(VBITS,8)]]i8.nxv16i8( [[TMP2]], i64 0)\n// CHECK-NEXT: store <[[#div(VBITS,8)]] x i8> [[CASTFIXEDSVE]], <[[#div(VBITS,8)]] x i8>* [[AGG_RESULT:%.*]], align 16, [[TBAA6]]\n// CHECK-NEXT: ret void\nvec_int8 f2(vec_int8 x) { return svasrd_x(svptrue_b8(), x, 1); }\n#endif\n\n// Page 27, item 3.\n#if __ARM_FEATURE_SVE_BITS && __ARM_FEATURE_SVE_VECTOR_OPERATORS\n#define N __ARM_FEATURE_SVE_BITS\ntypedef int8_t vec1 __attribute__((vector_size(N / 8)));\nvoid f3(vec1);\ntypedef svint8_t vec2 __attribute__((arm_sve_vector_bits(N)));\n\n// CHECK128-LABEL: define{{.*}} void @g( noundef %x.coerce)\n// CHECK128-NEXT: entry:\n// CHECK128-NEXT: [[X:%.*]] = tail call <16 x i8> @llvm.vector.extract.v16i8.nxv16i8( [[X_COERCE:%.*]], i64 0)\n// CHECK128-NEXT: call void @f3(<16 x i8> noundef [[X]]) [[ATTR5:#.*]]\n// CHECK128-NEXT: ret void\n\n// CHECK-LABEL: define{{.*}} void @g( noundef %x.coerce)\n// CHECK-NEXT: entry:\n// CHECK-NEXT: [[INDIRECT_ARG_TEMP:%.*]] = alloca <[[#div(VBITS,8)]] x i8>, align 16\n// CHECK-NEXT: [[X:%.*]] = tail call <[[#div(VBITS,8)]] x i8> @llvm.vector.extract.v[[#div(VBITS,8)]]i8.nxv16i8( [[X_COERCE:%.*]], i64 0)\n// CHECK-NEXT: store <[[#div(VBITS,8)]] x i8> [[X]], <[[#div(VBITS,8)]] x i8>* [[INDIRECT_ARG_TEMP]], align 16, [[TBAA6]]\n// CHECK-NEXT: call void @f3(<[[#div(VBITS,8)]] x i8>* noundef nonnull [[INDIRECT_ARG_TEMP]]) [[ATTR5:#.*]]\n// CHECK-NEXT: ret void\n\n// CHECK128-LABEL: declare void @f3(<16 x i8> noundef)\n\n// CHECK-LABEL: declare void @f3(\n// CHECK-SAME: <[[#div(VBITS,8)]] x i8>* noundef)\nvoid g(vec2 x) { f3(x); } // OK\n#endif\n"}},"token":"S9IXolU40Il5QZcV+Hk7VPgZCfIw137X/i+N6na7d3s=","login":null}