{"owner":"nuudlman","repo":"llvm","channel":"main","channels":["main"],"can_delete":true,"inode":{"File":{"path":[{"basename":"clang","pos":"7OVOGA6QKF5OI.EJBFAJQ","meta":576},{"basename":"test","pos":"7OVOGA6QKF5OI.RXSO6JQ","meta":576},{"basename":"CodeGen","pos":"7OVOGA6QKF5OI.GFHJKKY","meta":576},{"basename":"aarch64-v8.2a-neon-intrinsics-constrained.c","pos":"7OVOGA6QKF5OI.QMMQ6LA","meta":0}],"file":"// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.2a\\\n// RUN: -fallow-half-arguments-and-returns -flax-vector-conversions=none -S -disable-O0-optnone -emit-llvm -o - %s \\\n// RUN: | opt -S -mem2reg \\\n// RUN: | FileCheck --check-prefix=COMMON --check-prefix=COMMONIR --check-prefix=UNCONSTRAINED %s\n// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.2a\\\n// RUN: -ffp-exception-behavior=maytrap -DEXCEPT=1 \\\n// RUN: -fexperimental-strict-floating-point \\\n// RUN: -fallow-half-arguments-and-returns -flax-vector-conversions=none -S -disable-O0-optnone -emit-llvm -o - %s \\\n// RUN: | opt -S -mem2reg \\\n// RUN: | FileCheck --check-prefix=COMMON --check-prefix=COMMONIR --check-prefix=CONSTRAINED %s\n// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.2a\\\n// RUN: -fallow-half-arguments-and-returns -flax-vector-conversions=none -S -disable-O0-optnone -emit-llvm -o - %s \\\n// RUN: | opt -S -mem2reg | llc -o=- - \\\n// RUN: | FileCheck --check-prefix=COMMON --check-prefix=CHECK-ASM %s\n// RUN: %clang_cc1 -triple arm64-none-linux-gnu -target-feature +neon -target-feature +fullfp16 -target-feature +v8.2a\\\n// RUN: -ffp-exception-behavior=maytrap -DEXCEPT=1 \\\n// RUN: -fexperimental-strict-floating-point \\\n// RUN: -fallow-half-arguments-and-returns -flax-vector-conversions=none -S -disable-O0-optnone -emit-llvm -o - %s \\\n// RUN: | opt -S -mem2reg | llc -o=- - \\\n// RUN: | FileCheck --check-prefix=COMMON --check-prefix=CHECK-ASM %s\n\n// REQUIRES: aarch64-registered-target\n\n// Test that the constrained intrinsics are picking up the exception\n// metadata from the AST instead of the global default from the command line.\n// FIXME: All cases of \"fpexcept.maytrap\" in this test are wrong.\n\n#if EXCEPT\n#pragma float_control(except, on)\n#endif\n\n#include \n\n// COMMON-LABEL: test_vsqrt_f16\n// UNCONSTRAINED: [[SQR:%.*]] = call <4 x half> @llvm.sqrt.v4f16(<4 x half> %a)\n// CONSTRAINED: [[SQR:%.*]] = call <4 x half> @llvm.experimental.constrained.sqrt.v4f16(<4 x half> %a, metadata !\"round.tonearest\", metadata !\"fpexcept.maytrap\")\n// CHECK-ASM: fsqrt v{{[0-9]+}}.4h, v{{[0-9]+}}.4h\n// COMMONIR: ret <4 x half> [[SQR]]\nfloat16x4_t test_vsqrt_f16(float16x4_t a) {\n return vsqrt_f16(a);\n}\n\n// COMMON-LABEL: test_vsqrtq_f16\n// UNCONSTRAINED: [[SQR:%.*]] = call <8 x half> @llvm.sqrt.v8f16(<8 x half> %a)\n// CONSTRAINED: [[SQR:%.*]] = call <8 x half> @llvm.experimental.constrained.sqrt.v8f16(<8 x half> %a, metadata !\"round.tonearest\", metadata !\"fpexcept.maytrap\")\n// CHECK-ASM: fsqrt v{{[0-9]+}}.8h, v{{[0-9]+}}.8h\n// COMMONIR: ret <8 x half> [[SQR]]\nfloat16x8_t test_vsqrtq_f16(float16x8_t a) {\n return vsqrtq_f16(a);\n}\n\n// COMMON-LABEL: test_vfma_f16\n// UNCONSTRAINED: [[ADD:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half> %b, <4 x half> %c, <4 x half> %a)\n// CONSTRAINED: [[ADD:%.*]] = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> %b, <4 x half> %c, <4 x half> %a, metadata !\"round.tonearest\", metadata !\"fpexcept.maytrap\")\n// CHECK-ASM: fmla v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h\n// COMMONIR: ret <4 x half> [[ADD]]\nfloat16x4_t test_vfma_f16(float16x4_t a, float16x4_t b, float16x4_t c) {\n return vfma_f16(a, b, c);\n}\n\n// COMMON-LABEL: test_vfmaq_f16\n// UNCONSTRAINED: [[ADD:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half> %b, <8 x half> %c, <8 x half> %a)\n// CONSTRAINED: [[ADD:%.*]] = call <8 x half> @llvm.experimental.constrained.fma.v8f16(<8 x half> %b, <8 x half> %c, <8 x half> %a, metadata !\"round.tonearest\", metadata !\"fpexcept.maytrap\")\n// CHECK-ASM: fmla v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h\n// COMMONIR: ret <8 x half> [[ADD]]\nfloat16x8_t test_vfmaq_f16(float16x8_t a, float16x8_t b, float16x8_t c) {\n return vfmaq_f16(a, b, c);\n}\n\n// COMMON-LABEL: test_vfms_f16\n// COMMONIR: [[SUB:%.*]] = fneg <4 x half> %b\n// UNCONSTRAINED: [[ADD:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half> [[SUB]], <4 x half> %c, <4 x half> %a)\n// CONSTRAINED: [[ADD:%.*]] = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> [[SUB]], <4 x half> %c, <4 x half> %a, metadata !\"round.tonearest\", metadata !\"fpexcept.maytrap\")\n// CHECK-ASM: fmls v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.4h\n// COMMONIR: ret <4 x half> [[ADD]]\nfloat16x4_t test_vfms_f16(float16x4_t a, float16x4_t b, float16x4_t c) {\n return vfms_f16(a, b, c);\n}\n\n// COMMON-LABEL: test_vfmsq_f16\n// COMMONIR: [[SUB:%.*]] = fneg <8 x half> %b\n// UNCONSTRAINED: [[ADD:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half> [[SUB]], <8 x half> %c, <8 x half> %a)\n// CONSTRAINED: [[ADD:%.*]] = call <8 x half> @llvm.experimental.constrained.fma.v8f16(<8 x half> [[SUB]], <8 x half> %c, <8 x half> %a, metadata !\"round.tonearest\", metadata !\"fpexcept.maytrap\")\n// CHECK-ASM: fmls v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.8h\n// COMMONIR: ret <8 x half> [[ADD]]\nfloat16x8_t test_vfmsq_f16(float16x8_t a, float16x8_t b, float16x8_t c) {\n return vfmsq_f16(a, b, c);\n}\n\n// COMMON-LABEL: test_vfma_lane_f16\n// COMMONIR: [[TMP0:%.*]] = bitcast <4 x half> %a to <8 x i8>\n// COMMONIR: [[TMP1:%.*]] = bitcast <4 x half> %b to <8 x i8>\n// COMMONIR: [[TMP2:%.*]] = bitcast <4 x half> %c to <8 x i8>\n// COMMONIR: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x half>\n// COMMONIR: [[LANE:%.*]] = shufflevector <4 x half> [[TMP3]], <4 x half> [[TMP3]], <4 x i32> \n// COMMONIR: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half>\n// COMMONIR: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half>\n// UNCONSTRAINED: [[FMLA:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half> [[TMP4]], <4 x half> [[LANE]], <4 x half> [[TMP5]])\n// CONSTRAINED: [[FMLA:%.*]] = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> [[TMP4]], <4 x half> [[LANE]], <4 x half> [[TMP5]], metadata !\"round.tonearest\", metadata !\"fpexcept.maytrap\")\n// CHECK-ASM: fmla v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.h[{{[0-9]+}}]\n// COMMONIR: ret <4 x half> [[FMLA]]\nfloat16x4_t test_vfma_lane_f16(float16x4_t a, float16x4_t b, float16x4_t c) {\n return vfma_lane_f16(a, b, c, 3);\n}\n\n// COMMON-LABEL: test_vfmaq_lane_f16\n// COMMONIR: [[TMP0:%.*]] = bitcast <8 x half> %a to <16 x i8>\n// COMMONIR: [[TMP1:%.*]] = bitcast <8 x half> %b to <16 x i8>\n// COMMONIR: [[TMP2:%.*]] = bitcast <4 x half> %c to <8 x i8>\n// COMMONIR: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x half>\n// COMMONIR: [[LANE:%.*]] = shufflevector <4 x half> [[TMP3]], <4 x half> [[TMP3]], <8 x i32> \n// COMMONIR: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>\n// COMMONIR: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half>\n// UNCONSTRAINED: [[FMLA:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half> [[TMP4]], <8 x half> [[LANE]], <8 x half> [[TMP5]])\n// CONSTRAINED: [[FMLA:%.*]] = call <8 x half> @llvm.experimental.constrained.fma.v8f16(<8 x half> [[TMP4]], <8 x half> [[LANE]], <8 x half> [[TMP5]], metadata !\"round.tonearest\", metadata !\"fpexcept.maytrap\")\n// CHECK-ASM: fmla v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.h[{{[0-9]+}}]\n// COMMONIR: ret <8 x half> [[FMLA]]\nfloat16x8_t test_vfmaq_lane_f16(float16x8_t a, float16x8_t b, float16x4_t c) {\n return vfmaq_lane_f16(a, b, c, 3);\n}\n\n// COMMON-LABEL: test_vfma_laneq_f16\n// COMMONIR: [[TMP0:%.*]] = bitcast <4 x half> %a to <8 x i8>\n// COMMONIR: [[TMP1:%.*]] = bitcast <4 x half> %b to <8 x i8>\n// COMMONIR: [[TMP2:%.*]] = bitcast <8 x half> %c to <16 x i8>\n// COMMONIR: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half>\n// COMMONIR: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half>\n// COMMONIR: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x half>\n// COMMONIR: [[LANE:%.*]] = shufflevector <8 x half> [[TMP5]], <8 x half> [[TMP5]], <4 x i32> \n// UNCONSTRAINED: [[FMLA:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half> [[LANE]], <4 x half> [[TMP4]], <4 x half> [[TMP3]])\n// CONSTRAINED: [[FMLA:%.*]] = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> [[LANE]], <4 x half> [[TMP4]], <4 x half> [[TMP3]], metadata !\"round.tonearest\", metadata !\"fpexcept.maytrap\")\n// CHECK-ASM: fmla v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.h[{{[0-9]+}}]\n// COMMONIR: ret <4 x half> [[FMLA]]\nfloat16x4_t test_vfma_laneq_f16(float16x4_t a, float16x4_t b, float16x8_t c) {\n return vfma_laneq_f16(a, b, c, 7);\n}\n\n// COMMON-LABEL: test_vfmaq_laneq_f16\n// COMMONIR: [[TMP0:%.*]] = bitcast <8 x half> %a to <16 x i8>\n// COMMONIR: [[TMP1:%.*]] = bitcast <8 x half> %b to <16 x i8>\n// COMMONIR: [[TMP2:%.*]] = bitcast <8 x half> %c to <16 x i8>\n// COMMONIR: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half>\n// COMMONIR: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>\n// COMMONIR: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x half>\n// COMMONIR: [[LANE:%.*]] = shufflevector <8 x half> [[TMP5]], <8 x half> [[TMP5]], <8 x i32> \n// UNCONSTRAINED: [[FMLA:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half> [[LANE]], <8 x half> [[TMP4]], <8 x half> [[TMP3]])\n// CONSTRAINED: [[FMLA:%.*]] = call <8 x half> @llvm.experimental.constrained.fma.v8f16(<8 x half> [[LANE]], <8 x half> [[TMP4]], <8 x half> [[TMP3]], metadata !\"round.tonearest\", metadata !\"fpexcept.maytrap\")\n// CHECK-ASM: fmla v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.h[{{[0-9]+}}]\n// COMMONIR: ret <8 x half> [[FMLA]]\nfloat16x8_t test_vfmaq_laneq_f16(float16x8_t a, float16x8_t b, float16x8_t c) {\n return vfmaq_laneq_f16(a, b, c, 7);\n}\n\n// COMMON-LABEL: test_vfma_n_f16\n// COMMONIR: [[TMP0:%.*]] = insertelement <4 x half> undef, half %c, i32 0\n// COMMONIR: [[TMP1:%.*]] = insertelement <4 x half> [[TMP0]], half %c, i32 1\n// COMMONIR: [[TMP2:%.*]] = insertelement <4 x half> [[TMP1]], half %c, i32 2\n// COMMONIR: [[TMP3:%.*]] = insertelement <4 x half> [[TMP2]], half %c, i32 3\n// UNCONSTRAINED: [[FMA:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half> %b, <4 x half> [[TMP3]], <4 x half> %a)\n// CONSTRAINED: [[FMA:%.*]] = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> %b, <4 x half> [[TMP3]], <4 x half> %a, metadata !\"round.tonearest\", metadata !\"fpexcept.maytrap\")\n// CHECK-ASM: fmla v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.h[{{[0-9]+}}]\n// COMMONIR: ret <4 x half> [[FMA]]\nfloat16x4_t test_vfma_n_f16(float16x4_t a, float16x4_t b, float16_t c) {\n return vfma_n_f16(a, b, c);\n}\n\n// COMMON-LABEL: test_vfmaq_n_f16\n// COMMONIR: [[TMP0:%.*]] = insertelement <8 x half> undef, half %c, i32 0\n// COMMONIR: [[TMP1:%.*]] = insertelement <8 x half> [[TMP0]], half %c, i32 1\n// COMMONIR: [[TMP2:%.*]] = insertelement <8 x half> [[TMP1]], half %c, i32 2\n// COMMONIR: [[TMP3:%.*]] = insertelement <8 x half> [[TMP2]], half %c, i32 3\n// COMMONIR: [[TMP4:%.*]] = insertelement <8 x half> [[TMP3]], half %c, i32 4\n// COMMONIR: [[TMP5:%.*]] = insertelement <8 x half> [[TMP4]], half %c, i32 5\n// COMMONIR: [[TMP6:%.*]] = insertelement <8 x half> [[TMP5]], half %c, i32 6\n// COMMONIR: [[TMP7:%.*]] = insertelement <8 x half> [[TMP6]], half %c, i32 7\n// UNCONSTRAINED: [[FMA:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half> %b, <8 x half> [[TMP7]], <8 x half> %a)\n// CONSTRAINED: [[FMA:%.*]] = call <8 x half> @llvm.experimental.constrained.fma.v8f16(<8 x half> %b, <8 x half> [[TMP7]], <8 x half> %a, metadata !\"round.tonearest\", metadata !\"fpexcept.maytrap\")\n// CHECK-ASM: fmla v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.h[{{[0-9]+}}]\n// COMMONIR: ret <8 x half> [[FMA]]\nfloat16x8_t test_vfmaq_n_f16(float16x8_t a, float16x8_t b, float16_t c) {\n return vfmaq_n_f16(a, b, c);\n}\n\n// COMMON-LABEL: test_vfmah_lane_f16\n// COMMONIR: [[EXTR:%.*]] = extractelement <4 x half> %c, i32 3\n// UNCONSTRAINED: [[FMA:%.*]] = call half @llvm.fma.f16(half %b, half [[EXTR]], half %a)\n// CONSTRAINED: [[FMA:%.*]] = call half @llvm.experimental.constrained.fma.f16(half %b, half [[EXTR]], half %a, metadata !\"round.tonearest\", metadata !\"fpexcept.maytrap\")\n// CHECK-ASM: fmla h{{[0-9]+}}, h{{[0-9]+}}, v{{[0-9]+}}.h[{{[0-9]+}}]\n// COMMONIR: ret half [[FMA]]\nfloat16_t test_vfmah_lane_f16(float16_t a, float16_t b, float16x4_t c) {\n return vfmah_lane_f16(a, b, c, 3);\n}\n\n// COMMON-LABEL: test_vfmah_laneq_f16\n// COMMONIR: [[EXTR:%.*]] = extractelement <8 x half> %c, i32 7\n// UNCONSTRAINED: [[FMA:%.*]] = call half @llvm.fma.f16(half %b, half [[EXTR]], half %a)\n// CONSTRAINED: [[FMA:%.*]] = call half @llvm.experimental.constrained.fma.f16(half %b, half [[EXTR]], half %a, metadata !\"round.tonearest\", metadata !\"fpexcept.maytrap\")\n// CHECK-ASM: fmla h{{[0-9]+}}, h{{[0-9]+}}, v{{[0-9]+}}.h[{{[0-9]+}}]\n// COMMONIR: ret half [[FMA]]\nfloat16_t test_vfmah_laneq_f16(float16_t a, float16_t b, float16x8_t c) {\n return vfmah_laneq_f16(a, b, c, 7);\n}\n\n// COMMON-LABEL: test_vfms_lane_f16\n// COMMONIR: [[SUB:%.*]] = fneg <4 x half> %b\n// COMMONIR: [[TMP0:%.*]] = bitcast <4 x half> %a to <8 x i8>\n// COMMONIR: [[TMP1:%.*]] = bitcast <4 x half> [[SUB]] to <8 x i8>\n// COMMONIR: [[TMP2:%.*]] = bitcast <4 x half> %c to <8 x i8>\n// COMMONIR: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x half>\n// COMMONIR: [[LANE:%.*]] = shufflevector <4 x half> [[TMP3]], <4 x half> [[TMP3]], <4 x i32> \n// COMMONIR: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half>\n// COMMONIR: [[TMP5:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half>\n// UNCONSTRAINED: [[FMA:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half> [[TMP4]], <4 x half> [[LANE]], <4 x half> [[TMP5]])\n// CONSTRAINED: [[FMA:%.*]] = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> [[TMP4]], <4 x half> [[LANE]], <4 x half> [[TMP5]], metadata !\"round.tonearest\", metadata !\"fpexcept.maytrap\")\n// CHECK-ASM: fmls v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.h[{{[0-9]+}}]\n// COMMONIR: ret <4 x half> [[FMA]]\nfloat16x4_t test_vfms_lane_f16(float16x4_t a, float16x4_t b, float16x4_t c) {\n return vfms_lane_f16(a, b, c, 3);\n}\n\n// COMMON-LABEL: test_vfmsq_lane_f16\n// COMMONIR: [[SUB:%.*]] = fneg <8 x half> %b\n// COMMONIR: [[TMP0:%.*]] = bitcast <8 x half> %a to <16 x i8>\n// COMMONIR: [[TMP1:%.*]] = bitcast <8 x half> [[SUB]] to <16 x i8>\n// COMMONIR: [[TMP2:%.*]] = bitcast <4 x half> %c to <8 x i8>\n// COMMONIR: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x half>\n// COMMONIR: [[LANE:%.*]] = shufflevector <4 x half> [[TMP3]], <4 x half> [[TMP3]], <8 x i32> \n// COMMONIR: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>\n// COMMONIR: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half>\n// UNCONSTRAINED: [[FMLA:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half> [[TMP4]], <8 x half> [[LANE]], <8 x half> [[TMP5]])\n// CONSTRAINED: [[FMLA:%.*]] = call <8 x half> @llvm.experimental.constrained.fma.v8f16(<8 x half> [[TMP4]], <8 x half> [[LANE]], <8 x half> [[TMP5]], metadata !\"round.tonearest\", metadata !\"fpexcept.maytrap\")\n// CHECK-ASM: fmls v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.h[{{[0-9]+}}]\n// COMMONIR: ret <8 x half> [[FMLA]]\nfloat16x8_t test_vfmsq_lane_f16(float16x8_t a, float16x8_t b, float16x4_t c) {\n return vfmsq_lane_f16(a, b, c, 3);\n}\n\n// COMMON-LABEL: test_vfms_laneq_f16\n// COMMONIR: [[SUB:%.*]] = fneg <4 x half> %b\n// CHECK-ASM-NOT: fneg\n// COMMONIR: [[TMP0:%.*]] = bitcast <4 x half> %a to <8 x i8>\n// COMMONIR: [[TMP1:%.*]] = bitcast <4 x half> [[SUB]] to <8 x i8>\n// COMMONIR: [[TMP2:%.*]] = bitcast <8 x half> %c to <16 x i8>\n// COMMONIR: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x half>\n// COMMONIR: [[TMP4:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x half>\n// COMMONIR: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x half>\n// COMMONIR: [[LANE:%.*]] = shufflevector <8 x half> [[TMP5]], <8 x half> [[TMP5]], <4 x i32> \n// UNCONSTRAINED: [[FMLA:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half> [[LANE]], <4 x half> [[TMP4]], <4 x half> [[TMP3]])\n// CONSTRAINED: [[FMLA:%.*]] = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> [[LANE]], <4 x half> [[TMP4]], <4 x half> [[TMP3]], metadata !\"round.tonearest\", metadata !\"fpexcept.maytrap\")\n// CHECK-ASM: fmls v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.h[{{[0-9]+}}]\n// COMMONIR: ret <4 x half> [[FMLA]]\nfloat16x4_t test_vfms_laneq_f16(float16x4_t a, float16x4_t b, float16x8_t c) {\n return vfms_laneq_f16(a, b, c, 7);\n}\n\n// COMMON-LABEL: test_vfmsq_laneq_f16\n// COMMONIR: [[SUB:%.*]] = fneg <8 x half> %b\n// CHECK-ASM-NOT: fneg\n// COMMONIR: [[TMP0:%.*]] = bitcast <8 x half> %a to <16 x i8>\n// COMMONIR: [[TMP1:%.*]] = bitcast <8 x half> [[SUB]] to <16 x i8>\n// COMMONIR: [[TMP2:%.*]] = bitcast <8 x half> %c to <16 x i8>\n// COMMONIR: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x half>\n// COMMONIR: [[TMP4:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x half>\n// COMMONIR: [[TMP5:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x half>\n// COMMONIR: [[LANE:%.*]] = shufflevector <8 x half> [[TMP5]], <8 x half> [[TMP5]], <8 x i32> \n// UNCONSTRAINED: [[FMLA:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half> [[LANE]], <8 x half> [[TMP4]], <8 x half> [[TMP3]])\n// CONSTRAINED: [[FMLA:%.*]] = call <8 x half> @llvm.experimental.constrained.fma.v8f16(<8 x half> [[LANE]], <8 x half> [[TMP4]], <8 x half> [[TMP3]], metadata !\"round.tonearest\", metadata !\"fpexcept.maytrap\")\n// CHECK-ASM: fmls v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.h[{{[0-9]+}}]\n// COMMONIR: ret <8 x half> [[FMLA]]\nfloat16x8_t test_vfmsq_laneq_f16(float16x8_t a, float16x8_t b, float16x8_t c) {\n return vfmsq_laneq_f16(a, b, c, 7);\n}\n\n// COMMON-LABEL: test_vfms_n_f16\n// COMMONIR: [[SUB:%.*]] = fneg <4 x half> %b\n// COMMONIR: [[TMP0:%.*]] = insertelement <4 x half> undef, half %c, i32 0\n// COMMONIR: [[TMP1:%.*]] = insertelement <4 x half> [[TMP0]], half %c, i32 1\n// COMMONIR: [[TMP2:%.*]] = insertelement <4 x half> [[TMP1]], half %c, i32 2\n// COMMONIR: [[TMP3:%.*]] = insertelement <4 x half> [[TMP2]], half %c, i32 3\n// UNCONSTRAINED: [[FMA:%.*]] = call <4 x half> @llvm.fma.v4f16(<4 x half> [[SUB]], <4 x half> [[TMP3]], <4 x half> %a)\n// CONSTRAINED: [[FMA:%.*]] = call <4 x half> @llvm.experimental.constrained.fma.v4f16(<4 x half> [[SUB]], <4 x half> [[TMP3]], <4 x half> %a, metadata !\"round.tonearest\", metadata !\"fpexcept.maytrap\")\n// CHECK-ASM: fmls v{{[0-9]+}}.4h, v{{[0-9]+}}.4h, v{{[0-9]+}}.h[{{[0-9]+}}]\n// COMMONIR: ret <4 x half> [[FMA]]\nfloat16x4_t test_vfms_n_f16(float16x4_t a, float16x4_t b, float16_t c) {\n return vfms_n_f16(a, b, c);\n}\n\n// COMMON-LABEL: test_vfmsq_n_f16\n// COMMONIR: [[SUB:%.*]] = fneg <8 x half> %b\n// COMMONIR: [[TMP0:%.*]] = insertelement <8 x half> undef, half %c, i32 0\n// COMMONIR: [[TMP1:%.*]] = insertelement <8 x half> [[TMP0]], half %c, i32 1\n// COMMONIR: [[TMP2:%.*]] = insertelement <8 x half> [[TMP1]], half %c, i32 2\n// COMMONIR: [[TMP3:%.*]] = insertelement <8 x half> [[TMP2]], half %c, i32 3\n// COMMONIR: [[TMP4:%.*]] = insertelement <8 x half> [[TMP3]], half %c, i32 4\n// COMMONIR: [[TMP5:%.*]] = insertelement <8 x half> [[TMP4]], half %c, i32 5\n// COMMONIR: [[TMP6:%.*]] = insertelement <8 x half> [[TMP5]], half %c, i32 6\n// COMMONIR: [[TMP7:%.*]] = insertelement <8 x half> [[TMP6]], half %c, i32 7\n// UNCONSTRAINED: [[FMA:%.*]] = call <8 x half> @llvm.fma.v8f16(<8 x half> [[SUB]], <8 x half> [[TMP7]], <8 x half> %a)\n// CONSTRAINED: [[FMA:%.*]] = call <8 x half> @llvm.experimental.constrained.fma.v8f16(<8 x half> [[SUB]], <8 x half> [[TMP7]], <8 x half> %a, metadata !\"round.tonearest\", metadata !\"fpexcept.maytrap\")\n// CHECK-ASM: fmls v{{[0-9]+}}.8h, v{{[0-9]+}}.8h, v{{[0-9]+}}.h[{{[0-9]+}}]\n// COMMONIR: ret <8 x half> [[FMA]]\nfloat16x8_t test_vfmsq_n_f16(float16x8_t a, float16x8_t b, float16_t c) {\n return vfmsq_n_f16(a, b, c);\n}\n\n// COMMON-LABEL: test_vfmsh_lane_f16\n// UNCONSTRAINED: [[TMP0:%.*]] = fpext half %b to float\n// CONSTRAINED: [[TMP0:%.*]] = call float @llvm.experimental.constrained.fpext.f32.f16(half %b, metadata !\"fpexcept.strict\")\n// CHECK-ASM: fcvt s{{[0-9]+}}, h{{[0-9]+}}\n// COMMONIR: [[TMP1:%.*]] = fneg float [[TMP0]]\n// CHECK-ASM: fneg s{{[0-9]+}}, s{{[0-9]+}}\n// UNCONSTRAINED: [[SUB:%.*]] = fptrunc float [[TMP1]] to half\n// CONSTRAINED: [[SUB:%.*]] = call half @llvm.experimental.constrained.fptrunc.f16.f32(float [[TMP1]], metadata !\"round.tonearest\", metadata !\"fpexcept.strict\")\n// CHECK-ASM: fcvt h{{[0-9]+}}, s{{[0-9]+}}\n// COMMONIR: [[EXTR:%.*]] = extractelement <4 x half> %c, i32 3\n// UNCONSTRAINED: [[FMA:%.*]] = call half @llvm.fma.f16(half [[SUB]], half [[EXTR]], half %a)\n// CONSTRAINED: [[FMA:%.*]] = call half @llvm.experimental.constrained.fma.f16(half [[SUB]], half [[EXTR]], half %a, metadata !\"round.tonearest\", metadata !\"fpexcept.maytrap\")\n// CHECK-ASM: fmla h{{[0-9]+}}, h{{[0-9]+}}, v{{[0-9]+}}.h[{{[0-9]+}}]\n// COMMONIR: ret half [[FMA]]\nfloat16_t test_vfmsh_lane_f16(float16_t a, float16_t b, float16x4_t c) {\n return vfmsh_lane_f16(a, b, c, 3);\n}\n\n// COMMON-LABEL: test_vfmsh_laneq_f16\n// UNCONSTRAINED: [[TMP0:%.*]] = fpext half %b to float\n// CONSTRAINED: [[TMP0:%.*]] = call float @llvm.experimental.constrained.fpext.f32.f16(half %b, metadata !\"fpexcept.strict\")\n// CHECK-ASM: fcvt s{{[0-9]+}}, h{{[0-9]+}}\n// COMMONIR: [[TMP1:%.*]] = fneg float [[TMP0]]\n// CHECK-ASM: fneg s{{[0-9]+}}, s{{[0-9]+}}\n// UNCONSTRAINED: [[SUB:%.*]] = fptrunc float [[TMP1]] to half\n// CONSTRAINED: [[SUB:%.*]] = call half @llvm.experimental.constrained.fptrunc.f16.f32(float [[TMP1]], metadata !\"round.tonearest\", metadata !\"fpexcept.strict\")\n// CHECK-ASM: fcvt h{{[0-9]+}}, s{{[0-9]+}}\n// COMMONIR: [[EXTR:%.*]] = extractelement <8 x half> %c, i32 7\n// UNCONSTRAINED: [[FMA:%.*]] = call half @llvm.fma.f16(half [[SUB]], half [[EXTR]], half %a)\n// CONSTRAINED: [[FMA:%.*]] = call half @llvm.experimental.constrained.fma.f16(half [[SUB]], half [[EXTR]], half %a, metadata !\"round.tonearest\", metadata !\"fpexcept.maytrap\")\n// CHECK-ASM: fmla h{{[0-9]+}}, h{{[0-9]+}}, v{{[0-9]+}}.h[{{[0-9]+}}]\n// COMMONIR: ret half [[FMA]]\nfloat16_t test_vfmsh_laneq_f16(float16_t a, float16_t b, float16x8_t c) {\n return vfmsh_laneq_f16(a, b, c, 7);\n}\n"}},"token":"l24vHB+5rGwGfSI3byisbR6QisbLaz821PqhaYel30s=","login":null}