{"owner":"nuudlman","repo":"llvm","channel":"main","channels":["main"],"can_delete":true,"inode":{"File":{"path":[{"basename":"clang","pos":"7OVOGA6QKF5OI.EJBFAJQ","meta":576},{"basename":"test","pos":"7OVOGA6QKF5OI.RXSO6JQ","meta":576},{"basename":"CodeGen","pos":"7OVOGA6QKF5OI.GFHJKKY","meta":576},{"basename":"aarch64_neon_sve_bridge_intrinsics","pos":"7OVOGA6QKF5OI.2W4QWLA","meta":576},{"basename":"acle_neon_sve_bridge_dup_neonq.c","pos":"7OVOGA6QKF5OI.XYBQYLA","meta":0}],"file":"// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py\n// REQUIRES: aarch64-registered-target\n// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s\n// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK\n// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -o /dev/null %s\n// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s\n// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +neon -target-feature +sve -target-feature +bf16 -fallow-half-arguments-and-returns -S -O1 -Werror -Wall -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefix=CPP-CHECK\n#include \n\n#ifdef SVE_OVERLOADED_FORMS\n// A simple used,unused... macro, long enough to represent any SVE builtin.\n#define SVE_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED) A1##A3\n#else\n#define SVE_ACLE_FUNC(A1, A2, A3, A4) A1##A2##A3##A4\n#endif\n\n// CHECK-LABEL: @test_svdup_neonq_s8(\n// CHECK-NEXT: entry:\n// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv16i8.v16i8( undef, <16 x i8> [[N:%.*]], i64 0)\n// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.dupq.lane.nxv16i8( [[TMP0]], i64 0)\n// CHECK-NEXT: ret [[TMP1]]\n//\n// CPP-CHECK-LABEL: @_Z19test_svdup_neonq_s811__Int8x16_t(\n// CPP-CHECK-NEXT: entry:\n// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv16i8.v16i8( undef, <16 x i8> [[N:%.*]], i64 0)\n// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.dupq.lane.nxv16i8( [[TMP0]], i64 0)\n// CPP-CHECK-NEXT: ret [[TMP1]]\n//\nsvint8_t test_svdup_neonq_s8(int8x16_t n) {\n return SVE_ACLE_FUNC(svdup_neonq, _s8, , )(n);\n}\n\n// CHECK-LABEL: @test_svdup_neonq_s16(\n// CHECK-NEXT: entry:\n// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv8i16.v8i16( undef, <8 x i16> [[N:%.*]], i64 0)\n// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.dupq.lane.nxv8i16( [[TMP0]], i64 0)\n// CHECK-NEXT: ret [[TMP1]]\n//\n// CPP-CHECK-LABEL: @_Z20test_svdup_neonq_s1611__Int16x8_t(\n// CPP-CHECK-NEXT: entry:\n// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv8i16.v8i16( undef, <8 x i16> [[N:%.*]], i64 0)\n// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.dupq.lane.nxv8i16( [[TMP0]], i64 0)\n// CPP-CHECK-NEXT: ret [[TMP1]]\n//\nsvint16_t test_svdup_neonq_s16(int16x8_t n) {\n return SVE_ACLE_FUNC(svdup_neonq, _s16, , )(n);\n}\n\n// CHECK-LABEL: @test_svdup_neonq_s32(\n// CHECK-NEXT: entry:\n// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv4i32.v4i32( undef, <4 x i32> [[N:%.*]], i64 0)\n// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.dupq.lane.nxv4i32( [[TMP0]], i64 0)\n// CHECK-NEXT: ret [[TMP1]]\n//\n// CPP-CHECK-LABEL: @_Z20test_svdup_neonq_s3211__Int32x4_t(\n// CPP-CHECK-NEXT: entry:\n// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv4i32.v4i32( undef, <4 x i32> [[N:%.*]], i64 0)\n// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.dupq.lane.nxv4i32( [[TMP0]], i64 0)\n// CPP-CHECK-NEXT: ret [[TMP1]]\n//\nsvint32_t test_svdup_neonq_s32(int32x4_t n) {\n return SVE_ACLE_FUNC(svdup_neonq, _s32, , )(n);\n}\n\n// CHECK-LABEL: @test_svdup_neonq_s64(\n// CHECK-NEXT: entry:\n// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv2i64.v2i64( undef, <2 x i64> [[N:%.*]], i64 0)\n// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.dupq.lane.nxv2i64( [[TMP0]], i64 0)\n// CHECK-NEXT: ret [[TMP1]]\n//\n// CPP-CHECK-LABEL: @_Z20test_svdup_neonq_s6411__Int64x2_t(\n// CPP-CHECK-NEXT: entry:\n// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv2i64.v2i64( undef, <2 x i64> [[N:%.*]], i64 0)\n// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.dupq.lane.nxv2i64( [[TMP0]], i64 0)\n// CPP-CHECK-NEXT: ret [[TMP1]]\n//\nsvint64_t test_svdup_neonq_s64(int64x2_t n) {\n return SVE_ACLE_FUNC(svdup_neonq, _s64, , )(n);\n}\n\n// CHECK-LABEL: @test_svdup_neonq_u8(\n// CHECK-NEXT: entry:\n// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv16i8.v16i8( undef, <16 x i8> [[N:%.*]], i64 0)\n// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.dupq.lane.nxv16i8( [[TMP0]], i64 0)\n// CHECK-NEXT: ret [[TMP1]]\n//\n// CPP-CHECK-LABEL: @_Z19test_svdup_neonq_u812__Uint8x16_t(\n// CPP-CHECK-NEXT: entry:\n// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv16i8.v16i8( undef, <16 x i8> [[N:%.*]], i64 0)\n// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.dupq.lane.nxv16i8( [[TMP0]], i64 0)\n// CPP-CHECK-NEXT: ret [[TMP1]]\n//\nsvuint8_t test_svdup_neonq_u8(uint8x16_t n) {\n return SVE_ACLE_FUNC(svdup_neonq, _u8, , )(n);\n}\n\n// CHECK-LABEL: @test_svdup_neonq_u16(\n// CHECK-NEXT: entry:\n// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv8i16.v8i16( undef, <8 x i16> [[N:%.*]], i64 0)\n// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.dupq.lane.nxv8i16( [[TMP0]], i64 0)\n// CHECK-NEXT: ret [[TMP1]]\n//\n// CPP-CHECK-LABEL: @_Z20test_svdup_neonq_u1612__Uint16x8_t(\n// CPP-CHECK-NEXT: entry:\n// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv8i16.v8i16( undef, <8 x i16> [[N:%.*]], i64 0)\n// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.dupq.lane.nxv8i16( [[TMP0]], i64 0)\n// CPP-CHECK-NEXT: ret [[TMP1]]\n//\nsvuint16_t test_svdup_neonq_u16(uint16x8_t n) {\n return SVE_ACLE_FUNC(svdup_neonq, _u16, , )(n);\n}\n\n// CHECK-LABEL: @test_svdup_neonq_u32(\n// CHECK-NEXT: entry:\n// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv4i32.v4i32( undef, <4 x i32> [[N:%.*]], i64 0)\n// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.dupq.lane.nxv4i32( [[TMP0]], i64 0)\n// CHECK-NEXT: ret [[TMP1]]\n//\n// CPP-CHECK-LABEL: @_Z20test_svdup_neonq_u3212__Uint32x4_t(\n// CPP-CHECK-NEXT: entry:\n// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv4i32.v4i32( undef, <4 x i32> [[N:%.*]], i64 0)\n// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.dupq.lane.nxv4i32( [[TMP0]], i64 0)\n// CPP-CHECK-NEXT: ret [[TMP1]]\n//\nsvuint32_t test_svdup_neonq_u32(uint32x4_t n) {\n return SVE_ACLE_FUNC(svdup_neonq, _u32, , )(n);\n}\n\n// CHECK-LABEL: @test_svdup_neonq_u64(\n// CHECK-NEXT: entry:\n// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv2i64.v2i64( undef, <2 x i64> [[N:%.*]], i64 0)\n// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.dupq.lane.nxv2i64( [[TMP0]], i64 0)\n// CHECK-NEXT: ret [[TMP1]]\n//\n// CPP-CHECK-LABEL: @_Z20test_svdup_neonq_u6412__Uint64x2_t(\n// CPP-CHECK-NEXT: entry:\n// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv2i64.v2i64( undef, <2 x i64> [[N:%.*]], i64 0)\n// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.dupq.lane.nxv2i64( [[TMP0]], i64 0)\n// CPP-CHECK-NEXT: ret [[TMP1]]\n//\nsvuint64_t test_svdup_neonq_u64(uint64x2_t n) {\n return SVE_ACLE_FUNC(svdup_neonq, _u64, , )(n);\n}\n\n// CHECK-LABEL: @test_svdup_neonq_f16(\n// CHECK-NEXT: entry:\n// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv8f16.v8f16( undef, <8 x half> [[N:%.*]], i64 0)\n// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.dupq.lane.nxv8f16( [[TMP0]], i64 0)\n// CHECK-NEXT: ret [[TMP1]]\n//\n// CPP-CHECK-LABEL: @_Z20test_svdup_neonq_f1613__Float16x8_t(\n// CPP-CHECK-NEXT: entry:\n// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv8f16.v8f16( undef, <8 x half> [[N:%.*]], i64 0)\n// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.dupq.lane.nxv8f16( [[TMP0]], i64 0)\n// CPP-CHECK-NEXT: ret [[TMP1]]\n//\nsvfloat16_t test_svdup_neonq_f16(float16x8_t n) {\n return SVE_ACLE_FUNC(svdup_neonq, _f16, , )(n);\n}\n\n// CHECK-NEXT %0 = call @llvm.vector.insert.nxv4f32.v4f32( undef, <4 x float> %n, i64 0)\n// CHECK-NEXT %1 = call @llvm.aarch64.sve.dupq.lane.nxv4f32( %0, i64 0)\n// CHECK-NEXT ret %1\n// CHECK-LABEL: @test_svdup_neonq_f32(\n// CHECK-NEXT: entry:\n// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv4f32.v4f32( undef, <4 x float> [[N:%.*]], i64 0)\n// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.dupq.lane.nxv4f32( [[TMP0]], i64 0)\n// CHECK-NEXT: ret [[TMP1]]\n//\n// CPP-CHECK-LABEL: @_Z20test_svdup_neonq_f3213__Float32x4_t(\n// CPP-CHECK-NEXT: entry:\n// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv4f32.v4f32( undef, <4 x float> [[N:%.*]], i64 0)\n// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.dupq.lane.nxv4f32( [[TMP0]], i64 0)\n// CPP-CHECK-NEXT: ret [[TMP1]]\n//\nsvfloat32_t test_svdup_neonq_f32(float32x4_t n) {\n return SVE_ACLE_FUNC(svdup_neonq, _f32, , )(n);\n}\n\n// CHECK-LABEL: @test_svdup_neonq_f64(\n// CHECK-NEXT: entry:\n// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv2f64.v2f64( undef, <2 x double> [[N:%.*]], i64 0)\n// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.dupq.lane.nxv2f64( [[TMP0]], i64 0)\n// CHECK-NEXT: ret [[TMP1]]\n//\n// CPP-CHECK-LABEL: @_Z20test_svdup_neonq_f6413__Float64x2_t(\n// CPP-CHECK-NEXT: entry:\n// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv2f64.v2f64( undef, <2 x double> [[N:%.*]], i64 0)\n// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.dupq.lane.nxv2f64( [[TMP0]], i64 0)\n// CPP-CHECK-NEXT: ret [[TMP1]]\n//\nsvfloat64_t test_svdup_neonq_f64(float64x2_t n) {\n return SVE_ACLE_FUNC(svdup_neonq, _f64, , )(n);\n}\n\n// CHECK-LABEL: @test_svdup_neonq_bf16(\n// CHECK-NEXT: entry:\n// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv8bf16.v8bf16( undef, <8 x bfloat> [[N:%.*]], i64 0)\n// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.dupq.lane.nxv8bf16( [[TMP0]], i64 0)\n// CHECK-NEXT: ret [[TMP1]]\n//\n// CPP-CHECK-LABEL: @_Z21test_svdup_neonq_bf1614__Bfloat16x8_t(\n// CPP-CHECK-NEXT: entry:\n// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.insert.nxv8bf16.v8bf16( undef, <8 x bfloat> [[N:%.*]], i64 0)\n// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.dupq.lane.nxv8bf16( [[TMP0]], i64 0)\n// CPP-CHECK-NEXT: ret [[TMP1]]\n//\nsvbfloat16_t test_svdup_neonq_bf16(bfloat16x8_t n) {\n return SVE_ACLE_FUNC(svdup_neonq, _bf16, , )(n);\n}\n"}},"token":"u5DLdBQd2t64BJGFt56xj9+g7eiJe0VRakgxf2GqFDw=","login":null}