/*
** 2008 May 27
**
** The author disclaims copyright to this source code. In place of
** a legal notice, here is a blessing:
**
** May you do good and not evil.
** May you find forgiveness for yourself and forgive others.
** May you share freely, never taking more than you give.
**
******************************************************************************
**
** This file contains inline asm code for retrieving "high-performance"
** counters for x86 and x86_64 class CPUs.
*/
/*
** The following routine only works on Pentium-class (or newer) processors.
** It uses the RDTSC opcode to read the cycle count value out of the
** processor and returns that value. This can be used for high-res
** profiling.
*/
__inline__ sqlite_uint64
__declspec __inline sqlite_uint64 __cdecl
__inline__ sqlite_uint64
__inline__ sqlite_uint64
/*
** asm() is needed for hardware timing support. Without asm(),
** disable the sqlite3Hwtime() routine.
**
** sqlite3Hwtime() is only used for some obscure debugging
** and analysis configurations, not in any deliverable, so this
** should not be a great loss.
*/
sqlite_uint64
/* !defined(SQLITE_HWTIME_H) */