name = "barrel"
# SPDX-FileCopyrightText: 2024 Isaac Nudelman
# SPDX-License-Identifier: CERN-OHL-S-2.0

entity main() -> int<8> {
    0
}
// SPDX-FileCopyrightText: 2024 Isaac Nudelman
// SPDX-License-Identifier: CERN-OHL-S-2.0

[spade]
commit = "bb73fde37183c31065170ef5c576bc9b182384d9"

// SPDX-License-Identifier: CERN-OHL-S-2.0
// A basic SOC with the core, ram, and uart
// Default 16KB ram
`default_nettype none
`timescale 1ps/1ps
module soc 
#(
    parameter integer MEM_WORDS = 4096
)
(
    input   bit clk,
    input   bit rst,
    input   bit uart_rx,
    output  bit uart_tx
);
    // TODO: impl uart
    assign uart_tx = 0 & uart_rx & rst;
    // Memory
    struct {
        bit [3:0] wen;
        bit [31:0] addr;
        bit [31:0] rdata;
        bit [31:0] wdata;
    } mem;
    logic [31:0] memory [0:MEM_WORDS-1];
    always_ff @(posedge clk) begin
        mem.rdata <= memory[mem.addr];
        if (mem.wen[0]) memory[mem.addr][ 7: 0] <= mem.wdata[ 7: 0];
		if (mem.wen[1]) memory[mem.addr][15: 8] <= mem.wdata[15: 8];
		if (mem.wen[2]) memory[mem.addr][23:16] <= mem.wdata[23:16];
		if (mem.wen[3]) memory[mem.addr][31:24] <= mem.wdata[31:24];
    end
    // End Memory
    // synthesis translate off
    logic [1000:0] mem_file;
    initial begin
        if ($test$plusargs("trace") != 0) begin
            $display("[%0t] Tracing to logs/vlt_dump.vcd...\n", $time);
            $dumpfile("logs/vlt_dump.vcd");
            $dumpvars();
        end
        if ($value$plusargs("mem", mem_file)) begin
            $display("[%0t] Initializing memory\n", $time);
            $readmemh(mem_file, memory);
        end
    end
    // synthesis translate on
endmodule

# Barrel - A (work in progress) parallel RISC-V application processor
The core targets RV32IAMS to fit on reasonably priced FPGAs while still being able to boot Linux.
A toolchain will need to be compiled from source, as the default extensions for RISC-V toolchains are GC, and the `ilp32` ABI used is not compatible with the ABI they use.
Future work may enable D & V extensions to use the DSP blocks found on most FPGAS.

# SPDX-License-Identifier: CERN-OHL-S-2.0
VERILATOR ?= verilator 
VERILATOR_COVERAGE ?= verilator_coverage 
YOSYS ?= yosys 
SMTBMC ?= yosys-smtbmc
# Keep frame pointers for debugging
CXXFLAGS += -fno-omit-frame-pointer 
# Don't use exceptions or rtti to reduce code bloat
CXXFLAGS += -fno-exceptions -fno-rtti -fno-unwind-tables -fno-asynchronous-unwind-tables
# Tune for current CPU to improve simulation performance
CXXFLAGS += -march=native -mtune=native
# Use the mold linker to massively improve linking speed
LDFLAGS += -fuse-ld=mold
# Enable multithreaded verilation
VERILATOR_FLAGS += -j $(nproc)
# Generate C++
VERILATOR_FLAGS += --cc
# Generate deps
VERILATOR_FLAGS += -MMD
# Split generated files into small translation units to improve iterative compile speed
VERILATOR_FLAGS += --output-split 500
# Split generated functions to improve compilation speed
VERILATOR_FLAGS += --output-split-cfuncs 50 --output-split-ctrace 50
# Warn about lint issues
VERILATOR_FLAGS += -Wall
# Check assertions
VERILATOR_FLAGS += --assert 
# Generate coverage analysis
VERILATOR_FLAGS += --coverage 
# Generate a multithreaded simulator
# VERILATOR_FLAGS += --threads $(nproc)
VERILATOR_DEPFILES = $(wildcard obj_dir/*.d)
default: soc
soc: soc-generate-cxx soc-compile-cxx
soc-generate-cxx:
	$(VERILATOR) $(VERILATOR_FLAGS) rtl/soc.sv
soc-compile-cxx:
	$(MAKE) -j -C obj_dir -f Vsoc.mk
-include $(VERILATOR_DEPFILES)

obj_dir/