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A massively parallel application RISC-V SOC
Refactor soc and core
Created by  8Cqo1QjSCQ3F66Vh3nan9N8dv1MjQSAEz8RNwt2cTacK  on May 17, 2024
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Implemented register file and created skeleton for basic core
Created by  8Cqo1QjSCQ3F66Vh3nan9N8dv1MjQSAEz8RNwt2cTacK  on May 15, 2024
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Factored out memory interface
Created by  8Cqo1QjSCQ3F66Vh3nan9N8dv1MjQSAEz8RNwt2cTacK  on May 15, 2024
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Focus on the hardware design by dropping alternative HDLS for Verilog
Created by  8Cqo1QjSCQ3F66Vh3nan9N8dv1MjQSAEz8RNwt2cTacK  on May 14, 2024
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Add swim lockfile
Created by  8Cqo1QjSCQ3F66Vh3nan9N8dv1MjQSAEz8RNwt2cTacK  on May 10, 2024
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Add SPDX License
Created by  8Cqo1QjSCQ3F66Vh3nan9N8dv1MjQSAEz8RNwt2cTacK  on May 10, 2024
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Create spade project
Created by  8Cqo1QjSCQ3F66Vh3nan9N8dv1MjQSAEz8RNwt2cTacK  on May 10, 2024
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(no change message)
Created by   on May 10, 2024
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