input   bit uart_rx,
    output  bit uart_tx

    input   wire uart_rx,
    output  wire uart_tx

// SPDX-License-Identifier: CERN-OHL-S-2.0
// A simple dual-read, single-write register file
`default_nettype none
`timescale 1ps/1ps
module regfile
(
    input bit clk, rst,
    // Write port
    input wire          wen,
    input wire [5:0]    waddr,
    input wire [31:0]   wdata,
    // Read ports
    input wire [5:0]    raddrA,
    output wire [31:0]  rdataA,
    input wire [5:0]    raddrB,
    output wire [31:0]  rdataB
);
    // r0 is always 0, so we can not implement it
    reg [31:0] registers [0:30]; 
    always_ff @(posedge clk, rst)
        if (rst)
            for (integer i = 0; i < 32; i++) begin
                registers[i] <= 0;
            end
        else if (wen)
            registers[~waddr[4:0]] <= wdata;
    assign rdataA = registers[~raddrA[4:0]];
	assign rdataB = registers[~raddrB[4:0]];
endmodule

    logic [31:0] memory [0:MEM_WORDS-1];
    logic [3:0] wen = mem.mode;

    reg [31:0] memory [0:MEM_WORDS-1];
    reg [3:0] wen = mem.mode;

// SPDX-License-Identifier: CERN-OHL-S-2.0
// A maxmimally simple core
`default_nettype none
`timescale 1ps/1ps
module basic_rv32i
(
    mem.core mem,
`ifdef RISCV_FORMAL
    output reg        rvfi_valid,
	output reg [63:0] rvfi_order,
	output reg [31:0] rvfi_insn,
	output reg        rvfi_trap,
	output reg        rvfi_halt,
	output reg        rvfi_intr,
	output reg [ 1:0] rvfi_mode,
	output reg [ 1:0] rvfi_ixl,
	output reg [ 4:0] rvfi_rs1_addr,
	output reg [ 4:0] rvfi_rs2_addr,
	output reg [31:0] rvfi_rs1_rdata,
	output reg [31:0] rvfi_rs2_rdata,
	output reg [ 4:0] rvfi_rd_addr,
	output reg [31:0] rvfi_rd_wdata,
	output reg [31:0] rvfi_pc_rdata,
	output reg [31:0] rvfi_pc_wdata,
	output reg [31:0] rvfi_mem_addr,
	output reg [ 3:0] rvfi_mem_rmask,
	output reg [ 3:0] rvfi_mem_wmask,
	output reg [31:0] rvfi_mem_rdata,
	output reg [31:0] rvfi_mem_wdata,
	output reg [63:0] rvfi_csr_mcycle_rmask,
	output reg [63:0] rvfi_csr_mcycle_wmask,
	output reg [63:0] rvfi_csr_mcycle_rdata,
	output reg [63:0] rvfi_csr_mcycle_wdata,
	output reg [63:0] rvfi_csr_minstret_rmask,
	output reg [63:0] rvfi_csr_minstret_wmask,
	output reg [63:0] rvfi_csr_minstret_rdata,
	output reg [63:0] rvfi_csr_minstret_wdata,
`endif
    input bit clk, rst
);
endmodule