# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64 -global-isel -verify-machineinstrs -run-pass=legalizer %s -o - | FileCheck %s

...
---
name:            s8
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $w0
    ; CHECK-LABEL: name: s8
    ; CHECK: liveins: $w0
    ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 256
    ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[DEF]], [[C]]
    ; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[OR]]
    ; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[BITREVERSE]](s32)
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[CTLZ]](s32)
    ; CHECK: $w0 = COPY [[COPY]](s32)
    ; CHECK: RET_ReallyLR implicit $w0
    %val:_(s8) = G_IMPLICIT_DEF
    %cttz:_(s8) = G_CTTZ %val(s8)
    %ext:_(s32) = G_ANYEXT %cttz(s8)
    $w0 = COPY %ext(s32)
    RET_ReallyLR implicit $w0

...
---
name:            s16
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $w0
    ; CHECK-LABEL: name: s16
    ; CHECK: liveins: $w0
    ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65536
    ; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[DEF]], [[C]]
    ; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE [[OR]]
    ; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[BITREVERSE]](s32)
    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY [[CTLZ]](s32)
    ; CHECK: $w0 = COPY [[COPY]](s32)
    ; CHECK: RET_ReallyLR implicit $w0
    %val:_(s16) = G_IMPLICIT_DEF
    %cttz:_(s16) = G_CTTZ %val(s16)
    %ext:_(s32) = G_ANYEXT %cttz(s16)
    $w0 = COPY %ext(s32)
    RET_ReallyLR implicit $w0

...
---
name:            s32
alignment:       4
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $w0

    ; CHECK-LABEL: name: s32
    ; CHECK: liveins: $w0
    ; CHECK: %val:_(s32) = COPY $w0
    ; CHECK: [[BITREVERSE:%[0-9]+]]:_(s32) = G_BITREVERSE %val
    ; CHECK: [[CTLZ:%[0-9]+]]:_(s32) = G_CTLZ [[BITREVERSE]](s32)
    ; CHECK: $w0 = COPY [[CTLZ]](s32)
    ; CHECK: RET_ReallyLR implicit $w0
    %val:_(s32) = COPY $w0
    %1:_(s32) = G_CTTZ %val(s32)
    $w0 = COPY %1(s32)
    RET_ReallyLR implicit $w0

...
---
name:            s64
alignment:       4
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x0

    ; CHECK-LABEL: name: s64
    ; CHECK: liveins: $x0
    ; CHECK: %val:_(s64) = COPY $x0
    ; CHECK: [[BITREVERSE:%[0-9]+]]:_(s64) = G_BITREVERSE %val
    ; CHECK: [[CTLZ:%[0-9]+]]:_(s64) = G_CTLZ [[BITREVERSE]](s64)
    ; CHECK: $x0 = COPY [[CTLZ]](s64)
    ; CHECK: RET_ReallyLR implicit $x0
    %val:_(s64) = COPY $x0
    %1:_(s64) = G_CTTZ %val(s64)
    $x0 = COPY %1(s64)
    RET_ReallyLR implicit $x0
...
---
name:            v4s32
alignment:       4
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $q0

    ; CHECK-LABEL: name: v4s32
    ; CHECK: liveins: $q0
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: %val:_(<4 x s32>) = COPY $q0
    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
    ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<4 x s32>) = G_XOR %val, [[BUILD_VECTOR]]
    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD %val, [[BUILD_VECTOR]]
    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s32>) = G_AND [[XOR]], [[ADD]]
    ; CHECK-NEXT: [[CTPOP:%[0-9]+]]:_(<4 x s32>) = G_CTPOP [[AND]](<4 x s32>)
    ; CHECK-NEXT: $q0 = COPY [[CTPOP]](<4 x s32>)
    ; CHECK-NEXT: RET_ReallyLR implicit $q0
    %val:_(<4 x s32>) = COPY $q0
    %1:_(<4 x s32>) = G_CTTZ %val(<4 x s32>)
    $q0 = COPY %1(<4 x s32>)
    RET_ReallyLR implicit $q0
...