# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -run-pass=legalizer %s -o - | FileCheck %s --check-prefix=ALL

--- |
  define void @test_add_v16i8() {
    %ret = add <16 x i8> undef, undef
    ret void
  }

  define void @test_add_v8i16() {
    %ret = add <8 x i16> undef, undef
    ret void
  }

  define void @test_add_v4i32() {
    %ret = add <4 x i32> undef, undef
    ret void
  }

  define void @test_add_v2i64() {
    %ret = add <2 x i64> undef, undef
    ret void
  }
...
---
name:            test_add_v16i8
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; ALL-LABEL: name: test_add_v16i8
    ; ALL: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
    ; ALL: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
    ; ALL: [[ADD:%[0-9]+]]:_(<16 x s8>) = G_ADD [[DEF]], [[DEF1]]
    ; ALL: $xmm0 = COPY [[ADD]](<16 x s8>)
    ; ALL: RET 0
    %0(<16 x s8>) = IMPLICIT_DEF
    %1(<16 x s8>) = IMPLICIT_DEF
    %2(<16 x s8>) = G_ADD %0, %1
    $xmm0 = COPY %2
    RET 0

...
---
name:            test_add_v8i16
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; ALL-LABEL: name: test_add_v8i16
    ; ALL: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
    ; ALL: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
    ; ALL: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[DEF]], [[DEF1]]
    ; ALL: $xmm0 = COPY [[ADD]](<8 x s16>)
    ; ALL: RET 0
    %0(<8 x s16>) = IMPLICIT_DEF
    %1(<8 x s16>) = IMPLICIT_DEF
    %2(<8 x s16>) = G_ADD %0, %1
    $xmm0 = COPY %2
    RET 0

...
---
name:            test_add_v4i32
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; ALL-LABEL: name: test_add_v4i32
    ; ALL: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
    ; ALL: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
    ; ALL: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[DEF]], [[DEF1]]
    ; ALL: $xmm0 = COPY [[ADD]](<4 x s32>)
    ; ALL: RET 0
    %0(<4 x s32>) = IMPLICIT_DEF
    %1(<4 x s32>) = IMPLICIT_DEF
    %2(<4 x s32>) = G_ADD %0, %1
    $xmm0 = COPY %2
    RET 0

...
---
name:            test_add_v2i64
alignment:       16
legalized:       false
regBankSelected: false
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; ALL-LABEL: name: test_add_v2i64
    ; ALL: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
    ; ALL: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
    ; ALL: [[ADD:%[0-9]+]]:_(<2 x s64>) = G_ADD [[DEF]], [[DEF1]]
    ; ALL: $xmm0 = COPY [[ADD]](<2 x s64>)
    ; ALL: RET 0
    %0(<2 x s64>) = IMPLICIT_DEF
    %1(<2 x s64>) = IMPLICIT_DEF
    %2(<2 x s64>) = G_ADD %0, %1
    $xmm0 = COPY %2
    RET 0

...