// RUN: not llvm-mc -triple=thumbv8m.main -mattr=+fp-armv8 -mattr=+cdecp0 -mattr=+cdecp1 -show-encoding < %s 2>%t | FileCheck %s
// RUN: FileCheck <%t --check-prefixes=ERROR,ERROR-FP %s
// RUN: not llvm-mc -triple=thumbv8m.main -mattr=+fp-armv8d16sp -mattr=+cdecp0 -mattr=+cdecp1 -show-encoding < %s 2>%t | FileCheck %s
// RUN: FileCheck <%t --check-prefixes=ERROR,ERROR-FP %s
// RUN: not llvm-mc -triple=thumbv8.1m.main -mattr=+mve -mattr=+cdecp0 -mattr=+cdecp1 -show-encoding < %s 2>%t | FileCheck --check-prefixes=CHECK,CHECK-MVE %s
// RUN: FileCheck <%t --check-prefixes=ERROR,ERROR-MVE %s
// CHECK-LABEL: test_predication:
test_predication:
ittt eq
// ERROR: [[@LINE+1]]:{{[0-9]+}}: error: instructions in IT block must be predicable
vcx1a p1, s7, // ERROR: [[@LINE+1]]:{{[0-9]+}}: error: instructions in IT block must be predicable
vcx2 p0, d0, d15, // ERROR-FP: [[@LINE+2]]:{{[0-9]+}}: error: invalid instruction
// ERROR-MVE: [[@LINE+1]]:{{[0-9]+}}: error: instructions in IT block must be predicable
vcx3 p0, q0, q7, q0, nop
nop
nop
// CHECK-LABEL: test_vcx1:
test_vcx1:
// CHECK-NEXT: vcx1 p0, s11, vcx1 p0, s11, // CHECK-NEXT: vcx1a p1, s7, vcx1a p1, s7, // CHECK-NEXT: vcx1 p0, d0, vcx1 p0, d0, // CHECK-NEXT: vcx1a p1, d3, vcx1a p1, d3, // CHECK-MVE-NEXT: vcx1 p0, q1, // ERROR-FP: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction, any one of the following would fix this:
vcx1 p0, q1, // CHECK-MVE-NEXT: vcx1a p1, q5, // ERROR-FP: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction
vcx1a p1, q5,
// ERROR: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction
vcx1a p1, s7, s7, // ERROR: [[@LINE+1]]:{{[0-9]+}}: error: operand must be an immediate in the range [0,2047]
vcx1 p0, d0, // ERROR-FP: [[@LINE+1]]:{{[0-9]+}}: error: operand must be an immediate in the range [0,2047]
vcx1a p1, s0, // ERROR-FP: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction
vcx1 p0, q0, // ERROR-FP: [[@LINE+2]]:{{[0-9]+}}: error: coprocessor must be in the range [p0, p7]
// ERROR-MVE: [[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction
vcx1 p8, d0, // ERROR: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction
vcx1 p0, d16, // ERROR: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction
vcx1 p0, s32, // ERROR-FP: [[@LINE+4]]:{{[0-9]+}}: error: invalid instruction, any one of the following would fix this:
// ERROR-FP: [[@LINE+3]]:{{[0-9]+}}: note: operand must be a register in range [s0, s31]
// ERROR-FP: [[@LINE+2]]:{{[0-9]+}}: note: operand must be a register in range [d0, d15]
// ERROR-MVE: [[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [q0, q7]
vcx1 p0, q8, // ERROR: [[@LINE+3]]:{{[0-9]+}}: error: invalid instruction, any one of the following would fix this:
// ERROR: [[@LINE+2]]:{{[0-9]+}}: note: operand must be a register in range [s0, s31]
// ERROR: [[@LINE+1]]:{{[0-9]+}}: note: operand must be a register in range [d0, d15]
vcx1 p0, r0, // ERROR: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction
vcx1 p0, d0, d0, // ERROR: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction
vcx1a p0, d0, d2,
// CHECK-LABEL: test_vcx2:
test_vcx2:
// CHECK-NEXT: vcx2 p0, s0, s31, vcx2 p0, s0, s31, // CHECK-NEXT: vcx2a p0, s1, s1, vcx2a p0, s1, s1, // CHECK-NEXT: vcx2 p0, d0, d15, vcx2 p0, d0, d15, // CHECK-NEXT: vcx2a p0, d1, d11, vcx2a p0, d1, d11, // CHECK-MVE: vcx2 p1, q0, q6, vcx2 p1, q0, q6, // CHECK-MVE: vcx2a p1, q3, q7, vcx2a p1, q3, q7,
// ERROR: [[@LINE+1]]:{{[0-9]+}}: error: operand must be an immediate in the range [0,63]
vcx2 p0, d0, d1, // ERROR: [[@LINE+1]]:{{[0-9]+}}: error: operand must be an immediate in the range [0,63]
vcx2a p0, s3, s1, // ERROR-MVE: [[@LINE+2]]:{{[0-9]+}}: error: operand must be an immediate in the range [0,127]
// ERROR-FP: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction
vcx2a p0, q1, q5, // ERROR-FP: [[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [d0, d15]
vcx2 p1, d0, q2, // ERROR-FP: [[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [s0, s31]
vcx2a p1, q2, s3, // ERROR: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction
vcx2 p1, d0, d0, d2, // ERROR: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction
vcx2a p1, q2, q3, q1,
// CHECK-LABEL: test_vcx3:
test_vcx3:
// CHECK-NEXT: vcx3 p0, s0, s31, s0, vcx3 p0, s0, s31, s0, // CHECK-NEXT: vcx3a p1, s1, s17, s11, vcx3a p1, s1, s17, s11, // CHECK-NEXT: vcx3 p0, d0, d15, d7, vcx3 p0, d0, d15, d7, // CHECK-NEXT: vcx3a p1, d1, d11, d11, vcx3a p1, d1, d11, d11, // CHECK-MVE-NEXT: vcx3 p0, q0, q2, q0, vcx3 p0, q0, q2, q0, // CHECK-MVE-NEXT: vcx3a p1, q3, q7, q6, vcx3a p1, q3, q7, q6,
// ERROR: [[@LINE+1]]:{{[0-9]+}}: error: operand must be an immediate in the range [0,7]
vcx3a p1, d1, d11, d12, // ERROR-MVE: [[@LINE+2]]:{{[0-9]+}}: error: operand must be an immediate in the range [0,15]
// ERROR-FP: error: invalid instruction
vcx3a p1, q1, q2, q3, // ERROR-MVE: [[@LINE+2]]:{{[0-9]+}}: error: invalid instruction
// ERROR-FP: [[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [d0, d15]
vcx3 p0, d0, q0, d7, // ERROR: [[@LINE+1]]:{{[0-9]+}}: error: operand must be a register in range [s0, s31]
vcx3a p1, s0, s1, d3, // ERROR: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction
vcx3a p0, s0, d0, q0, // ERROR: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction
vcx3 p0, s0, s0, s31, s0, // ERROR: [[@LINE+1]]:{{[0-9]+}}: error: invalid instruction
vcx3a p1, d1, d3, d22, d22,