# RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1010 -run-pass=prologepilog -o - %s | FileCheck %s

# On PAL, we need to ensure SRSRC do not clobber GIT pointer, passed
# in SGPR8 for HS or GS

--- |

  define amdgpu_gs void @shader(i32 inreg %mergedGroupInfo) {
    ret void
  }
...
---
name:            shader
tracksRegLiveness: true
liveins:
  - { reg: '$sgpr0' }
machineFunctionInfo:
  isEntryFunction: true
  scratchRSrcReg:  '$sgpr100_sgpr101_sgpr102_sgpr103'
  stackPtrOffsetReg: '$sgpr32'
  argumentInfo:
    privateSegmentWaveByteOffset: { reg: '$sgpr5' }
body:             |
  ; CHECK:   $sgpr1 = COPY killed $sgpr5
  ; CHECK:   $sgpr4_sgpr5 = S_GETPC_B64
  ; CHECK:   $sgpr4 = S_MOV_B32 $sgpr8
  ; CHECK:   $sgpr4_sgpr5_sgpr6_sgpr7 = S_LOAD_DWORDX4_IMM $sgpr4_sgpr5, 0, 0, implicit-def $sgpr4_sgpr5_sgpr6_sgpr7 :: (dereferenceable invariant load (s128), align 4, addrspace 4)
  bb.0:
    successors: %bb.1, %bb.2
    liveins: $sgpr0

    $exec_lo = S_MOV_B32 -1
    renamable $vgpr0 = V_MBCNT_LO_U32_B32_e64 -1, 0, implicit $exec
    renamable $sgpr0 = S_BFE_U32 killed renamable $sgpr0, 589836, implicit-def dead $scc
    renamable $vcc_lo = V_CMP_GT_U32_e64 killed $sgpr0, killed $vgpr0, implicit $exec
    $sgpr0 = S_AND_SAVEEXEC_B32 $vcc_lo, implicit-def $exec, implicit-def $scc, implicit $exec
    S_CBRANCH_EXECZ %bb.2, implicit $exec
    S_BRANCH %bb.1

  bb.1:
    renamable $vgpr0 = V_MOV_B32_e32 1065353216, implicit $exec
    BUFFER_STORE_DWORD_OFFEN killed renamable $vgpr0, undef renamable $vgpr0, $sgpr100_sgpr101_sgpr102_sgpr103, 0, 0, 0, 0, 0, implicit $exec :: (store (s32), addrspace 5)

  bb.2:
    S_ENDPGM 0

...