; RUN: llvm-mc -triple arm64-apple-darwin -show-encoding < %s | FileCheck %s
foo:
;==---------------------------------------------------------------------------==
; 5.4.2 Logical (immediate)
;==---------------------------------------------------------------------------==
and w0, w0, and x0, x0, and w1, w2, and x1, x2, and sp, x5, ands w0, w0, ands x0, x0, ands w1, w2, ands x1, x2,
; CHECK: and w0, w0, ; CHECK: and x0, x0, ; CHECK: and w1, w2, ; CHECK: and x1, x2, ; CHECK: and sp, x5, ; CHECK: ands w0, w0, ; CHECK: ands x0, x0, ; CHECK: ands w1, w2, ; CHECK: ands x1, x2,
eor w1, w2, eor x1, x2,
; CHECK: eor w1, w2, ; CHECK: eor x1, x2,
orr w1, w2, orr x1, x2,
; CHECK: orr w1, w2, ; CHECK: orr x1, x2,
orr w8, wzr, orr x8, xzr,
; CHECK: orr w8, wzr, ; CHECK: orr x8, xzr,
;==---------------------------------------------------------------------------==
; 5.5.3 Logical (shifted register)
;==---------------------------------------------------------------------------==
and w1, w2, w3
and x1, x2, x3
and w1, w2, w3, lsl and x1, x2, x3, lsl and w1, w2, w3, lsr and x1, x2, x3, lsr and w1, w2, w3, asr and x1, x2, x3, asr and w1, w2, w3, ror and x1, x2, x3, ror
; CHECK: and w1, w2, w3 ; encoding: [0x41,0x00,0x03,0x0a]
; CHECK: and x1, x2, x3 ; encoding: [0x41,0x00,0x03,0x8a]
; CHECK: and w1, w2, w3, lsl ; CHECK: and x1, x2, x3, lsl ; CHECK: and w1, w2, w3, lsr ; CHECK: and x1, x2, x3, lsr ; CHECK: and w1, w2, w3, asr ; CHECK: and x1, x2, x3, asr ; CHECK: and w1, w2, w3, ror ; CHECK: and x1, x2, x3, ror
ands w1, w2, w3
ands x1, x2, x3
ands w1, w2, w3, lsl ands x1, x2, x3, lsl ands w1, w2, w3, lsr ands x1, x2, x3, lsr ands w1, w2, w3, asr ands x1, x2, x3, asr ands w1, w2, w3, ror ands x1, x2, x3, ror
; CHECK: ands w1, w2, w3 ; encoding: [0x41,0x00,0x03,0x6a]
; CHECK: ands x1, x2, x3 ; encoding: [0x41,0x00,0x03,0xea]
; CHECK: ands w1, w2, w3, lsl ; CHECK: ands x1, x2, x3, lsl ; CHECK: ands w1, w2, w3, lsr ; CHECK: ands x1, x2, x3, lsr ; CHECK: ands w1, w2, w3, asr ; CHECK: ands x1, x2, x3, asr ; CHECK: ands w1, w2, w3, ror ; CHECK: ands x1, x2, x3, ror
bic w1, w2, w3
bic x1, x2, x3
bic w1, w2, w3, lsl bic x1, x2, x3, lsl bic w1, w2, w3, lsr bic x1, x2, x3, lsr bic w1, w2, w3, asr bic x1, x2, x3, asr bic w1, w2, w3, ror bic x1, x2, x3, ror
; CHECK: bic w1, w2, w3 ; encoding: [0x41,0x00,0x23,0x0a]
; CHECK: bic x1, x2, x3 ; encoding: [0x41,0x00,0x23,0x8a]
; CHECK: bic w1, w2, w3, lsl ; CHECK: bic x1, x2, x3, lsl ; CHECK: bic w1, w2, w3, lsr ; CHECK: bic x1, x2, x3, lsr ; CHECK: bic w1, w2, w3, asr ; CHECK: bic x1, x2, x3, asr ; CHECK: bic w1, w2, w3, ror ; CHECK: bic x1, x2, x3, ror
bics w1, w2, w3
bics x1, x2, x3
bics w1, w2, w3, lsl bics x1, x2, x3, lsl bics w1, w2, w3, lsr bics x1, x2, x3, lsr bics w1, w2, w3, asr bics x1, x2, x3, asr bics w1, w2, w3, ror bics x1, x2, x3, ror
; CHECK: bics w1, w2, w3 ; encoding: [0x41,0x00,0x23,0x6a]
; CHECK: bics x1, x2, x3 ; encoding: [0x41,0x00,0x23,0xea]
; CHECK: bics w1, w2, w3, lsl ; CHECK: bics x1, x2, x3, lsl ; CHECK: bics w1, w2, w3, lsr ; CHECK: bics x1, x2, x3, lsr ; CHECK: bics w1, w2, w3, asr ; CHECK: bics x1, x2, x3, asr ; CHECK: bics w1, w2, w3, ror ; CHECK: bics x1, x2, x3, ror
eon w1, w2, w3
eon x1, x2, x3
eon w1, w2, w3, lsl eon x1, x2, x3, lsl eon w1, w2, w3, lsr eon x1, x2, x3, lsr eon w1, w2, w3, asr eon x1, x2, x3, asr eon w1, w2, w3, ror eon x1, x2, x3, ror
; CHECK: eon w1, w2, w3 ; encoding: [0x41,0x00,0x23,0x4a]
; CHECK: eon x1, x2, x3 ; encoding: [0x41,0x00,0x23,0xca]
; CHECK: eon w1, w2, w3, lsl ; CHECK: eon x1, x2, x3, lsl ; CHECK: eon w1, w2, w3, lsr ; CHECK: eon x1, x2, x3, lsr ; CHECK: eon w1, w2, w3, asr ; CHECK: eon x1, x2, x3, asr ; CHECK: eon w1, w2, w3, ror ; CHECK: eon x1, x2, x3, ror
eor w1, w2, w3
eor x1, x2, x3
eor w1, w2, w3, lsl eor x1, x2, x3, lsl eor w1, w2, w3, lsr eor x1, x2, x3, lsr eor w1, w2, w3, asr eor x1, x2, x3, asr eor w1, w2, w3, ror eor x1, x2, x3, ror
; CHECK: eor w1, w2, w3 ; encoding: [0x41,0x00,0x03,0x4a]
; CHECK: eor x1, x2, x3 ; encoding: [0x41,0x00,0x03,0xca]
; CHECK: eor w1, w2, w3, lsl ; CHECK: eor x1, x2, x3, lsl ; CHECK: eor w1, w2, w3, lsr ; CHECK: eor x1, x2, x3, lsr ; CHECK: eor w1, w2, w3, asr ; CHECK: eor x1, x2, x3, asr ; CHECK: eor w1, w2, w3, ror ; CHECK: eor x1, x2, x3, ror
orr w1, w2, w3
orr x1, x2, x3
orr w1, w2, w3, lsl orr x1, x2, x3, lsl orr w1, w2, w3, lsr orr x1, x2, x3, lsr orr w1, w2, w3, asr orr x1, x2, x3, asr orr w1, w2, w3, ror orr x1, x2, x3, ror
; CHECK: orr w1, w2, w3 ; encoding: [0x41,0x00,0x03,0x2a]
; CHECK: orr x1, x2, x3 ; encoding: [0x41,0x00,0x03,0xaa]
; CHECK: orr w1, w2, w3, lsl ; CHECK: orr x1, x2, x3, lsl ; CHECK: orr w1, w2, w3, lsr ; CHECK: orr x1, x2, x3, lsr ; CHECK: orr w1, w2, w3, asr ; CHECK: orr x1, x2, x3, asr ; CHECK: orr w1, w2, w3, ror ; CHECK: orr x1, x2, x3, ror
orn w1, w2, w3
orn x1, x2, x3
orn w1, w2, w3, lsl orn x1, x2, x3, lsl orn w1, w2, w3, lsr orn x1, x2, x3, lsr orn w1, w2, w3, asr orn x1, x2, x3, asr orn w1, w2, w3, ror orn x1, x2, x3, ror
; CHECK: orn w1, w2, w3 ; encoding: [0x41,0x00,0x23,0x2a]
; CHECK: orn x1, x2, x3 ; encoding: [0x41,0x00,0x23,0xaa]
; CHECK: orn w1, w2, w3, lsl ; CHECK: orn x1, x2, x3, lsl ; CHECK: orn w1, w2, w3, lsr ; CHECK: orn x1, x2, x3, lsr ; CHECK: orn w1, w2, w3, asr ; CHECK: orn x1, x2, x3, asr ; CHECK: orn w1, w2, w3, ror ; CHECK: orn x1, x2, x3, ror
;; Allow all-1 in top bits.
and w0, w0, and w1, w1,
; CHECK: and w0, w0, ; CHECK: and w1, w1,