; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=thumbv7-apple-darwin -arm-atomic-cfg-tidy=0 -mcpu=cortex-a8 -relocation-model=pic -frame-pointer=all | FileCheck %s
; rdar://7352504

%0 = type { i16, i8, i8 }
%1 = type { [2 x i32], [2 x i32] }
%2 = type { %union.rec* }
%struct.FILE_POS = type { i8, i8, i16, i32 }
%struct.GAP = type { i8, i8, i16 }
%struct.LIST = type { %union.rec*, %union.rec* }
%struct.STYLE = type { %union.anon, %union.anon, i16, i16, i32 }
%struct.head_type = type { [2 x %struct.LIST], %union.FIRST_UNION, %union.SECOND_UNION, %union.THIRD_UNION, %union.FOURTH_UNION, %union.rec*, %2, %union.rec*, %union.rec*, %union.rec*, %union.rec*, %union.rec*, %union.rec*, %union.rec*, %union.rec*, i32 }
%union.FIRST_UNION = type { %struct.FILE_POS }
%union.FOURTH_UNION = type { %struct.STYLE }
%union.SECOND_UNION = type { %0 }
%union.THIRD_UNION = type { %1 }
%union.anon = type { %struct.GAP }
%union.rec = type { %struct.head_type }

@zz_hold = external global %union.rec*            ; <%union.rec**> [#uses=2]
@zz_res = external global %union.rec*             ; <%union.rec**> [#uses=1]

define %union.rec* @Manifest(%union.rec* %x, %union.rec* %env, %struct.STYLE* %style, %union.rec** %bthr, %union.rec** %fthr, %union.rec** %target, %union.rec** %crs, i32 %ok, i32 %need_expand, %union.rec** %enclose, i32 %fcr) nounwind {
; CHECK-LABEL: Manifest:
; CHECK:       @ %bb.0: @ %entry
; CHECK-NEXT:    push {r4, r5, r6, r7, lr}
; CHECK-NEXT:    add r7, sp, #12
; CHECK-NEXT:    push.w {r8, r10, r11}
; CHECK-NEXT:    sub sp, #292
; CHECK-NEXT:    add.w r10, r7, #8
; CHECK-NEXT:    ldrd r8, lr, [r7, #20]
; CHECK-NEXT:    movs r5, #0
; CHECK-NEXT:    cmp r5, #0
; CHECK-NEXT:    ldm.w r10, {r4, r9, r10}
; CHECK-NEXT:    ldr.w r12, [r7, #28]
; CHECK-NEXT:    ittt ne
; CHECK-NEXT:    addne sp, #292
; CHECK-NEXT:    popne.w {r8, r10, r11}
; CHECK-NEXT:    popne {r4, r5, r6, r7, pc}
; CHECK-NEXT:  LBB0_1: @ %bb20
; CHECK-NEXT:    cmp.w r0, #450
; CHECK-NEXT:    bge LBB0_4
; CHECK-NEXT:  @ %bb.2: @ %bb20
; CHECK-NEXT:    cmp r0, #209
; CHECK-NEXT:    ble LBB0_5
; CHECK-NEXT:  @ %bb.3: @ %bb420
; CHECK-NEXT:    movw r5, :lower16:(L_zz_hold$non_lazy_ptr-(LPC0_0+4))
; CHECK-NEXT:    movt r5, :upper16:(L_zz_hold$non_lazy_ptr-(LPC0_0+4))
; CHECK-NEXT:    movw r11, :lower16:(L_zz_res$non_lazy_ptr-(LPC0_1+4))
; CHECK-NEXT:  LPC0_0:
; CHECK-NEXT:    add r5, pc
; CHECK-NEXT:    movt r11, :upper16:(L_zz_res$non_lazy_ptr-(LPC0_1+4))
; CHECK-NEXT:  LPC0_1:
; CHECK-NEXT:    add r11, pc
; CHECK-NEXT:    ldr r5, [r5]
; CHECK-NEXT:    str r5, [sp, #32] @ 4-byte Spill
; CHECK-NEXT:    ldr.w r5, [r11]
; CHECK-NEXT:    mov.w r11, #0
; CHECK-NEXT:    str r5, [sp, #28] @ 4-byte Spill
; CHECK-NEXT:    ldr r5, [sp, #32] @ 4-byte Reload
; CHECK-NEXT:    str.w r11, [r5]
; CHECK-NEXT:    movs r5, #0
; CHECK-NEXT:    ldr r6, [sp, #28] @ 4-byte Reload
; CHECK-NEXT:    str r5, [r6]
; CHECK-NEXT:    ldr r5, [sp, #32] @ 4-byte Reload
; CHECK-NEXT:    str r0, [r5]
; CHECK-NEXT:    ldr r0, [r7, #32]
; CHECK-NEXT:    stm.w sp, {r4, r9, r10}
; CHECK-NEXT:    strd r8, lr, [sp, #12]
; CHECK-NEXT:    str.w r12, [sp, #20]
; CHECK-NEXT:    str r0, [sp, #24]
; CHECK-NEXT:    bl _Manifest
; CHECK-NEXT:    trap
; CHECK-NEXT:  LBB0_4: @ %bb20
; CHECK-NEXT:    cmp.w r0, #560
; CHECK-NEXT:    itt ge
; CHECK-NEXT:    movge r0, #0
; CHECK-NEXT:    cmpge r0, #0
; CHECK-NEXT:  LBB0_5: @ %bb20
; CHECK-NEXT:    trap
entry:
  %xgaps.i = alloca [32 x %union.rec*], align 4   ; <[32 x %union.rec*]*> [#uses=0]
  %ycomp.i = alloca [32 x %union.rec*], align 4   ; <[32 x %union.rec*]*> [#uses=0]
  br label %bb20

bb20:                                             ; preds = %entry
  switch i32 undef, label %bb1287 [
    i32 110, label %bb119
    i32 120, label %bb119
    i32 210, label %bb420
    i32 230, label %bb420
    i32 450, label %bb438
    i32 460, label %bb438
    i32 550, label %bb533
    i32 560, label %bb569
    i32 640, label %bb745
    i32 780, label %bb1098
  ]

bb119:                                            ; preds = %bb20, %bb20
  unreachable

bb420:                                            ; preds = %bb20, %bb20
  store volatile %union.rec* null, %union.rec** @zz_hold, align 4
  store %union.rec* null, %union.rec** @zz_res, align 4
  store volatile %union.rec* %x, %union.rec** @zz_hold, align 4
  %0 = call  %union.rec* @Manifest(%union.rec* undef, %union.rec* %env, %struct.STYLE* %style, %union.rec** %bthr, %union.rec** %fthr, %union.rec** %target, %union.rec** %crs, i32 %ok, i32 %need_expand, %union.rec** %enclose, i32 %fcr) nounwind ; <%union.rec*> [#uses=0]
  unreachable

bb438:                                            ; preds = %bb20, %bb20
  unreachable

bb533:                                            ; preds = %bb20
  ret %union.rec* %x

bb569:                                            ; preds = %bb20
  unreachable

bb745:                                            ; preds = %bb20
  unreachable

bb1098:                                           ; preds = %bb20
  unreachable

bb1287:                                           ; preds = %bb20
  unreachable
}