# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=mipsel-linux-gnu -mcpu=mips32r5 -mattr=+msa,+fp64,+nan2008 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=P5600
--- |
declare <16 x i8> @llvm.mips.div.s.b(<16 x i8>, <16 x i8>)
define void @sdiv_v16i8_builtin(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
declare <8 x i16> @llvm.mips.div.s.h(<8 x i16>, <8 x i16>)
define void @sdiv_v8i16_builtin(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
declare <4 x i32> @llvm.mips.div.s.w(<4 x i32>, <4 x i32>)
define void @sdiv_v4i32_builtin(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
declare <2 x i64> @llvm.mips.div.s.d(<2 x i64>, <2 x i64>)
define void @sdiv_v2i64_builtin(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
declare <16 x i8> @llvm.mips.mod.s.b(<16 x i8>, <16 x i8>)
define void @smod_v16i8_builtin(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
declare <8 x i16> @llvm.mips.mod.s.h(<8 x i16>, <8 x i16>)
define void @smod_v8i16_builtin(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
declare <4 x i32> @llvm.mips.mod.s.w(<4 x i32>, <4 x i32>)
define void @smod_v4i32_builtin(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
declare <2 x i64> @llvm.mips.mod.s.d(<2 x i64>, <2 x i64>)
define void @smod_v2i64_builtin(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
declare <16 x i8> @llvm.mips.div.u.b(<16 x i8>, <16 x i8>)
define void @udiv_v16i8_builtin(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
declare <8 x i16> @llvm.mips.div.u.h(<8 x i16>, <8 x i16>)
define void @udiv_v8i16_builtin(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
declare <4 x i32> @llvm.mips.div.u.w(<4 x i32>, <4 x i32>)
define void @udiv_v4i32_builtin(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
declare <2 x i64> @llvm.mips.div.u.d(<2 x i64>, <2 x i64>)
define void @udiv_v2i64_builtin(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
declare <16 x i8> @llvm.mips.mod.u.b(<16 x i8>, <16 x i8>)
define void @umod_v16i8_builtin(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) { entry: ret void }
declare <8 x i16> @llvm.mips.mod.u.h(<8 x i16>, <8 x i16>)
define void @umod_v8i16_builtin(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) { entry: ret void }
declare <4 x i32> @llvm.mips.mod.u.w(<4 x i32>, <4 x i32>)
define void @umod_v4i32_builtin(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) { entry: ret void }
declare <2 x i64> @llvm.mips.mod.u.d(<2 x i64>, <2 x i64>)
define void @umod_v2i64_builtin(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) { entry: ret void }
...
---
name: sdiv_v16i8_builtin
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; P5600-LABEL: name: sdiv_v16i8_builtin
; P5600: liveins: $a0, $a1, $a2
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load (<16 x s8>) from %ir.b)
; P5600: [[SDIV:%[0-9]+]]:_(<16 x s8>) = G_SDIV [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[SDIV]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)
; P5600: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
%2:_(p0) = COPY $a2
%3:_(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
%4:_(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
%5:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.mips.div.s.b), %3(<16 x s8>), %4(<16 x s8>)
G_STORE %5(<16 x s8>), %2(p0) :: (store (<16 x s8>) into %ir.c)
RetRA
...
---
name: sdiv_v8i16_builtin
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; P5600-LABEL: name: sdiv_v8i16_builtin
; P5600: liveins: $a0, $a1, $a2
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load (<8 x s16>) from %ir.b)
; P5600: [[SDIV:%[0-9]+]]:_(<8 x s16>) = G_SDIV [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[SDIV]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)
; P5600: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
%2:_(p0) = COPY $a2
%3:_(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
%4:_(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
%5:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.mips.div.s.h), %3(<8 x s16>), %4(<8 x s16>)
G_STORE %5(<8 x s16>), %2(p0) :: (store (<8 x s16>) into %ir.c)
RetRA
...
---
name: sdiv_v4i32_builtin
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; P5600-LABEL: name: sdiv_v4i32_builtin
; P5600: liveins: $a0, $a1, $a2
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
; P5600: [[SDIV:%[0-9]+]]:_(<4 x s32>) = G_SDIV [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[SDIV]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
%2:_(p0) = COPY $a2
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.div.s.w), %3(<4 x s32>), %4(<4 x s32>)
G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
RetRA
...
---
name: sdiv_v2i64_builtin
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; P5600-LABEL: name: sdiv_v2i64_builtin
; P5600: liveins: $a0, $a1, $a2
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
; P5600: [[SDIV:%[0-9]+]]:_(<2 x s64>) = G_SDIV [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[SDIV]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
%2:_(p0) = COPY $a2
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.mips.div.s.d), %3(<2 x s64>), %4(<2 x s64>)
G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)
RetRA
...
---
name: smod_v16i8_builtin
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; P5600-LABEL: name: smod_v16i8_builtin
; P5600: liveins: $a0, $a1, $a2
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load (<16 x s8>) from %ir.b)
; P5600: [[SREM:%[0-9]+]]:_(<16 x s8>) = G_SREM [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[SREM]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)
; P5600: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
%2:_(p0) = COPY $a2
%3:_(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
%4:_(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
%5:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.mips.mod.s.b), %3(<16 x s8>), %4(<16 x s8>)
G_STORE %5(<16 x s8>), %2(p0) :: (store (<16 x s8>) into %ir.c)
RetRA
...
---
name: smod_v8i16_builtin
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; P5600-LABEL: name: smod_v8i16_builtin
; P5600: liveins: $a0, $a1, $a2
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load (<8 x s16>) from %ir.b)
; P5600: [[SREM:%[0-9]+]]:_(<8 x s16>) = G_SREM [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[SREM]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)
; P5600: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
%2:_(p0) = COPY $a2
%3:_(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
%4:_(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
%5:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.mips.mod.s.h), %3(<8 x s16>), %4(<8 x s16>)
G_STORE %5(<8 x s16>), %2(p0) :: (store (<8 x s16>) into %ir.c)
RetRA
...
---
name: smod_v4i32_builtin
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; P5600-LABEL: name: smod_v4i32_builtin
; P5600: liveins: $a0, $a1, $a2
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
; P5600: [[SREM:%[0-9]+]]:_(<4 x s32>) = G_SREM [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[SREM]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
%2:_(p0) = COPY $a2
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.mod.s.w), %3(<4 x s32>), %4(<4 x s32>)
G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
RetRA
...
---
name: smod_v2i64_builtin
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; P5600-LABEL: name: smod_v2i64_builtin
; P5600: liveins: $a0, $a1, $a2
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
; P5600: [[SREM:%[0-9]+]]:_(<2 x s64>) = G_SREM [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[SREM]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
%2:_(p0) = COPY $a2
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.mips.mod.s.d), %3(<2 x s64>), %4(<2 x s64>)
G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)
RetRA
...
---
name: udiv_v16i8_builtin
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; P5600-LABEL: name: udiv_v16i8_builtin
; P5600: liveins: $a0, $a1, $a2
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load (<16 x s8>) from %ir.b)
; P5600: [[UDIV:%[0-9]+]]:_(<16 x s8>) = G_UDIV [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[UDIV]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)
; P5600: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
%2:_(p0) = COPY $a2
%3:_(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
%4:_(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
%5:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.mips.div.u.b), %3(<16 x s8>), %4(<16 x s8>)
G_STORE %5(<16 x s8>), %2(p0) :: (store (<16 x s8>) into %ir.c)
RetRA
...
---
name: udiv_v8i16_builtin
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; P5600-LABEL: name: udiv_v8i16_builtin
; P5600: liveins: $a0, $a1, $a2
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load (<8 x s16>) from %ir.b)
; P5600: [[UDIV:%[0-9]+]]:_(<8 x s16>) = G_UDIV [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[UDIV]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)
; P5600: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
%2:_(p0) = COPY $a2
%3:_(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
%4:_(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
%5:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.mips.div.u.h), %3(<8 x s16>), %4(<8 x s16>)
G_STORE %5(<8 x s16>), %2(p0) :: (store (<8 x s16>) into %ir.c)
RetRA
...
---
name: udiv_v4i32_builtin
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; P5600-LABEL: name: udiv_v4i32_builtin
; P5600: liveins: $a0, $a1, $a2
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
; P5600: [[UDIV:%[0-9]+]]:_(<4 x s32>) = G_UDIV [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[UDIV]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
%2:_(p0) = COPY $a2
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.div.u.w), %3(<4 x s32>), %4(<4 x s32>)
G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
RetRA
...
---
name: udiv_v2i64_builtin
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; P5600-LABEL: name: udiv_v2i64_builtin
; P5600: liveins: $a0, $a1, $a2
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
; P5600: [[UDIV:%[0-9]+]]:_(<2 x s64>) = G_UDIV [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[UDIV]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
%2:_(p0) = COPY $a2
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.mips.div.u.d), %3(<2 x s64>), %4(<2 x s64>)
G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)
RetRA
...
---
name: umod_v16i8_builtin
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; P5600-LABEL: name: umod_v16i8_builtin
; P5600: liveins: $a0, $a1, $a2
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
; P5600: [[LOAD:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY]](p0) :: (load (<16 x s8>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<16 x s8>) = G_LOAD [[COPY1]](p0) :: (load (<16 x s8>) from %ir.b)
; P5600: [[UREM:%[0-9]+]]:_(<16 x s8>) = G_UREM [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[UREM]](<16 x s8>), [[COPY2]](p0) :: (store (<16 x s8>) into %ir.c)
; P5600: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
%2:_(p0) = COPY $a2
%3:_(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>) from %ir.a)
%4:_(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>) from %ir.b)
%5:_(<16 x s8>) = G_INTRINSIC intrinsic(@llvm.mips.mod.u.b), %3(<16 x s8>), %4(<16 x s8>)
G_STORE %5(<16 x s8>), %2(p0) :: (store (<16 x s8>) into %ir.c)
RetRA
...
---
name: umod_v8i16_builtin
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; P5600-LABEL: name: umod_v8i16_builtin
; P5600: liveins: $a0, $a1, $a2
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
; P5600: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p0) :: (load (<8 x s16>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY1]](p0) :: (load (<8 x s16>) from %ir.b)
; P5600: [[UREM:%[0-9]+]]:_(<8 x s16>) = G_UREM [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[UREM]](<8 x s16>), [[COPY2]](p0) :: (store (<8 x s16>) into %ir.c)
; P5600: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
%2:_(p0) = COPY $a2
%3:_(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>) from %ir.a)
%4:_(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>) from %ir.b)
%5:_(<8 x s16>) = G_INTRINSIC intrinsic(@llvm.mips.mod.u.h), %3(<8 x s16>), %4(<8 x s16>)
G_STORE %5(<8 x s16>), %2(p0) :: (store (<8 x s16>) into %ir.c)
RetRA
...
---
name: umod_v4i32_builtin
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; P5600-LABEL: name: umod_v4i32_builtin
; P5600: liveins: $a0, $a1, $a2
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
; P5600: [[LOAD:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY]](p0) :: (load (<4 x s32>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<4 x s32>) = G_LOAD [[COPY1]](p0) :: (load (<4 x s32>) from %ir.b)
; P5600: [[UREM:%[0-9]+]]:_(<4 x s32>) = G_UREM [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[UREM]](<4 x s32>), [[COPY2]](p0) :: (store (<4 x s32>) into %ir.c)
; P5600: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
%2:_(p0) = COPY $a2
%3:_(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>) from %ir.a)
%4:_(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>) from %ir.b)
%5:_(<4 x s32>) = G_INTRINSIC intrinsic(@llvm.mips.mod.u.w), %3(<4 x s32>), %4(<4 x s32>)
G_STORE %5(<4 x s32>), %2(p0) :: (store (<4 x s32>) into %ir.c)
RetRA
...
---
name: umod_v2i64_builtin
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1, $a2
; P5600-LABEL: name: umod_v2i64_builtin
; P5600: liveins: $a0, $a1, $a2
; P5600: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; P5600: [[COPY1:%[0-9]+]]:_(p0) = COPY $a1
; P5600: [[COPY2:%[0-9]+]]:_(p0) = COPY $a2
; P5600: [[LOAD:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY]](p0) :: (load (<2 x s64>) from %ir.a)
; P5600: [[LOAD1:%[0-9]+]]:_(<2 x s64>) = G_LOAD [[COPY1]](p0) :: (load (<2 x s64>) from %ir.b)
; P5600: [[UREM:%[0-9]+]]:_(<2 x s64>) = G_UREM [[LOAD]], [[LOAD1]]
; P5600: G_STORE [[UREM]](<2 x s64>), [[COPY2]](p0) :: (store (<2 x s64>) into %ir.c)
; P5600: RetRA
%0:_(p0) = COPY $a0
%1:_(p0) = COPY $a1
%2:_(p0) = COPY $a2
%3:_(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>) from %ir.a)
%4:_(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>) from %ir.b)
%5:_(<2 x s64>) = G_INTRINSIC intrinsic(@llvm.mips.mod.u.d), %3(<2 x s64>), %4(<2 x s64>)
G_STORE %5(<2 x s64>), %2(p0) :: (store (<2 x s64>) into %ir.c)
RetRA
...