# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64 -run-pass=legalizer %s -o - -verify-machineinstrs | FileCheck %s
---
name:            test_v2i64_eq
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v2i64_eq
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(eq), [[COPY]](<2 x s64>), [[COPY1]]
    ; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[ICMP]](<2 x s64>)
    ; CHECK: $d0 = COPY [[TRUNC]](<2 x s32>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<2 x s64>) = COPY $q0
    %1:_(<2 x s64>) = COPY $q1
    %2:_(<2 x s1>) = G_ICMP intpred(eq), %0(<2 x s64>), %1
    %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>)
    $d0 = COPY %3(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v4i32_eq
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v4i32_eq
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(eq), [[COPY]](<4 x s32>), [[COPY1]]
    ; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>)
    ; CHECK: $d0 = COPY [[TRUNC]](<4 x s16>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<4 x s32>) = COPY $q0
    %1:_(<4 x s32>) = COPY $q1
    %2:_(<4 x s1>) = G_ICMP intpred(eq), %0(<4 x s32>), %1
    %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>)
    $d0 = COPY %3(<4 x s16>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i32_eq
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v2i32_eq
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(eq), [[COPY]](<2 x s32>), [[COPY1]]
    ; CHECK: $d0 = COPY [[ICMP]](<2 x s32>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<2 x s32>) = COPY $d0
    %1:_(<2 x s32>) = COPY $d1
    %2:_(<2 x s1>) = G_ICMP intpred(eq), %0(<2 x s32>), %1
    %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>)
    $d0 = COPY %3(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v8i16_eq
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v8i16_eq
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s16>) = G_ICMP intpred(eq), [[COPY]](<8 x s16>), [[COPY1]]
    ; CHECK: [[TRUNC:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[ICMP]](<8 x s16>)
    ; CHECK: $d0 = COPY [[TRUNC]](<8 x s8>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<8 x s16>) = COPY $q0
    %1:_(<8 x s16>) = COPY $q1
    %2:_(<8 x s1>) = G_ICMP intpred(eq), %0(<8 x s16>), %1
    %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>)
    $d0 = COPY %3(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v4i16_eq
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v4i16_eq
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(eq), [[COPY]](<4 x s16>), [[COPY1]]
    ; CHECK: $d0 = COPY [[ICMP]](<4 x s16>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<4 x s16>) = COPY $d0
    %1:_(<4 x s16>) = COPY $d1
    %2:_(<4 x s1>) = G_ICMP intpred(eq), %0(<4 x s16>), %1
    %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>)
    $d0 = COPY %3(<4 x s16>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v16i8_eq
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v16i8_eq
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(eq), [[COPY]](<16 x s8>), [[COPY1]]
    ; CHECK: $q0 = COPY [[ICMP]](<16 x s8>)
    ; CHECK: RET_ReallyLR implicit $q0
    %0:_(<16 x s8>) = COPY $q0
    %1:_(<16 x s8>) = COPY $q1
    %2:_(<16 x s1>) = G_ICMP intpred(eq), %0(<16 x s8>), %1
    %3:_(<16 x s8>) = G_ANYEXT %2(<16 x s1>)
    $q0 = COPY %3(<16 x s8>)
    RET_ReallyLR implicit $q0

...
---
name:            test_v8i8_eq
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v8i8_eq
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(eq), [[COPY]](<8 x s8>), [[COPY1]]
    ; CHECK: $d0 = COPY [[ICMP]](<8 x s8>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<8 x s8>) = COPY $d0
    %1:_(<8 x s8>) = COPY $d1
    %2:_(<8 x s1>) = G_ICMP intpred(eq), %0(<8 x s8>), %1
    %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>)
    $d0 = COPY %3(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i64_ugt
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v2i64_ugt
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ugt), [[COPY]](<2 x s64>), [[COPY1]]
    ; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[ICMP]](<2 x s64>)
    ; CHECK: $d0 = COPY [[TRUNC]](<2 x s32>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<2 x s64>) = COPY $q0
    %1:_(<2 x s64>) = COPY $q1
    %2:_(<2 x s1>) = G_ICMP intpred(ugt), %0(<2 x s64>), %1
    %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>)
    $d0 = COPY %3(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v4i32_ugt
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v4i32_ugt
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(ugt), [[COPY]](<4 x s32>), [[COPY1]]
    ; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>)
    ; CHECK: $d0 = COPY [[TRUNC]](<4 x s16>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<4 x s32>) = COPY $q0
    %1:_(<4 x s32>) = COPY $q1
    %2:_(<4 x s1>) = G_ICMP intpred(ugt), %0(<4 x s32>), %1
    %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>)
    $d0 = COPY %3(<4 x s16>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i32_ugt
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v2i32_ugt
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(ugt), [[COPY]](<2 x s32>), [[COPY1]]
    ; CHECK: $d0 = COPY [[ICMP]](<2 x s32>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<2 x s32>) = COPY $d0
    %1:_(<2 x s32>) = COPY $d1
    %2:_(<2 x s1>) = G_ICMP intpred(ugt), %0(<2 x s32>), %1
    %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>)
    $d0 = COPY %3(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v8i16_ugt
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v8i16_ugt
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s16>) = G_ICMP intpred(ugt), [[COPY]](<8 x s16>), [[COPY1]]
    ; CHECK: [[TRUNC:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[ICMP]](<8 x s16>)
    ; CHECK: $d0 = COPY [[TRUNC]](<8 x s8>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<8 x s16>) = COPY $q0
    %1:_(<8 x s16>) = COPY $q1
    %2:_(<8 x s1>) = G_ICMP intpred(ugt), %0(<8 x s16>), %1
    %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>)
    $d0 = COPY %3(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v4i16_ugt
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v4i16_ugt
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(ugt), [[COPY]](<4 x s16>), [[COPY1]]
    ; CHECK: $d0 = COPY [[ICMP]](<4 x s16>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<4 x s16>) = COPY $d0
    %1:_(<4 x s16>) = COPY $d1
    %2:_(<4 x s1>) = G_ICMP intpred(ugt), %0(<4 x s16>), %1
    %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>)
    $d0 = COPY %3(<4 x s16>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v16i8_ugt
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v16i8_ugt
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(ugt), [[COPY]](<16 x s8>), [[COPY1]]
    ; CHECK: $q0 = COPY [[ICMP]](<16 x s8>)
    ; CHECK: RET_ReallyLR implicit $q0
    %0:_(<16 x s8>) = COPY $q0
    %1:_(<16 x s8>) = COPY $q1
    %2:_(<16 x s1>) = G_ICMP intpred(ugt), %0(<16 x s8>), %1
    %3:_(<16 x s8>) = G_ANYEXT %2(<16 x s1>)
    $q0 = COPY %3(<16 x s8>)
    RET_ReallyLR implicit $q0

...
---
name:            test_v8i8_ugt
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v8i8_ugt
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(ugt), [[COPY]](<8 x s8>), [[COPY1]]
    ; CHECK: $d0 = COPY [[ICMP]](<8 x s8>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<8 x s8>) = COPY $d0
    %1:_(<8 x s8>) = COPY $d1
    %2:_(<8 x s1>) = G_ICMP intpred(ugt), %0(<8 x s8>), %1
    %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>)
    $d0 = COPY %3(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i64_uge
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v2i64_uge
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(uge), [[COPY]](<2 x s64>), [[COPY1]]
    ; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[ICMP]](<2 x s64>)
    ; CHECK: $d0 = COPY [[TRUNC]](<2 x s32>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<2 x s64>) = COPY $q0
    %1:_(<2 x s64>) = COPY $q1
    %2:_(<2 x s1>) = G_ICMP intpred(uge), %0(<2 x s64>), %1
    %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>)
    $d0 = COPY %3(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v4i32_uge
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v4i32_uge
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(uge), [[COPY]](<4 x s32>), [[COPY1]]
    ; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>)
    ; CHECK: $d0 = COPY [[TRUNC]](<4 x s16>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<4 x s32>) = COPY $q0
    %1:_(<4 x s32>) = COPY $q1
    %2:_(<4 x s1>) = G_ICMP intpred(uge), %0(<4 x s32>), %1
    %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>)
    $d0 = COPY %3(<4 x s16>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i32_uge
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v2i32_uge
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(uge), [[COPY]](<2 x s32>), [[COPY1]]
    ; CHECK: $d0 = COPY [[ICMP]](<2 x s32>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<2 x s32>) = COPY $d0
    %1:_(<2 x s32>) = COPY $d1
    %2:_(<2 x s1>) = G_ICMP intpred(uge), %0(<2 x s32>), %1
    %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>)
    $d0 = COPY %3(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v8i16_uge
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v8i16_uge
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s16>) = G_ICMP intpred(uge), [[COPY]](<8 x s16>), [[COPY1]]
    ; CHECK: [[TRUNC:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[ICMP]](<8 x s16>)
    ; CHECK: $d0 = COPY [[TRUNC]](<8 x s8>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<8 x s16>) = COPY $q0
    %1:_(<8 x s16>) = COPY $q1
    %2:_(<8 x s1>) = G_ICMP intpred(uge), %0(<8 x s16>), %1
    %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>)
    $d0 = COPY %3(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v4i16_uge
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v4i16_uge
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(uge), [[COPY]](<4 x s16>), [[COPY1]]
    ; CHECK: $d0 = COPY [[ICMP]](<4 x s16>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<4 x s16>) = COPY $d0
    %1:_(<4 x s16>) = COPY $d1
    %2:_(<4 x s1>) = G_ICMP intpred(uge), %0(<4 x s16>), %1
    %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>)
    $d0 = COPY %3(<4 x s16>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v16i8_uge
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v16i8_uge
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(uge), [[COPY]](<16 x s8>), [[COPY1]]
    ; CHECK: $q0 = COPY [[ICMP]](<16 x s8>)
    ; CHECK: RET_ReallyLR implicit $q0
    %0:_(<16 x s8>) = COPY $q0
    %1:_(<16 x s8>) = COPY $q1
    %2:_(<16 x s1>) = G_ICMP intpred(uge), %0(<16 x s8>), %1
    %3:_(<16 x s8>) = G_ANYEXT %2(<16 x s1>)
    $q0 = COPY %3(<16 x s8>)
    RET_ReallyLR implicit $q0

...
---
name:            test_v8i8_uge
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v8i8_uge
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(uge), [[COPY]](<8 x s8>), [[COPY1]]
    ; CHECK: $d0 = COPY [[ICMP]](<8 x s8>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<8 x s8>) = COPY $d0
    %1:_(<8 x s8>) = COPY $d1
    %2:_(<8 x s1>) = G_ICMP intpred(uge), %0(<8 x s8>), %1
    %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>)
    $d0 = COPY %3(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i64_ult
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v2i64_ult
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ult), [[COPY]](<2 x s64>), [[COPY1]]
    ; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[ICMP]](<2 x s64>)
    ; CHECK: $d0 = COPY [[TRUNC]](<2 x s32>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<2 x s64>) = COPY $q0
    %1:_(<2 x s64>) = COPY $q1
    %2:_(<2 x s1>) = G_ICMP intpred(ult), %0(<2 x s64>), %1
    %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>)
    $d0 = COPY %3(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v4i32_ult
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v4i32_ult
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(ult), [[COPY]](<4 x s32>), [[COPY1]]
    ; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>)
    ; CHECK: $d0 = COPY [[TRUNC]](<4 x s16>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<4 x s32>) = COPY $q0
    %1:_(<4 x s32>) = COPY $q1
    %2:_(<4 x s1>) = G_ICMP intpred(ult), %0(<4 x s32>), %1
    %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>)
    $d0 = COPY %3(<4 x s16>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i32_ult
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v2i32_ult
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(ult), [[COPY]](<2 x s32>), [[COPY1]]
    ; CHECK: $d0 = COPY [[ICMP]](<2 x s32>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<2 x s32>) = COPY $d0
    %1:_(<2 x s32>) = COPY $d1
    %2:_(<2 x s1>) = G_ICMP intpred(ult), %0(<2 x s32>), %1
    %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>)
    $d0 = COPY %3(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v8i16_ult
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v8i16_ult
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s16>) = G_ICMP intpred(ult), [[COPY]](<8 x s16>), [[COPY1]]
    ; CHECK: [[TRUNC:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[ICMP]](<8 x s16>)
    ; CHECK: $d0 = COPY [[TRUNC]](<8 x s8>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<8 x s16>) = COPY $q0
    %1:_(<8 x s16>) = COPY $q1
    %2:_(<8 x s1>) = G_ICMP intpred(ult), %0(<8 x s16>), %1
    %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>)
    $d0 = COPY %3(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v4i16_ult
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v4i16_ult
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(ult), [[COPY]](<4 x s16>), [[COPY1]]
    ; CHECK: $d0 = COPY [[ICMP]](<4 x s16>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<4 x s16>) = COPY $d0
    %1:_(<4 x s16>) = COPY $d1
    %2:_(<4 x s1>) = G_ICMP intpred(ult), %0(<4 x s16>), %1
    %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>)
    $d0 = COPY %3(<4 x s16>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v16i8_ult
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v16i8_ult
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(ult), [[COPY]](<16 x s8>), [[COPY1]]
    ; CHECK: $q0 = COPY [[ICMP]](<16 x s8>)
    ; CHECK: RET_ReallyLR implicit $q0
    %0:_(<16 x s8>) = COPY $q0
    %1:_(<16 x s8>) = COPY $q1
    %2:_(<16 x s1>) = G_ICMP intpred(ult), %0(<16 x s8>), %1
    %3:_(<16 x s8>) = G_ANYEXT %2(<16 x s1>)
    $q0 = COPY %3(<16 x s8>)
    RET_ReallyLR implicit $q0

...
---
name:            test_v8i8_ult
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v8i8_ult
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(ult), [[COPY]](<8 x s8>), [[COPY1]]
    ; CHECK: $d0 = COPY [[ICMP]](<8 x s8>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<8 x s8>) = COPY $d0
    %1:_(<8 x s8>) = COPY $d1
    %2:_(<8 x s1>) = G_ICMP intpred(ult), %0(<8 x s8>), %1
    %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>)
    $d0 = COPY %3(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i64_ule
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v2i64_ule
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ule), [[COPY]](<2 x s64>), [[COPY1]]
    ; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[ICMP]](<2 x s64>)
    ; CHECK: $d0 = COPY [[TRUNC]](<2 x s32>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<2 x s64>) = COPY $q0
    %1:_(<2 x s64>) = COPY $q1
    %2:_(<2 x s1>) = G_ICMP intpred(ule), %0(<2 x s64>), %1
    %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>)
    $d0 = COPY %3(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v4i32_ule
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v4i32_ule
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(ule), [[COPY]](<4 x s32>), [[COPY1]]
    ; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>)
    ; CHECK: $d0 = COPY [[TRUNC]](<4 x s16>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<4 x s32>) = COPY $q0
    %1:_(<4 x s32>) = COPY $q1
    %2:_(<4 x s1>) = G_ICMP intpred(ule), %0(<4 x s32>), %1
    %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>)
    $d0 = COPY %3(<4 x s16>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i32_ule
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v2i32_ule
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(ule), [[COPY]](<2 x s32>), [[COPY1]]
    ; CHECK: $d0 = COPY [[ICMP]](<2 x s32>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<2 x s32>) = COPY $d0
    %1:_(<2 x s32>) = COPY $d1
    %2:_(<2 x s1>) = G_ICMP intpred(ule), %0(<2 x s32>), %1
    %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>)
    $d0 = COPY %3(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v8i16_ule
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v8i16_ule
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s16>) = G_ICMP intpred(ule), [[COPY]](<8 x s16>), [[COPY1]]
    ; CHECK: [[TRUNC:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[ICMP]](<8 x s16>)
    ; CHECK: $d0 = COPY [[TRUNC]](<8 x s8>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<8 x s16>) = COPY $q0
    %1:_(<8 x s16>) = COPY $q1
    %2:_(<8 x s1>) = G_ICMP intpred(ule), %0(<8 x s16>), %1
    %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>)
    $d0 = COPY %3(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v4i16_ule
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v4i16_ule
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(ule), [[COPY]](<4 x s16>), [[COPY1]]
    ; CHECK: $d0 = COPY [[ICMP]](<4 x s16>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<4 x s16>) = COPY $d0
    %1:_(<4 x s16>) = COPY $d1
    %2:_(<4 x s1>) = G_ICMP intpred(ule), %0(<4 x s16>), %1
    %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>)
    $d0 = COPY %3(<4 x s16>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v16i8_ule
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v16i8_ule
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(ule), [[COPY]](<16 x s8>), [[COPY1]]
    ; CHECK: $q0 = COPY [[ICMP]](<16 x s8>)
    ; CHECK: RET_ReallyLR implicit $q0
    %0:_(<16 x s8>) = COPY $q0
    %1:_(<16 x s8>) = COPY $q1
    %2:_(<16 x s1>) = G_ICMP intpred(ule), %0(<16 x s8>), %1
    %3:_(<16 x s8>) = G_ANYEXT %2(<16 x s1>)
    $q0 = COPY %3(<16 x s8>)
    RET_ReallyLR implicit $q0

...
---
name:            test_v8i8_ule
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v8i8_ule
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(ule), [[COPY]](<8 x s8>), [[COPY1]]
    ; CHECK: $d0 = COPY [[ICMP]](<8 x s8>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<8 x s8>) = COPY $d0
    %1:_(<8 x s8>) = COPY $d1
    %2:_(<8 x s1>) = G_ICMP intpred(ule), %0(<8 x s8>), %1
    %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>)
    $d0 = COPY %3(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i64_sgt
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v2i64_sgt
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sgt), [[COPY]](<2 x s64>), [[COPY1]]
    ; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[ICMP]](<2 x s64>)
    ; CHECK: $d0 = COPY [[TRUNC]](<2 x s32>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<2 x s64>) = COPY $q0
    %1:_(<2 x s64>) = COPY $q1
    %2:_(<2 x s1>) = G_ICMP intpred(sgt), %0(<2 x s64>), %1
    %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>)
    $d0 = COPY %3(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v4i32_sgt
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v4i32_sgt
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(sgt), [[COPY]](<4 x s32>), [[COPY1]]
    ; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>)
    ; CHECK: $d0 = COPY [[TRUNC]](<4 x s16>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<4 x s32>) = COPY $q0
    %1:_(<4 x s32>) = COPY $q1
    %2:_(<4 x s1>) = G_ICMP intpred(sgt), %0(<4 x s32>), %1
    %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>)
    $d0 = COPY %3(<4 x s16>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i32_sgt
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v2i32_sgt
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(sgt), [[COPY]](<2 x s32>), [[COPY1]]
    ; CHECK: $d0 = COPY [[ICMP]](<2 x s32>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<2 x s32>) = COPY $d0
    %1:_(<2 x s32>) = COPY $d1
    %2:_(<2 x s1>) = G_ICMP intpred(sgt), %0(<2 x s32>), %1
    %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>)
    $d0 = COPY %3(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v8i16_sgt
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v8i16_sgt
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s16>) = G_ICMP intpred(sgt), [[COPY]](<8 x s16>), [[COPY1]]
    ; CHECK: [[TRUNC:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[ICMP]](<8 x s16>)
    ; CHECK: $d0 = COPY [[TRUNC]](<8 x s8>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<8 x s16>) = COPY $q0
    %1:_(<8 x s16>) = COPY $q1
    %2:_(<8 x s1>) = G_ICMP intpred(sgt), %0(<8 x s16>), %1
    %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>)
    $d0 = COPY %3(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v4i16_sgt
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v4i16_sgt
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(sgt), [[COPY]](<4 x s16>), [[COPY1]]
    ; CHECK: $d0 = COPY [[ICMP]](<4 x s16>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<4 x s16>) = COPY $d0
    %1:_(<4 x s16>) = COPY $d1
    %2:_(<4 x s1>) = G_ICMP intpred(sgt), %0(<4 x s16>), %1
    %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>)
    $d0 = COPY %3(<4 x s16>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v16i8_sgt
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v16i8_sgt
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(sgt), [[COPY]](<16 x s8>), [[COPY1]]
    ; CHECK: $q0 = COPY [[ICMP]](<16 x s8>)
    ; CHECK: RET_ReallyLR implicit $q0
    %0:_(<16 x s8>) = COPY $q0
    %1:_(<16 x s8>) = COPY $q1
    %2:_(<16 x s1>) = G_ICMP intpred(sgt), %0(<16 x s8>), %1
    %3:_(<16 x s8>) = G_ANYEXT %2(<16 x s1>)
    $q0 = COPY %3(<16 x s8>)
    RET_ReallyLR implicit $q0

...
---
name:            test_v8i8_sgt
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v8i8_sgt
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(sgt), [[COPY]](<8 x s8>), [[COPY1]]
    ; CHECK: $d0 = COPY [[ICMP]](<8 x s8>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<8 x s8>) = COPY $d0
    %1:_(<8 x s8>) = COPY $d1
    %2:_(<8 x s1>) = G_ICMP intpred(sgt), %0(<8 x s8>), %1
    %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>)
    $d0 = COPY %3(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i64_sge
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v2i64_sge
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sge), [[COPY]](<2 x s64>), [[COPY1]]
    ; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[ICMP]](<2 x s64>)
    ; CHECK: $d0 = COPY [[TRUNC]](<2 x s32>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<2 x s64>) = COPY $q0
    %1:_(<2 x s64>) = COPY $q1
    %2:_(<2 x s1>) = G_ICMP intpred(sge), %0(<2 x s64>), %1
    %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>)
    $d0 = COPY %3(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v4i32_sge
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v4i32_sge
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(sge), [[COPY]](<4 x s32>), [[COPY1]]
    ; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>)
    ; CHECK: $d0 = COPY [[TRUNC]](<4 x s16>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<4 x s32>) = COPY $q0
    %1:_(<4 x s32>) = COPY $q1
    %2:_(<4 x s1>) = G_ICMP intpred(sge), %0(<4 x s32>), %1
    %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>)
    $d0 = COPY %3(<4 x s16>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i32_sge
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v2i32_sge
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(sge), [[COPY]](<2 x s32>), [[COPY1]]
    ; CHECK: $d0 = COPY [[ICMP]](<2 x s32>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<2 x s32>) = COPY $d0
    %1:_(<2 x s32>) = COPY $d1
    %2:_(<2 x s1>) = G_ICMP intpred(sge), %0(<2 x s32>), %1
    %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>)
    $d0 = COPY %3(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v8i16_sge
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v8i16_sge
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s16>) = G_ICMP intpred(sge), [[COPY]](<8 x s16>), [[COPY1]]
    ; CHECK: [[TRUNC:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[ICMP]](<8 x s16>)
    ; CHECK: $d0 = COPY [[TRUNC]](<8 x s8>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<8 x s16>) = COPY $q0
    %1:_(<8 x s16>) = COPY $q1
    %2:_(<8 x s1>) = G_ICMP intpred(sge), %0(<8 x s16>), %1
    %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>)
    $d0 = COPY %3(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v4i16_sge
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v4i16_sge
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(sge), [[COPY]](<4 x s16>), [[COPY1]]
    ; CHECK: $d0 = COPY [[ICMP]](<4 x s16>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<4 x s16>) = COPY $d0
    %1:_(<4 x s16>) = COPY $d1
    %2:_(<4 x s1>) = G_ICMP intpred(sge), %0(<4 x s16>), %1
    %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>)
    $d0 = COPY %3(<4 x s16>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v16i8_sge
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v16i8_sge
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(sge), [[COPY]](<16 x s8>), [[COPY1]]
    ; CHECK: $q0 = COPY [[ICMP]](<16 x s8>)
    ; CHECK: RET_ReallyLR implicit $q0
    %0:_(<16 x s8>) = COPY $q0
    %1:_(<16 x s8>) = COPY $q1
    %2:_(<16 x s1>) = G_ICMP intpred(sge), %0(<16 x s8>), %1
    %3:_(<16 x s8>) = G_ANYEXT %2(<16 x s1>)
    $q0 = COPY %3(<16 x s8>)
    RET_ReallyLR implicit $q0

...
---
name:            test_v8i8_sge
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v8i8_sge
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(sge), [[COPY]](<8 x s8>), [[COPY1]]
    ; CHECK: $d0 = COPY [[ICMP]](<8 x s8>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<8 x s8>) = COPY $d0
    %1:_(<8 x s8>) = COPY $d1
    %2:_(<8 x s1>) = G_ICMP intpred(sge), %0(<8 x s8>), %1
    %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>)
    $d0 = COPY %3(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i64_slt
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v2i64_slt
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(slt), [[COPY]](<2 x s64>), [[COPY1]]
    ; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[ICMP]](<2 x s64>)
    ; CHECK: $d0 = COPY [[TRUNC]](<2 x s32>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<2 x s64>) = COPY $q0
    %1:_(<2 x s64>) = COPY $q1
    %2:_(<2 x s1>) = G_ICMP intpred(slt), %0(<2 x s64>), %1
    %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>)
    $d0 = COPY %3(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v4i32_slt
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v4i32_slt
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(slt), [[COPY]](<4 x s32>), [[COPY1]]
    ; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>)
    ; CHECK: $d0 = COPY [[TRUNC]](<4 x s16>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<4 x s32>) = COPY $q0
    %1:_(<4 x s32>) = COPY $q1
    %2:_(<4 x s1>) = G_ICMP intpred(slt), %0(<4 x s32>), %1
    %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>)
    $d0 = COPY %3(<4 x s16>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i32_slt
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v2i32_slt
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(slt), [[COPY]](<2 x s32>), [[COPY1]]
    ; CHECK: $d0 = COPY [[ICMP]](<2 x s32>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<2 x s32>) = COPY $d0
    %1:_(<2 x s32>) = COPY $d1
    %2:_(<2 x s1>) = G_ICMP intpred(slt), %0(<2 x s32>), %1
    %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>)
    $d0 = COPY %3(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v8i16_slt
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v8i16_slt
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s16>) = G_ICMP intpred(slt), [[COPY]](<8 x s16>), [[COPY1]]
    ; CHECK: [[TRUNC:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[ICMP]](<8 x s16>)
    ; CHECK: $d0 = COPY [[TRUNC]](<8 x s8>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<8 x s16>) = COPY $q0
    %1:_(<8 x s16>) = COPY $q1
    %2:_(<8 x s1>) = G_ICMP intpred(slt), %0(<8 x s16>), %1
    %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>)
    $d0 = COPY %3(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v4i16_slt
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v4i16_slt
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(slt), [[COPY]](<4 x s16>), [[COPY1]]
    ; CHECK: $d0 = COPY [[ICMP]](<4 x s16>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<4 x s16>) = COPY $d0
    %1:_(<4 x s16>) = COPY $d1
    %2:_(<4 x s1>) = G_ICMP intpred(slt), %0(<4 x s16>), %1
    %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>)
    $d0 = COPY %3(<4 x s16>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v16i8_slt
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v16i8_slt
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(slt), [[COPY]](<16 x s8>), [[COPY1]]
    ; CHECK: $q0 = COPY [[ICMP]](<16 x s8>)
    ; CHECK: RET_ReallyLR implicit $q0
    %0:_(<16 x s8>) = COPY $q0
    %1:_(<16 x s8>) = COPY $q1
    %2:_(<16 x s1>) = G_ICMP intpred(slt), %0(<16 x s8>), %1
    %3:_(<16 x s8>) = G_ANYEXT %2(<16 x s1>)
    $q0 = COPY %3(<16 x s8>)
    RET_ReallyLR implicit $q0

...
---
name:            test_v8i8_slt
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v8i8_slt
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(slt), [[COPY]](<8 x s8>), [[COPY1]]
    ; CHECK: $d0 = COPY [[ICMP]](<8 x s8>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<8 x s8>) = COPY $d0
    %1:_(<8 x s8>) = COPY $d1
    %2:_(<8 x s1>) = G_ICMP intpred(slt), %0(<8 x s8>), %1
    %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>)
    $d0 = COPY %3(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i64_sle
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v2i64_sle
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sle), [[COPY]](<2 x s64>), [[COPY1]]
    ; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[ICMP]](<2 x s64>)
    ; CHECK: $d0 = COPY [[TRUNC]](<2 x s32>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<2 x s64>) = COPY $q0
    %1:_(<2 x s64>) = COPY $q1
    %2:_(<2 x s1>) = G_ICMP intpred(sle), %0(<2 x s64>), %1
    %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>)
    $d0 = COPY %3(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v4i32_sle
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v4i32_sle
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(sle), [[COPY]](<4 x s32>), [[COPY1]]
    ; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>)
    ; CHECK: $d0 = COPY [[TRUNC]](<4 x s16>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<4 x s32>) = COPY $q0
    %1:_(<4 x s32>) = COPY $q1
    %2:_(<4 x s1>) = G_ICMP intpred(sle), %0(<4 x s32>), %1
    %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>)
    $d0 = COPY %3(<4 x s16>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2i32_sle
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v2i32_sle
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(sle), [[COPY]](<2 x s32>), [[COPY1]]
    ; CHECK: $d0 = COPY [[ICMP]](<2 x s32>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<2 x s32>) = COPY $d0
    %1:_(<2 x s32>) = COPY $d1
    %2:_(<2 x s1>) = G_ICMP intpred(sle), %0(<2 x s32>), %1
    %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>)
    $d0 = COPY %3(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v8i16_sle
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v8i16_sle
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s16>) = G_ICMP intpred(sle), [[COPY]](<8 x s16>), [[COPY1]]
    ; CHECK: [[TRUNC:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[ICMP]](<8 x s16>)
    ; CHECK: $d0 = COPY [[TRUNC]](<8 x s8>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<8 x s16>) = COPY $q0
    %1:_(<8 x s16>) = COPY $q1
    %2:_(<8 x s1>) = G_ICMP intpred(sle), %0(<8 x s16>), %1
    %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>)
    $d0 = COPY %3(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v4i16_sle
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v4i16_sle
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(sle), [[COPY]](<4 x s16>), [[COPY1]]
    ; CHECK: $d0 = COPY [[ICMP]](<4 x s16>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<4 x s16>) = COPY $d0
    %1:_(<4 x s16>) = COPY $d1
    %2:_(<4 x s1>) = G_ICMP intpred(sle), %0(<4 x s16>), %1
    %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>)
    $d0 = COPY %3(<4 x s16>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v16i8_sle
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v16i8_sle
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(sle), [[COPY]](<16 x s8>), [[COPY1]]
    ; CHECK: $q0 = COPY [[ICMP]](<16 x s8>)
    ; CHECK: RET_ReallyLR implicit $q0
    %0:_(<16 x s8>) = COPY $q0
    %1:_(<16 x s8>) = COPY $q1
    %2:_(<16 x s1>) = G_ICMP intpred(sle), %0(<16 x s8>), %1
    %3:_(<16 x s8>) = G_ANYEXT %2(<16 x s1>)
    $q0 = COPY %3(<16 x s8>)
    RET_ReallyLR implicit $q0

...
---
name:            test_v8i8_sle
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $d0, $d1

    ; CHECK-LABEL: name: test_v8i8_sle
    ; CHECK: liveins: $d0, $d1
    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(sle), [[COPY]](<8 x s8>), [[COPY1]]
    ; CHECK: $d0 = COPY [[ICMP]](<8 x s8>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<8 x s8>) = COPY $d0
    %1:_(<8 x s8>) = COPY $d1
    %2:_(<8 x s1>) = G_ICMP intpred(sle), %0(<8 x s8>), %1
    %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>)
    $d0 = COPY %3(<8 x s8>)
    RET_ReallyLR implicit $d0

...
---
name:            test_v2p0_eq
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $q0, $q1

    ; CHECK-LABEL: name: test_v2p0_eq
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:_(<2 x p0>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<2 x p0>) = COPY $q1
    ; CHECK: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(eq), [[COPY]](<2 x p0>), [[COPY1]]
    ; CHECK: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[ICMP]](<2 x s64>)
    ; CHECK: $d0 = COPY [[TRUNC]](<2 x s32>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<2 x p0>) = COPY $q0
    %1:_(<2 x p0>) = COPY $q1
    %2:_(<2 x s1>) = G_ICMP intpred(eq), %0(<2 x p0>), %1
    %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>)
    $d0 = COPY %3(<2 x s32>)
    RET_ReallyLR implicit $d0

...
---
name:            icmp_8xs1
alignment:       4
tracksRegLiveness: true
liveins:
  - { reg: '$q0' }
  - { reg: '$q1' }
  - { reg: '$q2' }
  - { reg: '$q3' }
body:             |
  bb.1:
    liveins: $q0, $q1, $q2, $q3

    ; CHECK-LABEL: name: icmp_8xs1
    ; CHECK: liveins: $q0, $q1, $q2, $q3
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
    ; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $q2
    ; CHECK: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY $q3
    ; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(eq), [[COPY]](<4 x s32>), [[COPY2]]
    ; CHECK: [[ICMP1:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(eq), [[COPY1]](<4 x s32>), [[COPY3]]
    ; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>)
    ; CHECK: [[TRUNC1:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP1]](<4 x s32>)
    ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[TRUNC]](<4 x s16>), [[TRUNC1]](<4 x s16>)
    ; CHECK: [[TRUNC2:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[CONCAT_VECTORS]](<8 x s16>)
    ; CHECK: $d0 = COPY [[TRUNC2]](<8 x s8>)
    ; CHECK: RET_ReallyLR implicit $d0
    %2:_(<4 x s32>) = COPY $q0
    %3:_(<4 x s32>) = COPY $q1
    %0:_(<8 x s32>) = G_CONCAT_VECTORS %2(<4 x s32>), %3(<4 x s32>)
    %4:_(<4 x s32>) = COPY $q2
    %5:_(<4 x s32>) = COPY $q3
    %1:_(<8 x s32>) = G_CONCAT_VECTORS %4(<4 x s32>), %5(<4 x s32>)
    %6:_(<8 x s1>) = G_ICMP intpred(eq), %0(<8 x s32>), %1
    %7:_(<8 x s8>) = G_ANYEXT %6(<8 x s1>)
    $d0 = COPY %7(<8 x s8>)
    RET_ReallyLR implicit $d0
...
---
name:            icmp_8xs32
alignment:       4
tracksRegLiveness: true
liveins:
  - { reg: '$q0' }
  - { reg: '$q1' }
  - { reg: '$q2' }
  - { reg: '$q3' }
body:             |
  bb.1:
    liveins: $q0, $q1, $q2, $q3

    ; CHECK-LABEL: name: icmp_8xs32
    ; CHECK: liveins: $q0, $q1, $q2, $q3
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
    ; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $q2
    ; CHECK: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY $q3
    ; CHECK: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(eq), [[COPY]](<4 x s32>), [[COPY2]]
    ; CHECK: [[ICMP1:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(eq), [[COPY1]](<4 x s32>), [[COPY3]]
    ; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>)
    ; CHECK: [[TRUNC1:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP1]](<4 x s32>)
    ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[TRUNC]](<4 x s16>), [[TRUNC1]](<4 x s16>)
    ; CHECK: [[TRUNC2:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[CONCAT_VECTORS]](<8 x s16>)
    ; CHECK: $d0 = COPY [[TRUNC2]](<8 x s8>)
    ; CHECK: RET_ReallyLR implicit $d0
    %2:_(<4 x s32>) = COPY $q0
    %3:_(<4 x s32>) = COPY $q1
    %0:_(<8 x s32>) = G_CONCAT_VECTORS %2(<4 x s32>), %3(<4 x s32>)
    %4:_(<4 x s32>) = COPY $q2
    %5:_(<4 x s32>) = COPY $q3
    %1:_(<8 x s32>) = G_CONCAT_VECTORS %4(<4 x s32>), %5(<4 x s32>)
    %6:_(<8 x s32>) = G_ICMP intpred(eq), %0(<8 x s32>), %1
    %7:_(<8 x s8>) = G_TRUNC %6(<8 x s32>)
    $d0 = COPY %7(<8 x s8>)
    RET_ReallyLR implicit $d0
...
---
name:            fcmp_8xs1
alignment:       4
tracksRegLiveness: true
liveins:
  - { reg: '$q0' }
  - { reg: '$q1' }
  - { reg: '$q2' }
  - { reg: '$q3' }
body:             |
  bb.1:
    liveins: $q0, $q1, $q2, $q3

    ; CHECK-LABEL: name: fcmp_8xs1
    ; CHECK: liveins: $q0, $q1, $q2, $q3
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
    ; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $q2
    ; CHECK: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY $q3
    ; CHECK: [[FCMP:%[0-9]+]]:_(<4 x s32>) = G_FCMP floatpred(one), [[COPY]](<4 x s32>), [[COPY2]]
    ; CHECK: [[FCMP1:%[0-9]+]]:_(<4 x s32>) = G_FCMP floatpred(one), [[COPY1]](<4 x s32>), [[COPY3]]
    ; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[FCMP]](<4 x s32>)
    ; CHECK: [[TRUNC1:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[FCMP1]](<4 x s32>)
    ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[TRUNC]](<4 x s16>), [[TRUNC1]](<4 x s16>)
    ; CHECK: [[TRUNC2:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[CONCAT_VECTORS]](<8 x s16>)
    ; CHECK: $d0 = COPY [[TRUNC2]](<8 x s8>)
    ; CHECK: RET_ReallyLR implicit $d0
    %2:_(<4 x s32>) = COPY $q0
    %3:_(<4 x s32>) = COPY $q1
    %0:_(<8 x s32>) = G_CONCAT_VECTORS %2(<4 x s32>), %3(<4 x s32>)
    %4:_(<4 x s32>) = COPY $q2
    %5:_(<4 x s32>) = COPY $q3
    %1:_(<8 x s32>) = G_CONCAT_VECTORS %4(<4 x s32>), %5(<4 x s32>)
    %6:_(<8 x s1>) = G_FCMP floatpred(one), %0(<8 x s32>), %1
    %7:_(<8 x s8>) = G_ANYEXT %6(<8 x s1>)
    $d0 = COPY %7(<8 x s8>)
    RET_ReallyLR implicit $d0
...
---
name:            fcmp_8xs32
alignment:       4
tracksRegLiveness: true
liveins:
  - { reg: '$q0' }
  - { reg: '$q1' }
  - { reg: '$q2' }
  - { reg: '$q3' }
body:             |
  bb.1:
    liveins: $q0, $q1, $q2, $q3

    ; CHECK-LABEL: name: fcmp_8xs32
    ; CHECK: liveins: $q0, $q1, $q2, $q3
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
    ; CHECK: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $q2
    ; CHECK: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY $q3
    ; CHECK: [[FCMP:%[0-9]+]]:_(<4 x s32>) = G_FCMP floatpred(oeq), [[COPY]](<4 x s32>), [[COPY2]]
    ; CHECK: [[FCMP1:%[0-9]+]]:_(<4 x s32>) = G_FCMP floatpred(oeq), [[COPY1]](<4 x s32>), [[COPY3]]
    ; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[FCMP]](<4 x s32>)
    ; CHECK: [[TRUNC1:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[FCMP1]](<4 x s32>)
    ; CHECK: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[TRUNC]](<4 x s16>), [[TRUNC1]](<4 x s16>)
    ; CHECK: [[TRUNC2:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[CONCAT_VECTORS]](<8 x s16>)
    ; CHECK: $d0 = COPY [[TRUNC2]](<8 x s8>)
    ; CHECK: RET_ReallyLR implicit $d0
    %2:_(<4 x s32>) = COPY $q0
    %3:_(<4 x s32>) = COPY $q1
    %0:_(<8 x s32>) = G_CONCAT_VECTORS %2(<4 x s32>), %3(<4 x s32>)
    %4:_(<4 x s32>) = COPY $q2
    %5:_(<4 x s32>) = COPY $q3
    %1:_(<8 x s32>) = G_CONCAT_VECTORS %4(<4 x s32>), %5(<4 x s32>)
    %6:_(<8 x s32>) = G_FCMP floatpred(oeq), %0(<8 x s32>), %1
    %7:_(<8 x s8>) = G_TRUNC %6(<8 x s32>)
    $d0 = COPY %7(<8 x s8>)
    RET_ReallyLR implicit $d0
...
---
name:            fcmp_v4s32
alignment:       4
tracksRegLiveness: true
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
machineFunctionInfo: {}
body:             |
  bb.1:
    liveins: $q0, $q1

    ; CHECK-LABEL: name: fcmp_v4s32
    ; CHECK: liveins: $q0, $q1
    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
    ; CHECK: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
    ; CHECK: [[FCMP:%[0-9]+]]:_(<4 x s32>) = G_FCMP floatpred(olt), [[COPY]](<4 x s32>), [[COPY1]]
    ; CHECK: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[FCMP]](<4 x s32>)
    ; CHECK: $d0 = COPY [[TRUNC]](<4 x s16>)
    ; CHECK: RET_ReallyLR implicit $d0
    %0:_(<4 x s32>) = COPY $q0
    %1:_(<4 x s32>) = COPY $q1
    %2:_(<4 x s1>) = G_FCMP floatpred(olt), %0(<4 x s32>), %1
    %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>)
    $d0 = COPY %3(<4 x s16>)
    RET_ReallyLR implicit $d0

...