// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -no-opaque-pointers -triple riscv32 -target-feature +zksh -emit-llvm %s -o - \
// RUN:     | FileCheck %s  -check-prefix=RV32ZKSH

// RV32ZKSH-LABEL: @sm3p0(
// RV32ZKSH-NEXT:  entry:
// RV32ZKSH-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
// RV32ZKSH-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
// RV32ZKSH-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
// RV32ZKSH-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.sm3p0.i32(i32 [[TMP0]])
// RV32ZKSH-NEXT:    ret i32 [[TMP1]]
//
long sm3p0(long rs1)
{
  return __builtin_riscv_sm3p0(rs1);
}

// RV32ZKSH-LABEL: @sm3p1(
// RV32ZKSH-NEXT:  entry:
// RV32ZKSH-NEXT:    [[RS1_ADDR:%.*]] = alloca i32, align 4
// RV32ZKSH-NEXT:    store i32 [[RS1:%.*]], i32* [[RS1_ADDR]], align 4
// RV32ZKSH-NEXT:    [[TMP0:%.*]] = load i32, i32* [[RS1_ADDR]], align 4
// RV32ZKSH-NEXT:    [[TMP1:%.*]] = call i32 @llvm.riscv.sm3p1.i32(i32 [[TMP0]])
// RV32ZKSH-NEXT:    ret i32 [[TMP1]]
//
long sm3p1(long rs1) {
  return __builtin_riscv_sm3p1(rs1);
}