# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - -mtriple=x86_64-- -run-pass=twoaddressinstruction,simple-register-coalescing %s | FileCheck %s
# Tests for commuting ADCX and ADOX to avoid copies. The ADOX tests were manually constructed by modifying ADCX tests to use OF instead of CF.
--- |
  ; ModuleID = 'test.ll'
  source_filename = "test.ll"
  target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"

  define void @adcx32_commute(i8 %cf, i32 %a, i32 %b, i32* %res) #0 {
    %ret = call { i8, i32 } @llvm.x86.addcarry.32(i8 %cf, i32 %a, i32 %b)
    %1 = extractvalue { i8, i32 } %ret, 1
    %2 = mul i32 %a, %1
    store i32 %2, i32* %res
    ret void
  }

  define void @adcx64_commute(i8 %cf, i64 %a, i64 %b, i64* %res) #0 {
    %ret = call { i8, i64 } @llvm.x86.addcarry.64(i8 %cf, i64 %a, i64 %b)
    %1 = extractvalue { i8, i64 } %ret, 1
    %2 = mul i64 %a, %1
    store i64 %2, i64* %res
    ret void
  }

  define void @adox32_commute(i8 %cf, i32 %a, i32 %b, i32* %res) #0 {
    %ret = call { i8, i32 } @llvm.x86.addcarry.32(i8 %cf, i32 %a, i32 %b)
    %1 = extractvalue { i8, i32 } %ret, 1
    %2 = mul i32 %a, %1
    store i32 %2, i32* %res
    ret void
  }

  define void @adox64_commute(i8 %cf, i64 %a, i64 %b, i64* %res) #0 {
    %ret = call { i8, i64 } @llvm.x86.addcarry.64(i8 %cf, i64 %a, i64 %b)
    %1 = extractvalue { i8, i64 } %ret, 1
    %2 = mul i64 %a, %1
    store i64 %2, i64* %res
    ret void
  }

  ; Function Attrs: nounwind readnone
  declare { i8, i32 } @llvm.x86.addcarry.32(i8, i32, i32) #1

  ; Function Attrs: nounwind readnone
  declare { i8, i64 } @llvm.x86.addcarry.64(i8, i64, i64) #1

  ; Function Attrs: nounwind
  declare void @llvm.stackprotector(i8*, i8**) #2

  attributes #0 = { "target-features"="+adx" }
  attributes #1 = { nounwind readnone "target-features"="+adx" }
  attributes #2 = { nounwind }

...
---
name:            adcx32_commute
alignment:       16
tracksRegLiveness: true
registers:
  - { id: 0, class: gr32 }
  - { id: 1, class: gr32 }
  - { id: 2, class: gr32 }
  - { id: 3, class: gr64 }
  - { id: 4, class: gr8 }
  - { id: 5, class: gr8 }
  - { id: 6, class: gr32 }
  - { id: 7, class: gr32 }
liveins:
  - { reg: '$edi', virtual-reg: '%0' }
  - { reg: '$esi', virtual-reg: '%1' }
  - { reg: '$edx', virtual-reg: '%2' }
  - { reg: '$rcx', virtual-reg: '%3' }
body:             |
  bb.0 (%ir-block.0):
    liveins: $edi, $esi, $edx, $rcx

    ; CHECK-LABEL: name: adcx32_commute
    ; CHECK: liveins: $edi, $esi, $edx, $rcx
    ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rcx
    ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $edx
    ; CHECK: [[COPY2:%[0-9]+]]:gr32 = COPY $esi
    ; CHECK: [[COPY3:%[0-9]+]]:gr32 = COPY $edi
    ; CHECK: dead [[COPY3]].sub_8bit:gr32 = ADD8ri [[COPY3]].sub_8bit, -1, implicit-def $eflags
    ; CHECK: [[ADCX32rr:%[0-9]+]]:gr32 = ADCX32rr [[ADCX32rr]], [[COPY2]], implicit-def dead $eflags, implicit killed $eflags
    ; CHECK: [[IMUL32rr:%[0-9]+]]:gr32 = IMUL32rr [[IMUL32rr]], [[COPY2]], implicit-def dead $eflags
    ; CHECK: MOV32mr [[COPY]], 1, $noreg, 0, $noreg, [[IMUL32rr]] :: (store (s32) into %ir.res)
    ; CHECK: RET 0
    %3:gr64 = COPY killed $rcx
    %2:gr32 = COPY killed $edx
    %1:gr32 = COPY killed $esi
    %0:gr32 = COPY killed $edi
    %4:gr8 = COPY killed %0.sub_8bit
    dead %5:gr8 = ADD8ri killed %4, -1, implicit-def $eflags
    %6:gr32 = ADCX32rr %1, killed %2, implicit-def dead $eflags, implicit killed $eflags
    %7:gr32 = IMUL32rr killed %1, killed %6, implicit-def dead $eflags
    MOV32mr killed %3, 1, $noreg, 0, $noreg, killed %7 :: (store (s32) into %ir.res)
    RET 0

...
---
name:            adcx64_commute
alignment:       16
tracksRegLiveness: true
registers:
  - { id: 0, class: gr32 }
  - { id: 1, class: gr64 }
  - { id: 2, class: gr64 }
  - { id: 3, class: gr64 }
  - { id: 4, class: gr8 }
  - { id: 5, class: gr8 }
  - { id: 6, class: gr64 }
  - { id: 7, class: gr64 }
liveins:
  - { reg: '$edi', virtual-reg: '%0' }
  - { reg: '$rsi', virtual-reg: '%1' }
  - { reg: '$rdx', virtual-reg: '%2' }
  - { reg: '$rcx', virtual-reg: '%3' }
body:             |
  bb.0 (%ir-block.0):
    liveins: $edi, $rsi, $rdx, $rcx

    ; CHECK-LABEL: name: adcx64_commute
    ; CHECK: liveins: $edi, $rsi, $rdx, $rcx
    ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rcx
    ; CHECK: [[COPY1:%[0-9]+]]:gr64 = COPY $rdx
    ; CHECK: [[COPY2:%[0-9]+]]:gr64 = COPY $rsi
    ; CHECK: [[COPY3:%[0-9]+]]:gr32 = COPY $edi
    ; CHECK: dead [[COPY3]].sub_8bit:gr32 = ADD8ri [[COPY3]].sub_8bit, -1, implicit-def $eflags
    ; CHECK: [[ADCX64rr:%[0-9]+]]:gr64 = ADCX64rr [[ADCX64rr]], [[COPY2]], implicit-def dead $eflags, implicit killed $eflags
    ; CHECK: [[IMUL64rr:%[0-9]+]]:gr64 = IMUL64rr [[IMUL64rr]], [[COPY2]], implicit-def dead $eflags
    ; CHECK: MOV64mr [[COPY]], 1, $noreg, 0, $noreg, [[IMUL64rr]] :: (store (s64) into %ir.res)
    ; CHECK: RET 0
    %3:gr64 = COPY killed $rcx
    %2:gr64 = COPY killed $rdx
    %1:gr64 = COPY killed $rsi
    %0:gr32 = COPY killed $edi
    %4:gr8 = COPY killed %0.sub_8bit
    dead %5:gr8 = ADD8ri killed %4, -1, implicit-def $eflags
    %6:gr64 = ADCX64rr %1, killed %2, implicit-def dead $eflags, implicit killed $eflags
    %7:gr64 = IMUL64rr killed %1, killed %6, implicit-def dead $eflags
    MOV64mr killed %3, 1, $noreg, 0, $noreg, killed %7 :: (store (s64) into %ir.res)
    RET 0

...
---
name:            adox32_commute
alignment:       16
tracksRegLiveness: true
registers:
  - { id: 0, class: gr32 }
  - { id: 1, class: gr32 }
  - { id: 2, class: gr32 }
  - { id: 3, class: gr64 }
  - { id: 4, class: gr8 }
  - { id: 5, class: gr8 }
  - { id: 6, class: gr32 }
  - { id: 7, class: gr32 }
liveins:
  - { reg: '$edi', virtual-reg: '%0' }
  - { reg: '$esi', virtual-reg: '%1' }
  - { reg: '$edx', virtual-reg: '%2' }
  - { reg: '$rcx', virtual-reg: '%3' }
body:             |
  bb.0 (%ir-block.0):
    liveins: $edi, $esi, $edx, $rcx

    ; CHECK-LABEL: name: adox32_commute
    ; CHECK: liveins: $edi, $esi, $edx, $rcx
    ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rcx
    ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $edx
    ; CHECK: [[COPY2:%[0-9]+]]:gr32 = COPY $esi
    ; CHECK: [[COPY3:%[0-9]+]]:gr32 = COPY $edi
    ; CHECK: dead [[COPY3]].sub_8bit:gr32 = ADD8ri [[COPY3]].sub_8bit, 127, implicit-def $eflags
    ; CHECK: [[ADOX32rr:%[0-9]+]]:gr32 = ADOX32rr [[ADOX32rr]], [[COPY2]], implicit-def dead $eflags, implicit killed $eflags
    ; CHECK: [[IMUL32rr:%[0-9]+]]:gr32 = IMUL32rr [[IMUL32rr]], [[COPY2]], implicit-def dead $eflags
    ; CHECK: MOV32mr [[COPY]], 1, $noreg, 0, $noreg, [[IMUL32rr]] :: (store (s32) into %ir.res)
    ; CHECK: RET 0
    %3:gr64 = COPY killed $rcx
    %2:gr32 = COPY killed $edx
    %1:gr32 = COPY killed $esi
    %0:gr32 = COPY killed $edi
    %4:gr8 = COPY killed %0.sub_8bit
    dead %5:gr8 = ADD8ri killed %4, 127, implicit-def $eflags
    %6:gr32 = ADOX32rr %1, killed %2, implicit-def dead $eflags, implicit killed $eflags
    %7:gr32 = IMUL32rr killed %1, killed %6, implicit-def dead $eflags
    MOV32mr killed %3, 1, $noreg, 0, $noreg, killed %7 :: (store (s32) into %ir.res)
    RET 0

...
---
name:            adox64_commute
alignment:       16
tracksRegLiveness: true
registers:
  - { id: 0, class: gr32 }
  - { id: 1, class: gr64 }
  - { id: 2, class: gr64 }
  - { id: 3, class: gr64 }
  - { id: 4, class: gr8 }
  - { id: 5, class: gr8 }
  - { id: 6, class: gr64 }
  - { id: 7, class: gr64 }
liveins:
  - { reg: '$edi', virtual-reg: '%0' }
  - { reg: '$rsi', virtual-reg: '%1' }
  - { reg: '$rdx', virtual-reg: '%2' }
  - { reg: '$rcx', virtual-reg: '%3' }
body:             |
  bb.0 (%ir-block.0):
    liveins: $edi, $rsi, $rdx, $rcx

    ; CHECK-LABEL: name: adox64_commute
    ; CHECK: liveins: $edi, $rsi, $rdx, $rcx
    ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rcx
    ; CHECK: [[COPY1:%[0-9]+]]:gr64 = COPY $rdx
    ; CHECK: [[COPY2:%[0-9]+]]:gr64 = COPY $rsi
    ; CHECK: [[COPY3:%[0-9]+]]:gr32 = COPY $edi
    ; CHECK: dead [[COPY3]].sub_8bit:gr32 = ADD8ri [[COPY3]].sub_8bit, 127, implicit-def $eflags
    ; CHECK: [[ADOX64rr:%[0-9]+]]:gr64 = ADOX64rr [[ADOX64rr]], [[COPY2]], implicit-def dead $eflags, implicit killed $eflags
    ; CHECK: [[IMUL64rr:%[0-9]+]]:gr64 = IMUL64rr [[IMUL64rr]], [[COPY2]], implicit-def dead $eflags
    ; CHECK: MOV64mr [[COPY]], 1, $noreg, 0, $noreg, [[IMUL64rr]] :: (store (s64) into %ir.res)
    ; CHECK: RET 0
    %3:gr64 = COPY killed $rcx
    %2:gr64 = COPY killed $rdx
    %1:gr64 = COPY killed $rsi
    %0:gr32 = COPY killed $edi
    %4:gr8 = COPY killed %0.sub_8bit
    dead %5:gr8 = ADD8ri killed %4, 127, implicit-def $eflags
    %6:gr64 = ADOX64rr %1, killed %2, implicit-def dead $eflags, implicit killed $eflags
    %7:gr64 = IMUL64rr killed %1, killed %6, implicit-def dead $eflags
    MOV64mr killed %3, 1, $noreg, 0, $noreg, killed %7 :: (store (s64) into %ir.res)
    RET 0

...