# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --- | define void @test_insert_128_idx0() { ret void } define void @test_insert_128_idx0_undef() { ret void } define void @test_insert_128_idx1() { ret void } define void @test_insert_128_idx1_undef() { ret void } define void @test_insert_256_idx0() { ret void } define void @test_insert_256_idx0_undef() { ret void } define void @test_insert_256_idx1() { ret void } define void @test_insert_256_idx1_undef() { ret void } ... --- name: test_insert_128_idx0 alignment: 16 legalized: true regBankSelected: true registers: - { id: 0, class: vecr } - { id: 1, class: vecr } - { id: 2, class: vecr } body: | bb.1 (%ir-block.0): liveins: $zmm0, $ymm1 ; ALL-LABEL: name: test_insert_128_idx0 ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0 ; ALL: [[COPY1:%[0-9]+]]:vr128x = COPY $xmm1 ; ALL: [[VINSERTF32x4Zrr:%[0-9]+]]:vr512 = VINSERTF32x4Zrr [[COPY]], [[COPY1]], 0 ; ALL: $zmm0 = COPY [[VINSERTF32x4Zrr]] ; ALL: RET 0, implicit $ymm0 %0(<16 x s32>) = COPY $zmm0 %1(<4 x s32>) = COPY $xmm1 %2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<4 x s32>), 0 $zmm0 = COPY %2(<16 x s32>) RET 0, implicit $ymm0 ... --- name: test_insert_128_idx0_undef alignment: 16 legalized: true regBankSelected: true registers: - { id: 0, class: vecr } - { id: 1, class: vecr } - { id: 2, class: vecr } body: | bb.1 (%ir-block.0): liveins: $ymm0, $ymm1 ; ALL-LABEL: name: test_insert_128_idx0_undef ; ALL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm1 ; ALL: undef %2.sub_xmm:vr512 = COPY [[COPY]] ; ALL: $zmm0 = COPY %2 ; ALL: RET 0, implicit $ymm0 %0(<16 x s32>) = IMPLICIT_DEF %1(<4 x s32>) = COPY $xmm1 %2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<4 x s32>), 0 $zmm0 = COPY %2(<16 x s32>) RET 0, implicit $ymm0 ... --- name: test_insert_128_idx1 alignment: 16 legalized: true regBankSelected: true registers: - { id: 0, class: vecr } - { id: 1, class: vecr } - { id: 2, class: vecr } body: | bb.1 (%ir-block.0): liveins: $ymm0, $ymm1 ; ALL-LABEL: name: test_insert_128_idx1 ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0 ; ALL: [[COPY1:%[0-9]+]]:vr128x = COPY $xmm1 ; ALL: [[VINSERTF32x4Zrr:%[0-9]+]]:vr512 = VINSERTF32x4Zrr [[COPY]], [[COPY1]], 1 ; ALL: $zmm0 = COPY [[VINSERTF32x4Zrr]] ; ALL: RET 0, implicit $ymm0 %0(<16 x s32>) = COPY $zmm0 %1(<4 x s32>) = COPY $xmm1 %2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<4 x s32>), 128 $zmm0 = COPY %2(<16 x s32>) RET 0, implicit $ymm0 ... --- name: test_insert_128_idx1_undef alignment: 16 legalized: true regBankSelected: true registers: - { id: 0, class: vecr } - { id: 1, class: vecr } - { id: 2, class: vecr } body: | bb.1 (%ir-block.0): liveins: $ymm0, $ymm1 ; ALL-LABEL: name: test_insert_128_idx1_undef ; ALL: [[DEF:%[0-9]+]]:vr512 = IMPLICIT_DEF ; ALL: [[COPY:%[0-9]+]]:vr128x = COPY $xmm1 ; ALL: [[VINSERTF32x4Zrr:%[0-9]+]]:vr512 = VINSERTF32x4Zrr [[DEF]], [[COPY]], 1 ; ALL: $zmm0 = COPY [[VINSERTF32x4Zrr]] ; ALL: RET 0, implicit $ymm0 %0(<16 x s32>) = IMPLICIT_DEF %1(<4 x s32>) = COPY $xmm1 %2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<4 x s32>), 128 $zmm0 = COPY %2(<16 x s32>) RET 0, implicit $ymm0 ... --- name: test_insert_256_idx0 alignment: 16 legalized: true regBankSelected: true registers: - { id: 0, class: vecr } - { id: 1, class: vecr } - { id: 2, class: vecr } body: | bb.1 (%ir-block.0): liveins: $zmm0, $ymm1 ; ALL-LABEL: name: test_insert_256_idx0 ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0 ; ALL: [[COPY1:%[0-9]+]]:vr256x = COPY $ymm1 ; ALL: [[VINSERTF64x4Zrr:%[0-9]+]]:vr512 = VINSERTF64x4Zrr [[COPY]], [[COPY1]], 0 ; ALL: $zmm0 = COPY [[VINSERTF64x4Zrr]] ; ALL: RET 0, implicit $ymm0 %0(<16 x s32>) = COPY $zmm0 %1(<8 x s32>) = COPY $ymm1 %2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<8 x s32>), 0 $zmm0 = COPY %2(<16 x s32>) RET 0, implicit $ymm0 ... --- name: test_insert_256_idx0_undef alignment: 16 legalized: true regBankSelected: true registers: - { id: 0, class: vecr } - { id: 1, class: vecr } - { id: 2, class: vecr } body: | bb.1 (%ir-block.0): liveins: $ymm0, $ymm1 ; ALL-LABEL: name: test_insert_256_idx0_undef ; ALL: [[COPY:%[0-9]+]]:vr256x = COPY $ymm1 ; ALL: undef %2.sub_ymm:vr512 = COPY [[COPY]] ; ALL: $zmm0 = COPY %2 ; ALL: RET 0, implicit $ymm0 %0(<16 x s32>) = IMPLICIT_DEF %1(<8 x s32>) = COPY $ymm1 %2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<8 x s32>), 0 $zmm0 = COPY %2(<16 x s32>) RET 0, implicit $ymm0 ... --- name: test_insert_256_idx1 alignment: 16 legalized: true regBankSelected: true registers: - { id: 0, class: vecr } - { id: 1, class: vecr } - { id: 2, class: vecr } body: | bb.1 (%ir-block.0): liveins: $ymm0, $ymm1 ; ALL-LABEL: name: test_insert_256_idx1 ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0 ; ALL: [[COPY1:%[0-9]+]]:vr256x = COPY $ymm1 ; ALL: [[VINSERTF64x4Zrr:%[0-9]+]]:vr512 = VINSERTF64x4Zrr [[COPY]], [[COPY1]], 1 ; ALL: $zmm0 = COPY [[VINSERTF64x4Zrr]] ; ALL: RET 0, implicit $ymm0 %0(<16 x s32>) = COPY $zmm0 %1(<8 x s32>) = COPY $ymm1 %2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<8 x s32>), 256 $zmm0 = COPY %2(<16 x s32>) RET 0, implicit $ymm0 ... --- name: test_insert_256_idx1_undef alignment: 16 legalized: true regBankSelected: true registers: - { id: 0, class: vecr } - { id: 1, class: vecr } - { id: 2, class: vecr } body: | bb.1 (%ir-block.0): liveins: $ymm0, $ymm1 ; ALL-LABEL: name: test_insert_256_idx1_undef ; ALL: [[DEF:%[0-9]+]]:vr512 = IMPLICIT_DEF ; ALL: [[COPY:%[0-9]+]]:vr256x = COPY $ymm1 ; ALL: [[VINSERTF64x4Zrr:%[0-9]+]]:vr512 = VINSERTF64x4Zrr [[DEF]], [[COPY]], 1 ; ALL: $zmm0 = COPY [[VINSERTF64x4Zrr]] ; ALL: RET 0, implicit $ymm0 %0(<16 x s32>) = IMPLICIT_DEF %1(<8 x s32>) = COPY $ymm1 %2(<16 x s32>) = G_INSERT %0(<16 x s32>), %1(<8 x s32>), 256 $zmm0 = COPY %2(<16 x s32>) RET 0, implicit $ymm0 ...