; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+zknh -verify-machineinstrs < %s \
; RUN:   | FileCheck %s -check-prefix=RV64ZKNH


declare i64 @llvm.riscv.sha256sig0.i64(i64);

define i64 @sha256sig0_i64(i64 %a) nounwind {
; RV64ZKNH-LABEL: sha256sig0_i64:
; RV64ZKNH:       # %bb.0:
; RV64ZKNH-NEXT:    sha256sig0 a0, a0
; RV64ZKNH-NEXT:    ret
    %val = call i64 @llvm.riscv.sha256sig0.i64(i64 %a)
    ret i64 %val
}

declare i64 @llvm.riscv.sha256sig1.i64(i64);

define i64 @sha256sig1_i64(i64 %a) nounwind {
; RV64ZKNH-LABEL: sha256sig1_i64:
; RV64ZKNH:       # %bb.0:
; RV64ZKNH-NEXT:    sha256sig1 a0, a0
; RV64ZKNH-NEXT:    ret
    %val = call i64 @llvm.riscv.sha256sig1.i64(i64 %a)
    ret i64 %val
}

declare i64 @llvm.riscv.sha256sum0.i64(i64);

define i64 @sha256sum0_i64(i64 %a) nounwind {
; RV64ZKNH-LABEL: sha256sum0_i64:
; RV64ZKNH:       # %bb.0:
; RV64ZKNH-NEXT:    sha256sum0 a0, a0
; RV64ZKNH-NEXT:    ret
    %val = call i64 @llvm.riscv.sha256sum0.i64(i64 %a)
    ret i64 %val
}

declare i64 @llvm.riscv.sha256sum1.i64(i64);

define i64 @sha256sum1_i64(i64 %a) nounwind {
; RV64ZKNH-LABEL: sha256sum1_i64:
; RV64ZKNH:       # %bb.0:
; RV64ZKNH-NEXT:    sha256sum1 a0, a0
; RV64ZKNH-NEXT:    ret
    %val = call i64 @llvm.riscv.sha256sum1.i64(i64 %a)
    ret i64 %val
}

declare i64 @llvm.riscv.sha512sig0(i64);

define i64 @sha512sig0(i64 %a) nounwind {
; RV64ZKNH-LABEL: sha512sig0:
; RV64ZKNH:       # %bb.0:
; RV64ZKNH-NEXT:    sha512sig0 a0, a0
; RV64ZKNH-NEXT:    ret
    %val = call i64 @llvm.riscv.sha512sig0(i64 %a)
    ret i64 %val
}

declare i64 @llvm.riscv.sha512sig1(i64);

define i64 @sha512sig1(i64 %a) nounwind {
; RV64ZKNH-LABEL: sha512sig1:
; RV64ZKNH:       # %bb.0:
; RV64ZKNH-NEXT:    sha512sig1 a0, a0
; RV64ZKNH-NEXT:    ret
    %val = call i64 @llvm.riscv.sha512sig1(i64 %a)
    ret i64 %val
}

declare i64 @llvm.riscv.sha512sum0(i64);

define i64 @sha512sum0(i64 %a) nounwind {
; RV64ZKNH-LABEL: sha512sum0:
; RV64ZKNH:       # %bb.0:
; RV64ZKNH-NEXT:    sha512sum0 a0, a0
; RV64ZKNH-NEXT:    ret
    %val = call i64 @llvm.riscv.sha512sum0(i64 %a)
    ret i64 %val
}

declare i64 @llvm.riscv.sha512sum1(i64);

define i64 @sha512sum1(i64 %a) nounwind {
; RV64ZKNH-LABEL: sha512sum1:
; RV64ZKNH:       # %bb.0:
; RV64ZKNH-NEXT:    sha512sum1 a0, a0
; RV64ZKNH-NEXT:    ret
    %val = call i64 @llvm.riscv.sha512sum1(i64 %a)
    ret i64 %val
}