# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=machine-sink -sink-insts-to-avoid-spills %s -o - 2>&1 | FileCheck %s
--- |
target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
target triple = "aarch64"
@A = external dso_local global [100 x i32], align 4
%struct.A = type { i32, i32, i32, i32, i32, i32 }
define void @cant_sink_adds_call_in_block(i8* nocapture readonly %input, %struct.A* %a) {
%1 = getelementptr inbounds %struct.A, %struct.A* %a, i64 0, i32 1
%2 = getelementptr inbounds %struct.A, %struct.A* %a, i64 0, i32 2
%3 = getelementptr inbounds %struct.A, %struct.A* %a, i64 0, i32 3
%4 = getelementptr inbounds %struct.A, %struct.A* %a, i64 0, i32 4
%5 = getelementptr inbounds %struct.A, %struct.A* %a, i64 0, i32 5
%scevgep = getelementptr i8, i8* %input, i64 1
br label %.backedge
.backedge: ; preds = %.backedge.backedge, %0
%lsr.iv = phi i8* [ %scevgep1, %.backedge.backedge ], [ %scevgep, %0 ]
%6 = load i8, i8* %lsr.iv, align 1
%7 = zext i8 %6 to i32
switch i32 %7, label %.backedge.backedge [
i32 0, label %8
i32 10, label %10
i32 20, label %11
i32 30, label %12
i32 40, label %13
i32 50, label %14
]
8: ; preds = %.backedge
%9 = bitcast %struct.A* %a to i32*
tail call void @_Z6assignPj(i32* %9)
br label %.backedge.backedge
10: ; preds = %.backedge
tail call void @_Z6assignPj(i32* %1)
br label %.backedge.backedge
11: ; preds = %.backedge
tail call void @_Z6assignPj(i32* %2)
br label %.backedge.backedge
12: ; preds = %.backedge
tail call void @_Z6assignPj(i32* %3)
br label %.backedge.backedge
13: ; preds = %.backedge
tail call void @_Z6assignPj(i32* %4)
br label %.backedge.backedge
14: ; preds = %.backedge
tail call void @_Z6assignPj(i32* %5)
br label %.backedge.backedge
.backedge.backedge: ; preds = %14, %13, %12, %11, %10, %8, %.backedge
%scevgep1 = getelementptr i8, i8* %lsr.iv, i64 1
br label %.backedge
}
define i32 @load_not_safe_to_move_consecutive_call(i32 %n) {
entry:
%cmp63 = icmp sgt i32 %n, 0
br i1 %cmp63, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader: ; preds = %entry
%0 = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @A, i64 0, i64 0), align 4
%call0 = tail call i32 @use(i32 %n)
br label %for.body
for.cond.cleanup: ; preds = %for.body, %entry
%sum.0.lcssa = phi i32 [ %n, %entry ], [ %div, %for.body ]
ret i32 %sum.0.lcssa
for.body: ; preds = %for.body, %for.body.preheader
%lsr.iv = phi i32 [ %n, %for.body.preheader ], [ %lsr.iv.next, %for.body ]
%sum.065 = phi i32 [ %div, %for.body ], [ %n, %for.body.preheader ]
%div = sdiv i32 %sum.065, %0
%lsr.iv.next = add i32 %lsr.iv, -1
%exitcond.not = icmp eq i32 %lsr.iv.next, 0
br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
}
define i32 @load_not_safe_to_move_consecutive_call_use(i32 %n) {
entry:
%cmp63 = icmp sgt i32 %n, 0
br i1 %cmp63, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader: ; preds = %entry
%0 = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @A, i64 0, i64 0), align 4
%call0 = tail call i32 @use(i32 %0)
br label %for.body
for.cond.cleanup: ; preds = %for.body, %entry
%sum.0.lcssa = phi i32 [ %n, %entry ], [ %div, %for.body ]
ret i32 %sum.0.lcssa
for.body: ; preds = %for.body, %for.body.preheader
%lsr.iv = phi i32 [ %n, %for.body.preheader ], [ %lsr.iv.next, %for.body ]
%sum.065 = phi i32 [ %div, %for.body ], [ %n, %for.body.preheader ]
%div = sdiv i32 %sum.065, %0
%lsr.iv.next = add i32 %lsr.iv, -1
%exitcond.not = icmp eq i32 %lsr.iv.next, 0
br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
}
define i32 @cant_sink_use_outside_loop(i32 %n) {
entry:
%cmp63 = icmp sgt i32 %n, 0
br i1 %cmp63, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader: ; preds = %entry
%0 = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @A, i64 0, i64 0), align 4
br label %for.body
for.cond.cleanup: ; preds = %for.body, %entry
%sum.0.lcssa = phi i32 [ %n, %entry ], [ %div, %for.body ]
%use.outside.loop = phi i32 [ 0, %entry ], [ %0, %for.body ]
%call = tail call i32 @use(i32 %use.outside.loop)
ret i32 %sum.0.lcssa
for.body: ; preds = %for.body, %for.body.preheader
%lsr.iv = phi i32 [ %n, %for.body.preheader ], [ %lsr.iv.next, %for.body ]
%sum.065 = phi i32 [ %div, %for.body ], [ %n, %for.body.preheader ]
%div = sdiv i32 %sum.065, %sum.065
%lsr.iv.next = add i32 %lsr.iv, -1
%exitcond.not = icmp eq i32 %lsr.iv.next, 0
br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
}
define i32 @use_is_not_a_copy(i32 %n) {
entry:
%cmp63 = icmp sgt i32 %n, 0
br i1 %cmp63, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader: ; preds = %entry
%0 = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @A, i64 0, i64 0), align 4
br label %for.body
for.cond.cleanup: ; preds = %for.body, %entry
%sum.0.lcssa = phi i32 [ %n, %entry ], [ %div, %for.body ]
ret i32 %sum.0.lcssa
for.body: ; preds = %for.body, %for.body.preheader
%lsr.iv = phi i32 [ %n, %for.body.preheader ], [ %lsr.iv.next, %for.body ]
%sum.065 = phi i32 [ %div, %for.body ], [ %n, %for.body.preheader ]
%div = sdiv i32 %sum.065, %0
%lsr.iv.next = add i32 %lsr.iv, -1
%exitcond.not = icmp eq i32 %lsr.iv.next, 0
br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
}
define dso_local void @sink_add(i32* noalias nocapture readonly %read, i32* noalias nocapture %write, i32 %n) local_unnamed_addr #0 {
entry:
%0 = load i32, i32* %read, align 4, !tbaa !6
%cmp10 = icmp sgt i32 %n, 0
br i1 %cmp10, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader: ; preds = %entry
%1 = add i32 %0, 42
br label %for.body
for.cond.cleanup: ; preds = %for.body, %entry
%sum.0.lcssa = phi i32 [ %n, %entry ], [ %div, %for.body ]
store i32 %sum.0.lcssa, i32* %write, align 4, !tbaa !6
ret void
for.body: ; preds = %for.body.preheader, %for.body
%lsr.iv1 = phi i32 [ %1, %for.body.preheader ], [ %lsr.iv.next2, %for.body ]
%lsr.iv = phi i32 [ %n, %for.body.preheader ], [ %lsr.iv.next, %for.body ]
%sum.011 = phi i32 [ %div, %for.body ], [ %n, %for.body.preheader ]
%div = sdiv i32 %sum.011, %lsr.iv1
%lsr.iv.next = add i32 %lsr.iv, -1
%lsr.iv.next2 = add i32 %lsr.iv1, 1
%exitcond.not = icmp eq i32 %lsr.iv.next, 0
br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
}
define dso_local void @store_after_add(i32* noalias nocapture readonly %read, i32* noalias nocapture %write, i32* nocapture %store, i32 %n) local_unnamed_addr #0 {
entry:
%0 = load i32, i32* %read, align 4, !tbaa !6
%cmp10 = icmp sgt i32 %n, 0
br i1 %cmp10, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader: ; preds = %entry
%1 = add i32 %0, 42
store i32 43, i32* %store, align 4, !tbaa !6
br label %for.body
for.cond.cleanup: ; preds = %for.body, %entry
%sum.0.lcssa = phi i32 [ %n, %entry ], [ %div, %for.body ]
store i32 %sum.0.lcssa, i32* %write, align 4, !tbaa !6
ret void
for.body: ; preds = %for.body.preheader, %for.body
%lsr.iv1 = phi i32 [ %1, %for.body.preheader ], [ %lsr.iv.next2, %for.body ]
%lsr.iv = phi i32 [ %n, %for.body.preheader ], [ %lsr.iv.next, %for.body ]
%sum.011 = phi i32 [ %div, %for.body ], [ %n, %for.body.preheader ]
%div = sdiv i32 %sum.011, %lsr.iv1
%lsr.iv.next = add i32 %lsr.iv, -1
%lsr.iv.next2 = add i32 %lsr.iv1, 1
%exitcond.not = icmp eq i32 %lsr.iv.next, 0
br i1 %exitcond.not, label %for.cond.cleanup, label %for.body, !llvm.loop !10
}
define dso_local void @aliased_store_after_add(i32* noalias nocapture readonly %read, i32* noalias nocapture %write, i32* nocapture %store, i32 %n) local_unnamed_addr #0 {
entry:
%0 = load i32, i32* %read, align 4, !tbaa !6
%cmp10 = icmp sgt i32 %n, 0
br i1 %cmp10, label %for.body.preheader, label %for.cond.cleanup
for.body.preheader: ; preds = %entry
%1 = add i32 %0, 42
store i32 43, i32* %read, align 4, !tbaa !6
br label %for.body
for.cond.cleanup: ; preds = %for.body, %entry
%sum.0.lcssa = phi i32 [ %n, %entry ], [ %div, %for.body ]
store i32 %sum.0.lcssa, i32* %write, align 4, !tbaa !6
ret void
for.body: ; preds = %for.body.preheader, %for.body
%lsr.iv1 = phi i32 [ %1, %for.body.preheader ], [ %lsr.iv.next2, %for.body ]
%lsr.iv = phi i32 [ %n, %for.body.preheader ], [ %lsr.iv.next, %for.body ]
%sum.011 = phi i32 [ %div, %for.body ], [ %n, %for.body.preheader ]
%div = sdiv i32 %sum.011, %lsr.iv1
%lsr.iv.next = add i32 %lsr.iv, -1
%lsr.iv.next2 = add i32 %lsr.iv1, 1
%exitcond.not = icmp eq i32 %lsr.iv.next, 0
br i1 %exitcond.not, label %for.cond.cleanup, label %for.body, !llvm.loop !10
}
declare i32 @use(i32)
declare void @_Z6assignPj(i32*)
!6 = !{!7, !7, i64 0}
!7 = !{!"int", !8, i64 0}
!8 = !{!"omnipotent char", !9, i64 0}
!9 = !{!"Simple C/C++ TBAA"}
!10 = distinct !{!10, !11}
!11 = !{!"llvm.loop.mustprogress"}
...
---
name: cant_sink_adds_call_in_block
alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
hasWinCFI: false
registers:
- { id: 0, class: gpr64all, preferred-register: '' }
- { id: 1, class: gpr64all, preferred-register: '' }
- { id: 2, class: gpr64all, preferred-register: '' }
- { id: 3, class: gpr64all, preferred-register: '' }
- { id: 4, class: gpr64all, preferred-register: '' }
- { id: 5, class: gpr64all, preferred-register: '' }
- { id: 6, class: gpr64sp, preferred-register: '' }
- { id: 7, class: gpr64all, preferred-register: '' }
- { id: 8, class: gpr64common, preferred-register: '' }
- { id: 9, class: gpr64common, preferred-register: '' }
- { id: 10, class: gpr64sp, preferred-register: '' }
- { id: 11, class: gpr64sp, preferred-register: '' }
- { id: 12, class: gpr64sp, preferred-register: '' }
- { id: 13, class: gpr64sp, preferred-register: '' }
- { id: 14, class: gpr64sp, preferred-register: '' }
- { id: 15, class: gpr64sp, preferred-register: '' }
- { id: 16, class: gpr64, preferred-register: '' }
- { id: 17, class: gpr32, preferred-register: '' }
- { id: 18, class: gpr32sp, preferred-register: '' }
- { id: 19, class: gpr32, preferred-register: '' }
- { id: 20, class: gpr64common, preferred-register: '' }
- { id: 21, class: gpr64, preferred-register: '' }
- { id: 22, class: gpr64sp, preferred-register: '' }
- { id: 23, class: gpr64sp, preferred-register: '' }
liveins:
- { reg: '$x0', virtual-reg: '%8' }
- { reg: '$x1', virtual-reg: '%9' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 1
adjustsStack: true
hasCalls: true
stackProtector: ''
maxCallFrameSize: 0
cvBytesOfCalleeSavedRegisters: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
fixedStack: []
stack: []
callSites: []
debugValueSubstitutions: []
constants: []
machineFunctionInfo: {}
jumpTable:
kind: block-address
entries:
- id: 0
blocks: [ '%bb.2', '%bb.8', '%bb.8', '%bb.8', '%bb.8', '%bb.8',
'%bb.8', '%bb.8', '%bb.8', '%bb.8', '%bb.3', '%bb.8',
'%bb.8', '%bb.8', '%bb.8', '%bb.8', '%bb.8', '%bb.8',
'%bb.8', '%bb.8', '%bb.4', '%bb.8', '%bb.8', '%bb.8',
'%bb.8', '%bb.8', '%bb.8', '%bb.8', '%bb.8', '%bb.8',
'%bb.5', '%bb.8', '%bb.8', '%bb.8', '%bb.8', '%bb.8',
'%bb.8', '%bb.8', '%bb.8', '%bb.8', '%bb.6', '%bb.8',
'%bb.8', '%bb.8', '%bb.8', '%bb.8', '%bb.8', '%bb.8',
'%bb.8', '%bb.8', '%bb.7' ]
body: |
; CHECK-LABEL: name: cant_sink_adds_call_in_block
; CHECK: bb.0 (%ir-block.0):
; CHECK: successors: %bb.1(0x80000000)
; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:gpr64common = COPY $x1
; CHECK: [[COPY1:%[0-9]+]]:gpr64common = COPY $x0
; CHECK: [[ADDXri:%[0-9]+]]:gpr64sp = nuw ADDXri [[COPY]], 4, 0
; CHECK: [[COPY2:%[0-9]+]]:gpr64all = COPY [[ADDXri]]
; CHECK: [[ADDXri1:%[0-9]+]]:gpr64sp = nuw ADDXri [[COPY]], 8, 0
; CHECK: [[COPY3:%[0-9]+]]:gpr64all = COPY [[ADDXri1]]
; CHECK: [[ADDXri2:%[0-9]+]]:gpr64sp = nuw ADDXri [[COPY]], 12, 0
; CHECK: [[COPY4:%[0-9]+]]:gpr64all = COPY [[ADDXri2]]
; CHECK: [[ADDXri3:%[0-9]+]]:gpr64sp = nuw ADDXri [[COPY]], 16, 0
; CHECK: [[COPY5:%[0-9]+]]:gpr64all = COPY [[ADDXri3]]
; CHECK: [[ADDXri4:%[0-9]+]]:gpr64sp = nuw ADDXri [[COPY]], 20, 0
; CHECK: [[COPY6:%[0-9]+]]:gpr64all = COPY [[ADDXri4]]
; CHECK: [[ADDXri5:%[0-9]+]]:gpr64sp = ADDXri [[COPY1]], 1, 0
; CHECK: [[COPY7:%[0-9]+]]:gpr64all = COPY [[ADDXri5]]
; CHECK: [[MOVaddrJT:%[0-9]+]]:gpr64common = MOVaddrJT target-flags(aarch64-page) %jump-table.0, target-flags(aarch64-pageoff, aarch64-nc) %jump-table.0
; CHECK: bb.1..backedge:
; CHECK: successors: %bb.9(0x09249249), %bb.2(0x76db6db7)
; CHECK: [[PHI:%[0-9]+]]:gpr64sp = PHI [[COPY7]], %bb.0, %7, %bb.9
; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[PHI]], 0 :: (load (s8) from %ir.lsr.iv)
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, killed [[LDRBBui]], %subreg.sub_32
; CHECK: [[COPY8:%[0-9]+]]:gpr32sp = COPY [[SUBREG_TO_REG]].sub_32
; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri killed [[COPY8]], 50, 0, implicit-def $nzcv
; CHECK: Bcc 8, %bb.9, implicit $nzcv
; CHECK: bb.2..backedge:
; CHECK: successors: %bb.3(0x13b13b14), %bb.9(0x09d89d8a), %bb.4(0x13b13b14), %bb.5(0x13b13b14), %bb.6(0x13b13b14), %bb.7(0x13b13b14), %bb.8(0x13b13b14)
; CHECK: early-clobber %21:gpr64, early-clobber %22:gpr64sp = JumpTableDest32 [[MOVaddrJT]], [[SUBREG_TO_REG]], %jump-table.0
; CHECK: BR killed %21
; CHECK: bb.3 (%ir-block.8):
; CHECK: successors: %bb.9(0x80000000)
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
; CHECK: $x0 = COPY [[COPY]]
; CHECK: BL @_Z6assignPj, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
; CHECK: B %bb.9
; CHECK: bb.4 (%ir-block.10):
; CHECK: successors: %bb.9(0x80000000)
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
; CHECK: $x0 = COPY [[COPY2]]
; CHECK: BL @_Z6assignPj, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
; CHECK: B %bb.9
; CHECK: bb.5 (%ir-block.11):
; CHECK: successors: %bb.9(0x80000000)
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
; CHECK: $x0 = COPY [[COPY3]]
; CHECK: BL @_Z6assignPj, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
; CHECK: B %bb.9
; CHECK: bb.6 (%ir-block.12):
; CHECK: successors: %bb.9(0x80000000)
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
; CHECK: $x0 = COPY [[COPY4]]
; CHECK: BL @_Z6assignPj, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
; CHECK: B %bb.9
; CHECK: bb.7 (%ir-block.13):
; CHECK: successors: %bb.9(0x80000000)
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
; CHECK: $x0 = COPY [[COPY5]]
; CHECK: BL @_Z6assignPj, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
; CHECK: B %bb.9
; CHECK: bb.8 (%ir-block.14):
; CHECK: successors: %bb.9(0x80000000)
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
; CHECK: $x0 = COPY [[COPY6]]
; CHECK: BL @_Z6assignPj, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
; CHECK: bb.9..backedge.backedge:
; CHECK: successors: %bb.1(0x80000000)
; CHECK: [[ADDXri6:%[0-9]+]]:gpr64sp = ADDXri [[PHI]], 1, 0
; CHECK: [[COPY9:%[0-9]+]]:gpr64all = COPY [[ADDXri6]]
; CHECK: B %bb.1
bb.0 (%ir-block.0):
successors: %bb.1(0x80000000)
liveins: $x0, $x1
%9:gpr64common = COPY $x1
%8:gpr64common = COPY $x0
%10:gpr64sp = nuw ADDXri %9, 4, 0
%0:gpr64all = COPY %10
%11:gpr64sp = nuw ADDXri %9, 8, 0
%1:gpr64all = COPY %11
%12:gpr64sp = nuw ADDXri %9, 12, 0
%2:gpr64all = COPY %12
%13:gpr64sp = nuw ADDXri %9, 16, 0
%3:gpr64all = COPY %13
%14:gpr64sp = nuw ADDXri %9, 20, 0
%4:gpr64all = COPY %14
%15:gpr64sp = ADDXri %8, 1, 0
%5:gpr64all = COPY %15
%20:gpr64common = MOVaddrJT target-flags(aarch64-page) %jump-table.0, target-flags(aarch64-pageoff, aarch64-nc) %jump-table.0
bb.1..backedge:
successors: %bb.8(0x09249249), %bb.9(0x76db6db7)
%6:gpr64sp = PHI %5, %bb.0, %7, %bb.8
%17:gpr32 = LDRBBui %6, 0 :: (load (s8) from %ir.lsr.iv)
%16:gpr64 = SUBREG_TO_REG 0, killed %17, %subreg.sub_32
%18:gpr32sp = COPY %16.sub_32
%19:gpr32 = SUBSWri killed %18, 50, 0, implicit-def $nzcv
Bcc 8, %bb.8, implicit $nzcv
bb.9..backedge:
successors: %bb.2(0x13b13b14), %bb.8(0x09d89d8a), %bb.3(0x13b13b14), %bb.4(0x13b13b14), %bb.5(0x13b13b14), %bb.6(0x13b13b14), %bb.7(0x13b13b14)
early-clobber %21:gpr64, early-clobber %22:gpr64sp = JumpTableDest32 %20, %16, %jump-table.0
BR killed %21
bb.2 (%ir-block.8):
successors: %bb.8(0x80000000)
ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
$x0 = COPY %9
BL @_Z6assignPj, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp
ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
B %bb.8
bb.3 (%ir-block.10):
successors: %bb.8(0x80000000)
ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
$x0 = COPY %0
BL @_Z6assignPj, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp
ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
B %bb.8
bb.4 (%ir-block.11):
successors: %bb.8(0x80000000)
ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
$x0 = COPY %1
BL @_Z6assignPj, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp
ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
B %bb.8
bb.5 (%ir-block.12):
successors: %bb.8(0x80000000)
ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
$x0 = COPY %2
BL @_Z6assignPj, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp
ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
B %bb.8
bb.6 (%ir-block.13):
successors: %bb.8(0x80000000)
ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
$x0 = COPY %3
BL @_Z6assignPj, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp
ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
B %bb.8
bb.7 (%ir-block.14):
successors: %bb.8(0x80000000)
ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
$x0 = COPY %4
BL @_Z6assignPj, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $x0, implicit-def $sp
ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
bb.8..backedge.backedge:
successors: %bb.1(0x80000000)
%23:gpr64sp = ADDXri %6, 1, 0
%7:gpr64all = COPY %23
B %bb.1
...
---
name: load_not_safe_to_move_consecutive_call
alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
hasWinCFI: false
registers:
- { id: 0, class: gpr32, preferred-register: '' }
- { id: 1, class: gpr32all, preferred-register: '' }
- { id: 2, class: gpr32sp, preferred-register: '' }
- { id: 3, class: gpr32, preferred-register: '' }
- { id: 4, class: gpr32all, preferred-register: '' }
- { id: 5, class: gpr32all, preferred-register: '' }
- { id: 6, class: gpr32common, preferred-register: '' }
- { id: 7, class: gpr32, preferred-register: '' }
- { id: 8, class: gpr64common, preferred-register: '' }
- { id: 9, class: gpr32, preferred-register: '' }
- { id: 10, class: gpr32all, preferred-register: '' }
- { id: 11, class: gpr32, preferred-register: '' }
- { id: 12, class: gpr32, preferred-register: '' }
liveins:
- { reg: '$w0', virtual-reg: '%6' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 1
adjustsStack: true
hasCalls: true
stackProtector: ''
maxCallFrameSize: 0
cvBytesOfCalleeSavedRegisters: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
fixedStack: []
stack: []
callSites: []
debugValueSubstitutions: []
constants: []
machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: load_not_safe_to_move_consecutive_call
; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
; CHECK: liveins: $w0
; CHECK: [[COPY:%[0-9]+]]:gpr32common = COPY $w0
; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def $nzcv
; CHECK: Bcc 11, %bb.2, implicit $nzcv
; CHECK: B %bb.1
; CHECK: bb.1.for.body.preheader:
; CHECK: successors: %bb.3(0x80000000)
; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @A
; CHECK: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui killed [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) @A :: (dereferenceable load (s32) from `i32* getelementptr inbounds ([100 x i32], [100 x i32]* @A, i64 0, i64 0)`)
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
; CHECK: $w0 = COPY [[COPY]]
; CHECK: BL @use, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
; CHECK: B %bb.3
; CHECK: bb.2.for.cond.cleanup:
; CHECK: [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY]], %bb.0, %4, %bb.3
; CHECK: $w0 = COPY [[PHI]]
; CHECK: RET_ReallyLR implicit $w0
; CHECK: bb.3.for.body:
; CHECK: successors: %bb.2(0x04000000), %bb.3(0x7c000000)
; CHECK: [[PHI1:%[0-9]+]]:gpr32sp = PHI [[COPY]], %bb.1, %5, %bb.3
; CHECK: [[PHI2:%[0-9]+]]:gpr32 = PHI [[COPY]], %bb.1, %4, %bb.3
; CHECK: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[PHI2]], [[LDRWui]]
; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SDIVWr]]
; CHECK: [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[PHI1]], 1, 0, implicit-def $nzcv
; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[SUBSWri1]]
; CHECK: Bcc 0, %bb.2, implicit $nzcv
; CHECK: B %bb.3
bb.0.entry:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $w0
%6:gpr32common = COPY $w0
%7:gpr32 = SUBSWri %6, 1, 0, implicit-def $nzcv
Bcc 11, %bb.2, implicit $nzcv
B %bb.1
bb.1.for.body.preheader:
successors: %bb.3(0x80000000)
%8:gpr64common = ADRP target-flags(aarch64-page) @A
%9:gpr32 = LDRWui killed %8, target-flags(aarch64-pageoff, aarch64-nc) @A :: (dereferenceable load (s32) from `i32* getelementptr inbounds ([100 x i32], [100 x i32]* @A, i64 0, i64 0)`)
ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
$w0 = COPY %6
BL @use, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
B %bb.3
bb.2.for.cond.cleanup:
%1:gpr32all = PHI %6, %bb.0, %4, %bb.3
$w0 = COPY %1
RET_ReallyLR implicit $w0
bb.3.for.body:
successors: %bb.2(0x04000000), %bb.3(0x7c000000)
%2:gpr32sp = PHI %6, %bb.1, %5, %bb.3
%3:gpr32 = PHI %6, %bb.1, %4, %bb.3
%11:gpr32 = SDIVWr %3, %9
%4:gpr32all = COPY %11
%12:gpr32 = SUBSWri %2, 1, 0, implicit-def $nzcv
%5:gpr32all = COPY %12
Bcc 0, %bb.2, implicit $nzcv
B %bb.3
...
---
name: load_not_safe_to_move_consecutive_call_use
alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
hasWinCFI: false
registers:
- { id: 0, class: gpr32, preferred-register: '' }
- { id: 1, class: gpr32all, preferred-register: '' }
- { id: 2, class: gpr32sp, preferred-register: '' }
- { id: 3, class: gpr32, preferred-register: '' }
- { id: 4, class: gpr32all, preferred-register: '' }
- { id: 5, class: gpr32all, preferred-register: '' }
- { id: 6, class: gpr32common, preferred-register: '' }
- { id: 7, class: gpr32, preferred-register: '' }
- { id: 8, class: gpr64common, preferred-register: '' }
- { id: 9, class: gpr32, preferred-register: '' }
- { id: 10, class: gpr32all, preferred-register: '' }
- { id: 11, class: gpr32, preferred-register: '' }
- { id: 12, class: gpr32, preferred-register: '' }
liveins:
- { reg: '$w0', virtual-reg: '%6' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 1
adjustsStack: true
hasCalls: true
stackProtector: ''
maxCallFrameSize: 0
cvBytesOfCalleeSavedRegisters: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
fixedStack: []
stack: []
callSites: []
debugValueSubstitutions: []
constants: []
machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: load_not_safe_to_move_consecutive_call_use
; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
; CHECK: liveins: $w0
; CHECK: [[COPY:%[0-9]+]]:gpr32common = COPY $w0
; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def $nzcv
; CHECK: Bcc 11, %bb.2, implicit $nzcv
; CHECK: B %bb.1
; CHECK: bb.1.for.body.preheader:
; CHECK: successors: %bb.3(0x80000000)
; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @A
; CHECK: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui killed [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) @A :: (dereferenceable load (s32) from `i32* getelementptr inbounds ([100 x i32], [100 x i32]* @A, i64 0, i64 0)`)
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
; CHECK: $w0 = COPY [[LDRWui]]
; CHECK: BL @use, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
; CHECK: B %bb.3
; CHECK: bb.2.for.cond.cleanup:
; CHECK: [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY]], %bb.0, %4, %bb.3
; CHECK: $w0 = COPY [[PHI]]
; CHECK: RET_ReallyLR implicit $w0
; CHECK: bb.3.for.body:
; CHECK: successors: %bb.2(0x04000000), %bb.3(0x7c000000)
; CHECK: [[PHI1:%[0-9]+]]:gpr32sp = PHI [[COPY]], %bb.1, %5, %bb.3
; CHECK: [[PHI2:%[0-9]+]]:gpr32 = PHI [[COPY]], %bb.1, %4, %bb.3
; CHECK: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[PHI2]], [[LDRWui]]
; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SDIVWr]]
; CHECK: [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[PHI1]], 1, 0, implicit-def $nzcv
; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[SUBSWri1]]
; CHECK: Bcc 0, %bb.2, implicit $nzcv
; CHECK: B %bb.3
bb.0.entry:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $w0
%6:gpr32common = COPY $w0
%7:gpr32 = SUBSWri %6, 1, 0, implicit-def $nzcv
Bcc 11, %bb.2, implicit $nzcv
B %bb.1
bb.1.for.body.preheader:
successors: %bb.3(0x80000000)
%8:gpr64common = ADRP target-flags(aarch64-page) @A
%9:gpr32 = LDRWui killed %8, target-flags(aarch64-pageoff, aarch64-nc) @A :: (dereferenceable load (s32) from `i32* getelementptr inbounds ([100 x i32], [100 x i32]* @A, i64 0, i64 0)`)
ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
$w0 = COPY %9
BL @use, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
B %bb.3
bb.2.for.cond.cleanup:
%1:gpr32all = PHI %6, %bb.0, %4, %bb.3
$w0 = COPY %1
RET_ReallyLR implicit $w0
bb.3.for.body:
successors: %bb.2(0x04000000), %bb.3(0x7c000000)
%2:gpr32sp = PHI %6, %bb.1, %5, %bb.3
%3:gpr32 = PHI %6, %bb.1, %4, %bb.3
%11:gpr32 = SDIVWr %3, %9
%4:gpr32all = COPY %11
%12:gpr32 = SUBSWri %2, 1, 0, implicit-def $nzcv
%5:gpr32all = COPY %12
Bcc 0, %bb.2, implicit $nzcv
B %bb.3
...
---
name: cant_sink_use_outside_loop
alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
hasWinCFI: false
registers:
- { id: 0, class: gpr32all, preferred-register: '' }
- { id: 1, class: gpr32all, preferred-register: '' }
- { id: 2, class: gpr32all, preferred-register: '' }
- { id: 3, class: gpr32sp, preferred-register: '' }
- { id: 4, class: gpr32all, preferred-register: '' }
- { id: 5, class: gpr32all, preferred-register: '' }
- { id: 6, class: gpr32all, preferred-register: '' }
- { id: 7, class: gpr32common, preferred-register: '' }
- { id: 8, class: gpr32all, preferred-register: '' }
- { id: 9, class: gpr32all, preferred-register: '' }
- { id: 10, class: gpr32, preferred-register: '' }
- { id: 11, class: gpr64common, preferred-register: '' }
- { id: 12, class: gpr32, preferred-register: '' }
- { id: 13, class: gpr32, preferred-register: '' }
- { id: 14, class: gpr32, preferred-register: '' }
- { id: 15, class: gpr32all, preferred-register: '' }
liveins:
- { reg: '$w0', virtual-reg: '%7' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 1
adjustsStack: true
hasCalls: true
stackProtector: ''
maxCallFrameSize: 0
cvBytesOfCalleeSavedRegisters: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
fixedStack: []
stack: []
callSites: []
debugValueSubstitutions: []
constants: []
machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: cant_sink_use_outside_loop
; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x50000000), %bb.4(0x30000000)
; CHECK: liveins: $w0
; CHECK: [[COPY:%[0-9]+]]:gpr32common = COPY $w0
; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def $nzcv
; CHECK: Bcc 10, %bb.1, implicit $nzcv
; CHECK: bb.4:
; CHECK: successors: %bb.2(0x80000000)
; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY $wzr
; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
; CHECK: B %bb.2
; CHECK: bb.1.for.body.preheader:
; CHECK: successors: %bb.3(0x80000000)
; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @A
; CHECK: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui killed [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) @A :: (dereferenceable load (s32) from `i32* getelementptr inbounds ([100 x i32], [100 x i32]* @A, i64 0, i64 0)`)
; CHECK: [[COPY3:%[0-9]+]]:gpr32all = COPY [[LDRWui]]
; CHECK: B %bb.3
; CHECK: bb.2.for.cond.cleanup:
; CHECK: [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY]], %bb.4, %5, %bb.5
; CHECK: [[PHI1:%[0-9]+]]:gpr32all = PHI [[COPY2]], %bb.4, [[COPY3]], %bb.5
; CHECK: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
; CHECK: $w0 = COPY [[PHI1]]
; CHECK: BL @use, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
; CHECK: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
; CHECK: $w0 = COPY [[PHI]]
; CHECK: RET_ReallyLR implicit $w0
; CHECK: bb.3.for.body:
; CHECK: successors: %bb.5(0x04000000), %bb.3(0x7c000000)
; CHECK: [[PHI2:%[0-9]+]]:gpr32sp = PHI [[COPY]], %bb.1, %6, %bb.3
; CHECK: [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[PHI2]], 1, 0, implicit-def $nzcv
; CHECK: [[COPY4:%[0-9]+]]:gpr32all = COPY [[SUBSWri1]]
; CHECK: Bcc 1, %bb.3, implicit $nzcv
; CHECK: bb.5:
; CHECK: successors: %bb.2(0x80000000)
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1
; CHECK: [[COPY5:%[0-9]+]]:gpr32all = COPY [[MOVi32imm]]
; CHECK: B %bb.2
bb.0.entry:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $w0
%7:gpr32common = COPY $w0
%9:gpr32all = COPY $wzr
%8:gpr32all = COPY %9
%10:gpr32 = SUBSWri %7, 1, 0, implicit-def $nzcv
Bcc 11, %bb.2, implicit $nzcv
B %bb.1
bb.1.for.body.preheader:
successors: %bb.3(0x80000000)
%11:gpr64common = ADRP target-flags(aarch64-page) @A
%12:gpr32 = LDRWui killed %11, target-flags(aarch64-pageoff, aarch64-nc) @A :: (dereferenceable load (s32) from `i32* getelementptr inbounds ([100 x i32], [100 x i32]* @A, i64 0, i64 0)`)
%0:gpr32all = COPY %12
B %bb.3
bb.2.for.cond.cleanup:
%1:gpr32all = PHI %7, %bb.0, %5, %bb.3
%2:gpr32all = PHI %8, %bb.0, %0, %bb.3
ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
$w0 = COPY %2
BL @use, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0
ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
$w0 = COPY %1
RET_ReallyLR implicit $w0
bb.3.for.body:
successors: %bb.2(0x04000000), %bb.3(0x7c000000)
%3:gpr32sp = PHI %7, %bb.1, %6, %bb.3
%13:gpr32 = MOVi32imm 1
%5:gpr32all = COPY %13
%14:gpr32 = SUBSWri %3, 1, 0, implicit-def $nzcv
%6:gpr32all = COPY %14
Bcc 0, %bb.2, implicit $nzcv
B %bb.3
...
---
name: use_is_not_a_copy
alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
hasWinCFI: false
registers:
- { id: 0, class: gpr32, preferred-register: '' }
- { id: 1, class: gpr32all, preferred-register: '' }
- { id: 2, class: gpr32sp, preferred-register: '' }
- { id: 3, class: gpr32, preferred-register: '' }
- { id: 4, class: gpr32all, preferred-register: '' }
- { id: 5, class: gpr32all, preferred-register: '' }
- { id: 6, class: gpr32common, preferred-register: '' }
- { id: 7, class: gpr32, preferred-register: '' }
- { id: 8, class: gpr64common, preferred-register: '' }
- { id: 9, class: gpr32, preferred-register: '' }
- { id: 10, class: gpr32, preferred-register: '' }
- { id: 11, class: gpr32, preferred-register: '' }
liveins:
- { reg: '$w0', virtual-reg: '%6' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 1
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 0
cvBytesOfCalleeSavedRegisters: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
fixedStack: []
stack: []
callSites: []
debugValueSubstitutions: []
constants: []
machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: use_is_not_a_copy
; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
; CHECK: liveins: $w0
; CHECK: [[COPY:%[0-9]+]]:gpr32common = COPY $w0
; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def $nzcv
; CHECK: Bcc 11, %bb.2, implicit $nzcv
; CHECK: B %bb.1
; CHECK: bb.1.for.body.preheader:
; CHECK: successors: %bb.3(0x80000000)
; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @A
; CHECK: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui killed [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) @A :: (dereferenceable load (s32) from `i32* getelementptr inbounds ([100 x i32], [100 x i32]* @A, i64 0, i64 0)`)
; CHECK: B %bb.3
; CHECK: bb.2.for.cond.cleanup:
; CHECK: [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY]], %bb.0, %4, %bb.3
; CHECK: $w0 = COPY [[PHI]]
; CHECK: RET_ReallyLR implicit $w0
; CHECK: bb.3.for.body:
; CHECK: successors: %bb.2(0x04000000), %bb.3(0x7c000000)
; CHECK: [[PHI1:%[0-9]+]]:gpr32sp = PHI [[COPY]], %bb.1, %5, %bb.3
; CHECK: [[PHI2:%[0-9]+]]:gpr32 = PHI [[COPY]], %bb.1, %4, %bb.3
; CHECK: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[PHI2]], [[LDRWui]]
; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SDIVWr]]
; CHECK: [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[PHI1]], 1, 0, implicit-def $nzcv
; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[SUBSWri1]]
; CHECK: Bcc 0, %bb.2, implicit $nzcv
; CHECK: B %bb.3
bb.0.entry:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $w0
%6:gpr32common = COPY $w0
%7:gpr32 = SUBSWri %6, 1, 0, implicit-def $nzcv
Bcc 11, %bb.2, implicit $nzcv
B %bb.1
bb.1.for.body.preheader:
successors: %bb.3(0x80000000)
%8:gpr64common = ADRP target-flags(aarch64-page) @A
%9:gpr32 = LDRWui killed %8, target-flags(aarch64-pageoff, aarch64-nc) @A :: (dereferenceable load (s32) from `i32* getelementptr inbounds ([100 x i32], [100 x i32]* @A, i64 0, i64 0)`)
B %bb.3
bb.2.for.cond.cleanup:
%1:gpr32all = PHI %6, %bb.0, %4, %bb.3
$w0 = COPY %1
RET_ReallyLR implicit $w0
bb.3.for.body:
successors: %bb.2(0x04000000), %bb.3(0x7c000000)
%2:gpr32sp = PHI %6, %bb.1, %5, %bb.3
%3:gpr32 = PHI %6, %bb.1, %4, %bb.3
%10:gpr32 = SDIVWr %3, %9
%4:gpr32all = COPY %10
%11:gpr32 = SUBSWri %2, 1, 0, implicit-def $nzcv
%5:gpr32all = COPY %11
Bcc 0, %bb.2, implicit $nzcv
B %bb.3
...
---
name: sink_add
alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
hasWinCFI: false
registers:
- { id: 0, class: gpr32sp, preferred-register: '' }
- { id: 1, class: gpr32all, preferred-register: '' }
- { id: 2, class: gpr32, preferred-register: '' }
- { id: 3, class: gpr32common, preferred-register: '' }
- { id: 4, class: gpr32sp, preferred-register: '' }
- { id: 5, class: gpr32, preferred-register: '' }
- { id: 6, class: gpr32all, preferred-register: '' }
- { id: 7, class: gpr32all, preferred-register: '' }
- { id: 8, class: gpr32all, preferred-register: '' }
- { id: 9, class: gpr64common, preferred-register: '' }
- { id: 10, class: gpr64common, preferred-register: '' }
- { id: 11, class: gpr32common, preferred-register: '' }
- { id: 12, class: gpr32common, preferred-register: '' }
- { id: 13, class: gpr32, preferred-register: '' }
- { id: 14, class: gpr32sp, preferred-register: '' }
- { id: 15, class: gpr32, preferred-register: '' }
- { id: 16, class: gpr32, preferred-register: '' }
- { id: 17, class: gpr32sp, preferred-register: '' }
liveins:
- { reg: '$x0', virtual-reg: '%9' }
- { reg: '$x1', virtual-reg: '%10' }
- { reg: '$w2', virtual-reg: '%11' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 1
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 0
cvBytesOfCalleeSavedRegisters: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
fixedStack: []
stack: []
callSites: []
debugValueSubstitutions: []
constants: []
machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: sink_add
; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
; CHECK: liveins: $x0, $x1, $w2
; CHECK: [[COPY:%[0-9]+]]:gpr32common = COPY $w2
; CHECK: [[COPY1:%[0-9]+]]:gpr64common = COPY $x1
; CHECK: [[COPY2:%[0-9]+]]:gpr64common = COPY $x0
; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def $nzcv
; CHECK: Bcc 11, %bb.2, implicit $nzcv
; CHECK: B %bb.1
; CHECK: bb.1.for.body.preheader:
; CHECK: successors: %bb.3(0x80000000)
; CHECK: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[COPY2]], 0 :: (load (s32) from %ir.read, !tbaa !0)
; CHECK: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[LDRWui]], 42, 0
; CHECK: [[COPY3:%[0-9]+]]:gpr32all = COPY [[ADDWri]]
; CHECK: B %bb.3
; CHECK: bb.2.for.cond.cleanup:
; CHECK: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY]], %bb.0, %6, %bb.3
; CHECK: STRWui [[PHI]], [[COPY1]], 0 :: (store (s32) into %ir.write, !tbaa !0)
; CHECK: RET_ReallyLR
; CHECK: bb.3.for.body:
; CHECK: successors: %bb.2(0x04000000), %bb.3(0x7c000000)
; CHECK: [[PHI1:%[0-9]+]]:gpr32common = PHI [[COPY3]], %bb.1, %8, %bb.3
; CHECK: [[PHI2:%[0-9]+]]:gpr32sp = PHI [[COPY]], %bb.1, %7, %bb.3
; CHECK: [[PHI3:%[0-9]+]]:gpr32 = PHI [[COPY]], %bb.1, %6, %bb.3
; CHECK: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[PHI3]], [[PHI1]]
; CHECK: [[COPY4:%[0-9]+]]:gpr32all = COPY [[SDIVWr]]
; CHECK: [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[PHI2]], 1, 0, implicit-def $nzcv
; CHECK: [[COPY5:%[0-9]+]]:gpr32all = COPY [[SUBSWri1]]
; CHECK: [[ADDWri1:%[0-9]+]]:gpr32sp = ADDWri [[PHI1]], 1, 0
; CHECK: [[COPY6:%[0-9]+]]:gpr32all = COPY [[ADDWri1]]
; CHECK: Bcc 0, %bb.2, implicit $nzcv
; CHECK: B %bb.3
bb.0.entry:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $x0, $x1, $w2
%11:gpr32common = COPY $w2
%10:gpr64common = COPY $x1
%9:gpr64common = COPY $x0
%12:gpr32common = LDRWui %9, 0 :: (load (s32) from %ir.read, !tbaa !6)
%13:gpr32 = SUBSWri %11, 1, 0, implicit-def $nzcv
Bcc 11, %bb.2, implicit $nzcv
B %bb.1
bb.1.for.body.preheader:
successors: %bb.3(0x80000000)
%14:gpr32sp = ADDWri %12, 42, 0
%1:gpr32all = COPY %14
B %bb.3
bb.2.for.cond.cleanup:
%2:gpr32 = PHI %11, %bb.0, %6, %bb.3
STRWui %2, %10, 0 :: (store (s32) into %ir.write, !tbaa !6)
RET_ReallyLR
bb.3.for.body:
successors: %bb.2(0x04000000), %bb.3(0x7c000000)
%3:gpr32common = PHI %1, %bb.1, %8, %bb.3
%4:gpr32sp = PHI %11, %bb.1, %7, %bb.3
%5:gpr32 = PHI %11, %bb.1, %6, %bb.3
%15:gpr32 = SDIVWr %5, %3
%6:gpr32all = COPY %15
%16:gpr32 = SUBSWri %4, 1, 0, implicit-def $nzcv
%7:gpr32all = COPY %16
%17:gpr32sp = ADDWri %3, 1, 0
%8:gpr32all = COPY %17
Bcc 0, %bb.2, implicit $nzcv
B %bb.3
...
---
name: store_after_add
alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
hasWinCFI: false
registers:
- { id: 0, class: gpr32sp, preferred-register: '' }
- { id: 1, class: gpr32all, preferred-register: '' }
- { id: 2, class: gpr32, preferred-register: '' }
- { id: 3, class: gpr32common, preferred-register: '' }
- { id: 4, class: gpr32sp, preferred-register: '' }
- { id: 5, class: gpr32, preferred-register: '' }
- { id: 6, class: gpr32all, preferred-register: '' }
- { id: 7, class: gpr32all, preferred-register: '' }
- { id: 8, class: gpr32all, preferred-register: '' }
- { id: 9, class: gpr64common, preferred-register: '' }
- { id: 10, class: gpr64common, preferred-register: '' }
- { id: 11, class: gpr64common, preferred-register: '' }
- { id: 12, class: gpr32common, preferred-register: '' }
- { id: 13, class: gpr32common, preferred-register: '' }
- { id: 14, class: gpr32, preferred-register: '' }
- { id: 15, class: gpr32, preferred-register: '' }
- { id: 16, class: gpr32sp, preferred-register: '' }
- { id: 17, class: gpr32, preferred-register: '' }
- { id: 18, class: gpr32, preferred-register: '' }
- { id: 19, class: gpr32sp, preferred-register: '' }
liveins:
- { reg: '$x0', virtual-reg: '%9' }
- { reg: '$x1', virtual-reg: '%10' }
- { reg: '$x2', virtual-reg: '%11' }
- { reg: '$w3', virtual-reg: '%12' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 1
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 0
cvBytesOfCalleeSavedRegisters: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
fixedStack: []
stack: []
callSites: []
debugValueSubstitutions: []
constants: []
machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: store_after_add
; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
; CHECK: liveins: $x0, $x1, $x2, $w3
; CHECK: [[COPY:%[0-9]+]]:gpr32common = COPY $w3
; CHECK: [[COPY1:%[0-9]+]]:gpr64common = COPY $x2
; CHECK: [[COPY2:%[0-9]+]]:gpr64common = COPY $x1
; CHECK: [[COPY3:%[0-9]+]]:gpr64common = COPY $x0
; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def $nzcv
; CHECK: Bcc 11, %bb.2, implicit $nzcv
; CHECK: B %bb.1
; CHECK: bb.1.for.body.preheader:
; CHECK: successors: %bb.3(0x80000000)
; CHECK: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[COPY3]], 0 :: (load (s32) from %ir.read, !tbaa !0)
; CHECK: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[LDRWui]], 42, 0
; CHECK: [[COPY4:%[0-9]+]]:gpr32all = COPY [[ADDWri]]
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 43
; CHECK: STRWui killed [[MOVi32imm]], [[COPY1]], 0 :: (store (s32) into %ir.store, !tbaa !0)
; CHECK: B %bb.3
; CHECK: bb.2.for.cond.cleanup:
; CHECK: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY]], %bb.0, %6, %bb.3
; CHECK: STRWui [[PHI]], [[COPY2]], 0 :: (store (s32) into %ir.write, !tbaa !0)
; CHECK: RET_ReallyLR
; CHECK: bb.3.for.body:
; CHECK: successors: %bb.2(0x04000000), %bb.3(0x7c000000)
; CHECK: [[PHI1:%[0-9]+]]:gpr32common = PHI [[COPY4]], %bb.1, %8, %bb.3
; CHECK: [[PHI2:%[0-9]+]]:gpr32sp = PHI [[COPY]], %bb.1, %7, %bb.3
; CHECK: [[PHI3:%[0-9]+]]:gpr32 = PHI [[COPY]], %bb.1, %6, %bb.3
; CHECK: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[PHI3]], [[PHI1]]
; CHECK: [[COPY5:%[0-9]+]]:gpr32all = COPY [[SDIVWr]]
; CHECK: [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[PHI2]], 1, 0, implicit-def $nzcv
; CHECK: [[COPY6:%[0-9]+]]:gpr32all = COPY [[SUBSWri1]]
; CHECK: [[ADDWri1:%[0-9]+]]:gpr32sp = ADDWri [[PHI1]], 1, 0
; CHECK: [[COPY7:%[0-9]+]]:gpr32all = COPY [[ADDWri1]]
; CHECK: Bcc 0, %bb.2, implicit $nzcv
; CHECK: B %bb.3
bb.0.entry:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $x0, $x1, $x2, $w3
%12:gpr32common = COPY $w3
%11:gpr64common = COPY $x2
%10:gpr64common = COPY $x1
%9:gpr64common = COPY $x0
%13:gpr32common = LDRWui %9, 0 :: (load (s32) from %ir.read, !tbaa !6)
%15:gpr32 = SUBSWri %12, 1, 0, implicit-def $nzcv
Bcc 11, %bb.2, implicit $nzcv
B %bb.1
bb.1.for.body.preheader:
successors: %bb.3(0x80000000)
%16:gpr32sp = ADDWri %13, 42, 0
%1:gpr32all = COPY %16
%14:gpr32 = MOVi32imm 43
STRWui killed %14, %11, 0 :: (store (s32) into %ir.store, !tbaa !6)
B %bb.3
bb.2.for.cond.cleanup:
%2:gpr32 = PHI %12, %bb.0, %6, %bb.3
STRWui %2, %10, 0 :: (store (s32) into %ir.write, !tbaa !6)
RET_ReallyLR
bb.3.for.body:
successors: %bb.2(0x04000000), %bb.3(0x7c000000)
%3:gpr32common = PHI %1, %bb.1, %8, %bb.3
%4:gpr32sp = PHI %12, %bb.1, %7, %bb.3
%5:gpr32 = PHI %12, %bb.1, %6, %bb.3
%17:gpr32 = SDIVWr %5, %3
%6:gpr32all = COPY %17
%18:gpr32 = SUBSWri %4, 1, 0, implicit-def $nzcv
%7:gpr32all = COPY %18
%19:gpr32sp = ADDWri %3, 1, 0
%8:gpr32all = COPY %19
Bcc 0, %bb.2, implicit $nzcv
B %bb.3
...
---
name: aliased_store_after_add
alignment: 16
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
hasWinCFI: false
registers:
- { id: 0, class: gpr32sp, preferred-register: '' }
- { id: 1, class: gpr32all, preferred-register: '' }
- { id: 2, class: gpr32, preferred-register: '' }
- { id: 3, class: gpr32common, preferred-register: '' }
- { id: 4, class: gpr32sp, preferred-register: '' }
- { id: 5, class: gpr32, preferred-register: '' }
- { id: 6, class: gpr32all, preferred-register: '' }
- { id: 7, class: gpr32all, preferred-register: '' }
- { id: 8, class: gpr32all, preferred-register: '' }
- { id: 9, class: gpr64common, preferred-register: '' }
- { id: 10, class: gpr64common, preferred-register: '' }
- { id: 11, class: gpr64common, preferred-register: '' }
- { id: 12, class: gpr32common, preferred-register: '' }
- { id: 13, class: gpr32common, preferred-register: '' }
- { id: 14, class: gpr32, preferred-register: '' }
- { id: 15, class: gpr32, preferred-register: '' }
- { id: 16, class: gpr32sp, preferred-register: '' }
- { id: 17, class: gpr32, preferred-register: '' }
- { id: 18, class: gpr32, preferred-register: '' }
- { id: 19, class: gpr32sp, preferred-register: '' }
liveins:
- { reg: '$x0', virtual-reg: '%9' }
- { reg: '$x1', virtual-reg: '%10' }
- { reg: '$x2', virtual-reg: '%11' }
- { reg: '$w3', virtual-reg: '%12' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 1
adjustsStack: false
hasCalls: false
stackProtector: ''
maxCallFrameSize: 0
cvBytesOfCalleeSavedRegisters: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
fixedStack: []
stack: []
callSites: []
debugValueSubstitutions: []
constants: []
machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: aliased_store_after_add
; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x50000000), %bb.2(0x30000000)
; CHECK: liveins: $x0, $x1, $x2, $w3
; CHECK: [[COPY:%[0-9]+]]:gpr32common = COPY $w3
; CHECK: [[COPY1:%[0-9]+]]:gpr64common = COPY $x2
; CHECK: [[COPY2:%[0-9]+]]:gpr64common = COPY $x1
; CHECK: [[COPY3:%[0-9]+]]:gpr64common = COPY $x0
; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def $nzcv
; CHECK: Bcc 11, %bb.2, implicit $nzcv
; CHECK: B %bb.1
; CHECK: bb.1.for.body.preheader:
; CHECK: successors: %bb.3(0x80000000)
; CHECK: [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[COPY3]], 0 :: (load (s32) from %ir.read, !tbaa !0)
; CHECK: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[LDRWui]], 42, 0
; CHECK: [[COPY4:%[0-9]+]]:gpr32all = COPY [[ADDWri]]
; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 43
; CHECK: STRWui killed [[MOVi32imm]], [[COPY3]], 0 :: (store (s32) into %ir.read, !tbaa !0)
; CHECK: B %bb.3
; CHECK: bb.2.for.cond.cleanup:
; CHECK: [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY]], %bb.0, %6, %bb.3
; CHECK: STRWui [[PHI]], [[COPY2]], 0 :: (store (s32) into %ir.write, !tbaa !0)
; CHECK: RET_ReallyLR
; CHECK: bb.3.for.body:
; CHECK: successors: %bb.2(0x04000000), %bb.3(0x7c000000)
; CHECK: [[PHI1:%[0-9]+]]:gpr32common = PHI [[COPY4]], %bb.1, %8, %bb.3
; CHECK: [[PHI2:%[0-9]+]]:gpr32sp = PHI [[COPY]], %bb.1, %7, %bb.3
; CHECK: [[PHI3:%[0-9]+]]:gpr32 = PHI [[COPY]], %bb.1, %6, %bb.3
; CHECK: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[PHI3]], [[PHI1]]
; CHECK: [[COPY5:%[0-9]+]]:gpr32all = COPY [[SDIVWr]]
; CHECK: [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[PHI2]], 1, 0, implicit-def $nzcv
; CHECK: [[COPY6:%[0-9]+]]:gpr32all = COPY [[SUBSWri1]]
; CHECK: [[ADDWri1:%[0-9]+]]:gpr32sp = ADDWri [[PHI1]], 1, 0
; CHECK: [[COPY7:%[0-9]+]]:gpr32all = COPY [[ADDWri1]]
; CHECK: Bcc 0, %bb.2, implicit $nzcv
; CHECK: B %bb.3
bb.0.entry:
successors: %bb.1(0x50000000), %bb.2(0x30000000)
liveins: $x0, $x1, $x2, $w3
%12:gpr32common = COPY $w3
%11:gpr64common = COPY $x2
%10:gpr64common = COPY $x1
%9:gpr64common = COPY $x0
%13:gpr32common = LDRWui %9, 0 :: (load (s32) from %ir.read, !tbaa !6)
%15:gpr32 = SUBSWri %12, 1, 0, implicit-def $nzcv
Bcc 11, %bb.2, implicit $nzcv
B %bb.1
bb.1.for.body.preheader:
successors: %bb.3(0x80000000)
%16:gpr32sp = ADDWri %13, 42, 0
%1:gpr32all = COPY %16
%14:gpr32 = MOVi32imm 43
STRWui killed %14, %9, 0 :: (store (s32) into %ir.read, !tbaa !6)
B %bb.3
bb.2.for.cond.cleanup:
%2:gpr32 = PHI %12, %bb.0, %6, %bb.3
STRWui %2, %10, 0 :: (store (s32) into %ir.write, !tbaa !6)
RET_ReallyLR
bb.3.for.body:
successors: %bb.2(0x04000000), %bb.3(0x7c000000)
%3:gpr32common = PHI %1, %bb.1, %8, %bb.3
%4:gpr32sp = PHI %12, %bb.1, %7, %bb.3
%5:gpr32 = PHI %12, %bb.1, %6, %bb.3
%17:gpr32 = SDIVWr %5, %3
%6:gpr32all = COPY %17
%18:gpr32 = SUBSWri %4, 1, 0, implicit-def $nzcv
%7:gpr32all = COPY %18
%19:gpr32sp = ADDWri %3, 1, 0
%8:gpr32all = COPY %19
Bcc 0, %bb.2, implicit $nzcv
B %bb.3
...