# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -mcpu=mips32r6 -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32R6
--- |
%struct.MemSize3_Align1 = type { [3 x i8], i8 }
%struct.MemSize3_Align2 = type { [3 x i8], i8 }
%struct.MemSize3_Align4 = type { [3 x i8], i8 }
%struct.MemSize3_Align8 = type { [3 x i8], i8, [4 x i8] }
%struct.MemSize5_Align1 = type <{ [5 x i8], i16, i8 }>
%struct.MemSize5_Align2 = type <{ [5 x i8], i16, i8 }>
%struct.MemSize5_Align4 = type <{ [5 x i8], i16, i8 }>
%struct.MemSize5_Align8 = type <{ [5 x i8], i16, i8 }>
%struct.MemSize6_Align1 = type { [6 x i8], i16 }
%struct.MemSize6_Align2 = type { [6 x i8], i16 }
%struct.MemSize6_Align4 = type { [6 x i8], i16 }
%struct.MemSize6_Align8 = type { [6 x i8], i16 }
%struct.MemSize7_Align1 = type { [7 x i8], i8 }
%struct.MemSize7_Align2 = type { [7 x i8], i8 }
%struct.MemSize7_Align4 = type { [7 x i8], i8 }
%struct.MemSize7_Align8 = type { [7 x i8], i8 }
@double_align1 = common global double 0.000000e+00, align 1
@double_align2 = common global double 0.000000e+00, align 2
@double_align4 = common global double 0.000000e+00, align 4
@double_align8 = common global double 0.000000e+00, align 8
@i64_align1 = common global i64 0, align 1
@i64_align2 = common global i64 0, align 2
@i64_align4 = common global i64 0, align 4
@i64_align8 = common global i64 0, align 8
define i32 @load3align1(%struct.MemSize3_Align1* %S) {
entry:
%0 = bitcast %struct.MemSize3_Align1* %S to i24*
%bf.load = load i24, i24* %0, align 1
%bf.cast = zext i24 %bf.load to i32
ret i32 %bf.cast
}
define i32 @load3align2(%struct.MemSize3_Align2* %S) {
entry:
%0 = bitcast %struct.MemSize3_Align2* %S to i24*
%bf.load = load i24, i24* %0, align 2
%bf.cast = zext i24 %bf.load to i32
ret i32 %bf.cast
}
define i32 @load3align4(%struct.MemSize3_Align4* %S, i32 signext %a) {
entry:
%0 = bitcast %struct.MemSize3_Align4* %S to i24*
%bf.load = load i24, i24* %0, align 4
%bf.cast = zext i24 %bf.load to i32
ret i32 %bf.cast
}
define i32 @load3align8(%struct.MemSize3_Align8* %S, i32 signext %a) {
entry:
%0 = bitcast %struct.MemSize3_Align8* %S to i24*
%bf.load = load i24, i24* %0, align 8
%bf.cast = zext i24 %bf.load to i32
ret i32 %bf.cast
}
define i64 @load5align1(%struct.MemSize5_Align1* %S) {
entry:
%0 = bitcast %struct.MemSize5_Align1* %S to i40*
%bf.load = load i40, i40* %0, align 1
%bf.cast = zext i40 %bf.load to i64
ret i64 %bf.cast
}
define i64 @load5align2(%struct.MemSize5_Align2* %S) {
entry:
%0 = bitcast %struct.MemSize5_Align2* %S to i40*
%bf.load = load i40, i40* %0, align 2
%bf.cast = zext i40 %bf.load to i64
ret i64 %bf.cast
}
define i64 @load5align4(%struct.MemSize5_Align4* %S) {
entry:
%0 = bitcast %struct.MemSize5_Align4* %S to i40*
%bf.load = load i40, i40* %0, align 4
%bf.cast = zext i40 %bf.load to i64
ret i64 %bf.cast
}
define i64 @load5align8(%struct.MemSize5_Align8* %S) {
entry:
%0 = bitcast %struct.MemSize5_Align8* %S to i40*
%bf.load = load i40, i40* %0, align 8
%bf.cast = zext i40 %bf.load to i64
ret i64 %bf.cast
}
define i64 @load6align1(%struct.MemSize6_Align1* %S) {
entry:
%0 = bitcast %struct.MemSize6_Align1* %S to i48*
%bf.load = load i48, i48* %0, align 1
%bf.cast = zext i48 %bf.load to i64
ret i64 %bf.cast
}
define i64 @load6align2(%struct.MemSize6_Align2* %S) {
entry:
%0 = bitcast %struct.MemSize6_Align2* %S to i48*
%bf.load = load i48, i48* %0, align 2
%bf.cast = zext i48 %bf.load to i64
ret i64 %bf.cast
}
define i64 @load6align4(%struct.MemSize6_Align4* %S) {
entry:
%0 = bitcast %struct.MemSize6_Align4* %S to i48*
%bf.load = load i48, i48* %0, align 4
%bf.cast = zext i48 %bf.load to i64
ret i64 %bf.cast
}
define i64 @load6align8(%struct.MemSize6_Align8* %S) {
entry:
%0 = bitcast %struct.MemSize6_Align8* %S to i48*
%bf.load = load i48, i48* %0, align 8
%bf.cast = zext i48 %bf.load to i64
ret i64 %bf.cast
}
define i64 @load7align1(%struct.MemSize7_Align1* %S) {
entry:
%0 = bitcast %struct.MemSize7_Align1* %S to i56*
%bf.load = load i56, i56* %0, align 1
%bf.cast = zext i56 %bf.load to i64
ret i64 %bf.cast
}
define i64 @load7align2(%struct.MemSize7_Align2* %S) {
entry:
%0 = bitcast %struct.MemSize7_Align2* %S to i56*
%bf.load = load i56, i56* %0, align 2
%bf.cast = zext i56 %bf.load to i64
ret i64 %bf.cast
}
define i64 @load7align4(%struct.MemSize7_Align4* %S) {
entry:
%0 = bitcast %struct.MemSize7_Align4* %S to i56*
%bf.load = load i56, i56* %0, align 4
%bf.cast = zext i56 %bf.load to i64
ret i64 %bf.cast
}
define i64 @load7align8(%struct.MemSize7_Align8* %S) {
entry:
%0 = bitcast %struct.MemSize7_Align8* %S to i56*
%bf.load = load i56, i56* %0, align 8
%bf.cast = zext i56 %bf.load to i64
ret i64 %bf.cast
}
define double @load_double_align1() {
entry:
%0 = load double, double* @double_align1, align 1
ret double %0
}
define double @load_double_align2() {
entry:
%0 = load double, double* @double_align2, align 2
ret double %0
}
define double @load_double_align4() {
entry:
%0 = load double, double* @double_align4, align 4
ret double %0
}
define double @load_double_align8() {
entry:
%0 = load double, double* @double_align8, align 8
ret double %0
}
define i64 @load_i64_align1() {
entry:
%0 = load i64, i64* @i64_align1, align 1
ret i64 %0
}
define i64 @load_i64_align2() {
entry:
%0 = load i64, i64* @i64_align2, align 2
ret i64 %0
}
define i64 @load_i64_align4() {
entry:
%0 = load i64, i64* @i64_align4, align 4
ret i64 %0
}
define i64 @load_i64_align8() {
entry:
%0 = load i64, i64* @i64_align8, align 8
ret i64 %0
}
...
---
name: load3align1
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0
; MIPS32-LABEL: name: load3align1
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.0, align 1)
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; MIPS32: $v0 = COPY [[AND]](s32)
; MIPS32: RetRA implicit $v0
; MIPS32R6-LABEL: name: load3align1
; MIPS32R6: liveins: $a0
; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.0, align 1)
; MIPS32R6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
; MIPS32R6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; MIPS32R6: $v0 = COPY [[AND]](s32)
; MIPS32R6: RetRA implicit $v0
%0:_(p0) = COPY $a0
%1:_(s24) = G_LOAD %0(p0) :: (load 3 from %ir.0, align 1)
%2:_(s32) = G_ZEXT %1(s24)
$v0 = COPY %2(s32)
RetRA implicit $v0
...
---
name: load3align2
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0
; MIPS32-LABEL: name: load3align2
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.0, align 2)
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; MIPS32: $v0 = COPY [[AND]](s32)
; MIPS32: RetRA implicit $v0
; MIPS32R6-LABEL: name: load3align2
; MIPS32R6: liveins: $a0
; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.0, align 2)
; MIPS32R6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
; MIPS32R6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; MIPS32R6: $v0 = COPY [[AND]](s32)
; MIPS32R6: RetRA implicit $v0
%0:_(p0) = COPY $a0
%1:_(s24) = G_LOAD %0(p0) :: (load 3 from %ir.0, align 2)
%2:_(s32) = G_ZEXT %1(s24)
$v0 = COPY %2(s32)
RetRA implicit $v0
...
---
name: load3align4
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1
; MIPS32-LABEL: name: load3align4
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.0)
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; MIPS32: $v0 = COPY [[AND]](s32)
; MIPS32: RetRA implicit $v0
; MIPS32R6-LABEL: name: load3align4
; MIPS32R6: liveins: $a0, $a1
; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.0)
; MIPS32R6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
; MIPS32R6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; MIPS32R6: $v0 = COPY [[AND]](s32)
; MIPS32R6: RetRA implicit $v0
%0:_(p0) = COPY $a0
%2:_(s24) = G_LOAD %0(p0) :: (load 3 from %ir.0, align 4)
%3:_(s32) = G_ZEXT %2(s24)
$v0 = COPY %3(s32)
RetRA implicit $v0
...
---
name: load3align8
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0, $a1
; MIPS32-LABEL: name: load3align8
; MIPS32: liveins: $a0, $a1
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.0, align 8)
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; MIPS32: $v0 = COPY [[AND]](s32)
; MIPS32: RetRA implicit $v0
; MIPS32R6-LABEL: name: load3align8
; MIPS32R6: liveins: $a0, $a1
; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.0, align 8)
; MIPS32R6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; MIPS32R6: [[COPY1:%[0-9]+]]:_(s32) = COPY [[LOAD]](s32)
; MIPS32R6: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
; MIPS32R6: $v0 = COPY [[AND]](s32)
; MIPS32R6: RetRA implicit $v0
%0:_(p0) = COPY $a0
%2:_(s24) = G_LOAD %0(p0) :: (load 3 from %ir.0, align 8)
%3:_(s32) = G_ZEXT %2(s24)
$v0 = COPY %3(s32)
RetRA implicit $v0
...
---
name: load5align1
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0
; MIPS32-LABEL: name: load5align1
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.0, align 1)
; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load 1 from %ir.0 + 4)
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[AND1]](s32)
; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
; MIPS32: $v0 = COPY [[UV]](s32)
; MIPS32: $v1 = COPY [[UV1]](s32)
; MIPS32: RetRA implicit $v0, implicit $v1
; MIPS32R6-LABEL: name: load5align1
; MIPS32R6: liveins: $a0
; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32R6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32R6: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.0, align 1)
; MIPS32R6: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load 1 from %ir.0 + 4)
; MIPS32R6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; MIPS32R6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; MIPS32R6: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
; MIPS32R6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
; MIPS32R6: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[AND1]](s32)
; MIPS32R6: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
; MIPS32R6: $v0 = COPY [[UV]](s32)
; MIPS32R6: $v1 = COPY [[UV1]](s32)
; MIPS32R6: RetRA implicit $v0, implicit $v1
%0:_(p0) = COPY $a0
%1:_(s40) = G_LOAD %0(p0) :: (load 5 from %ir.0, align 1)
%2:_(s64) = G_ZEXT %1(s40)
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
$v0 = COPY %3(s32)
$v1 = COPY %4(s32)
RetRA implicit $v0, implicit $v1
...
---
name: load5align2
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0
; MIPS32-LABEL: name: load5align2
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.0, align 2)
; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load 1 from %ir.0 + 4, align 2)
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[AND1]](s32)
; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
; MIPS32: $v0 = COPY [[UV]](s32)
; MIPS32: $v1 = COPY [[UV1]](s32)
; MIPS32: RetRA implicit $v0, implicit $v1
; MIPS32R6-LABEL: name: load5align2
; MIPS32R6: liveins: $a0
; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32R6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32R6: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.0, align 2)
; MIPS32R6: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load 1 from %ir.0 + 4, align 2)
; MIPS32R6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; MIPS32R6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; MIPS32R6: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
; MIPS32R6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
; MIPS32R6: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[AND1]](s32)
; MIPS32R6: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
; MIPS32R6: $v0 = COPY [[UV]](s32)
; MIPS32R6: $v1 = COPY [[UV1]](s32)
; MIPS32R6: RetRA implicit $v0, implicit $v1
%0:_(p0) = COPY $a0
%1:_(s40) = G_LOAD %0(p0) :: (load 5 from %ir.0, align 2)
%2:_(s64) = G_ZEXT %1(s40)
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
$v0 = COPY %3(s32)
$v1 = COPY %4(s32)
RetRA implicit $v0, implicit $v1
...
---
name: load5align4
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0
; MIPS32-LABEL: name: load5align4
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.0)
; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load 1 from %ir.0 + 4, align 4)
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[AND1]](s32)
; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
; MIPS32: $v0 = COPY [[UV]](s32)
; MIPS32: $v1 = COPY [[UV1]](s32)
; MIPS32: RetRA implicit $v0, implicit $v1
; MIPS32R6-LABEL: name: load5align4
; MIPS32R6: liveins: $a0
; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32R6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32R6: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.0)
; MIPS32R6: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load 1 from %ir.0 + 4, align 4)
; MIPS32R6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; MIPS32R6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; MIPS32R6: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
; MIPS32R6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
; MIPS32R6: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[AND1]](s32)
; MIPS32R6: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
; MIPS32R6: $v0 = COPY [[UV]](s32)
; MIPS32R6: $v1 = COPY [[UV1]](s32)
; MIPS32R6: RetRA implicit $v0, implicit $v1
%0:_(p0) = COPY $a0
%1:_(s40) = G_LOAD %0(p0) :: (load 5 from %ir.0, align 4)
%2:_(s64) = G_ZEXT %1(s40)
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
$v0 = COPY %3(s32)
$v1 = COPY %4(s32)
RetRA implicit $v0, implicit $v1
...
---
name: load5align8
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0
; MIPS32-LABEL: name: load5align8
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.0, align 8)
; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load 1 from %ir.0 + 4, align 8)
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[AND1]](s32)
; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
; MIPS32: $v0 = COPY [[UV]](s32)
; MIPS32: $v1 = COPY [[UV1]](s32)
; MIPS32: RetRA implicit $v0, implicit $v1
; MIPS32R6-LABEL: name: load5align8
; MIPS32R6: liveins: $a0
; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32R6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32R6: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.0, align 8)
; MIPS32R6: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load 1 from %ir.0 + 4, align 8)
; MIPS32R6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; MIPS32R6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
; MIPS32R6: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
; MIPS32R6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
; MIPS32R6: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[AND1]](s32)
; MIPS32R6: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
; MIPS32R6: $v0 = COPY [[UV]](s32)
; MIPS32R6: $v1 = COPY [[UV1]](s32)
; MIPS32R6: RetRA implicit $v0, implicit $v1
%0:_(p0) = COPY $a0
%1:_(s40) = G_LOAD %0(p0) :: (load 5 from %ir.0, align 8)
%2:_(s64) = G_ZEXT %1(s40)
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
$v0 = COPY %3(s32)
$v1 = COPY %4(s32)
RetRA implicit $v0, implicit $v1
...
---
name: load6align1
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0
; MIPS32-LABEL: name: load6align1
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.0, align 1)
; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load 4 from %ir.0 + 4, align 1)
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[AND1]](s32)
; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
; MIPS32: $v0 = COPY [[UV]](s32)
; MIPS32: $v1 = COPY [[UV1]](s32)
; MIPS32: RetRA implicit $v0, implicit $v1
; MIPS32R6-LABEL: name: load6align1
; MIPS32R6: liveins: $a0
; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32R6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32R6: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.0, align 1)
; MIPS32R6: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load 2 from %ir.0 + 4, align 1)
; MIPS32R6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; MIPS32R6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; MIPS32R6: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
; MIPS32R6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
; MIPS32R6: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[AND1]](s32)
; MIPS32R6: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
; MIPS32R6: $v0 = COPY [[UV]](s32)
; MIPS32R6: $v1 = COPY [[UV1]](s32)
; MIPS32R6: RetRA implicit $v0, implicit $v1
%0:_(p0) = COPY $a0
%1:_(s48) = G_LOAD %0(p0) :: (load 6 from %ir.0, align 1)
%2:_(s64) = G_ZEXT %1(s48)
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
$v0 = COPY %3(s32)
$v1 = COPY %4(s32)
RetRA implicit $v0, implicit $v1
...
---
name: load6align2
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0
; MIPS32-LABEL: name: load6align2
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.0, align 2)
; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load 2 from %ir.0 + 4)
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[AND1]](s32)
; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
; MIPS32: $v0 = COPY [[UV]](s32)
; MIPS32: $v1 = COPY [[UV1]](s32)
; MIPS32: RetRA implicit $v0, implicit $v1
; MIPS32R6-LABEL: name: load6align2
; MIPS32R6: liveins: $a0
; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32R6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32R6: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.0, align 2)
; MIPS32R6: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load 2 from %ir.0 + 4)
; MIPS32R6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; MIPS32R6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; MIPS32R6: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
; MIPS32R6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
; MIPS32R6: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[AND1]](s32)
; MIPS32R6: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
; MIPS32R6: $v0 = COPY [[UV]](s32)
; MIPS32R6: $v1 = COPY [[UV1]](s32)
; MIPS32R6: RetRA implicit $v0, implicit $v1
%0:_(p0) = COPY $a0
%1:_(s48) = G_LOAD %0(p0) :: (load 6 from %ir.0, align 2)
%2:_(s64) = G_ZEXT %1(s48)
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
$v0 = COPY %3(s32)
$v1 = COPY %4(s32)
RetRA implicit $v0, implicit $v1
...
---
name: load6align4
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0
; MIPS32-LABEL: name: load6align4
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.0)
; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load 2 from %ir.0 + 4, align 4)
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[AND1]](s32)
; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
; MIPS32: $v0 = COPY [[UV]](s32)
; MIPS32: $v1 = COPY [[UV1]](s32)
; MIPS32: RetRA implicit $v0, implicit $v1
; MIPS32R6-LABEL: name: load6align4
; MIPS32R6: liveins: $a0
; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32R6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32R6: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.0)
; MIPS32R6: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load 2 from %ir.0 + 4, align 4)
; MIPS32R6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; MIPS32R6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; MIPS32R6: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
; MIPS32R6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
; MIPS32R6: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[AND1]](s32)
; MIPS32R6: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
; MIPS32R6: $v0 = COPY [[UV]](s32)
; MIPS32R6: $v1 = COPY [[UV1]](s32)
; MIPS32R6: RetRA implicit $v0, implicit $v1
%0:_(p0) = COPY $a0
%1:_(s48) = G_LOAD %0(p0) :: (load 6 from %ir.0, align 4)
%2:_(s64) = G_ZEXT %1(s48)
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
$v0 = COPY %3(s32)
$v1 = COPY %4(s32)
RetRA implicit $v0, implicit $v1
...
---
name: load6align8
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0
; MIPS32-LABEL: name: load6align8
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.0, align 8)
; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load 2 from %ir.0 + 4, align 8)
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[AND1]](s32)
; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
; MIPS32: $v0 = COPY [[UV]](s32)
; MIPS32: $v1 = COPY [[UV1]](s32)
; MIPS32: RetRA implicit $v0, implicit $v1
; MIPS32R6-LABEL: name: load6align8
; MIPS32R6: liveins: $a0
; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32R6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32R6: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.0, align 8)
; MIPS32R6: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load 2 from %ir.0 + 4, align 8)
; MIPS32R6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; MIPS32R6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
; MIPS32R6: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
; MIPS32R6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
; MIPS32R6: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[AND1]](s32)
; MIPS32R6: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
; MIPS32R6: $v0 = COPY [[UV]](s32)
; MIPS32R6: $v1 = COPY [[UV1]](s32)
; MIPS32R6: RetRA implicit $v0, implicit $v1
%0:_(p0) = COPY $a0
%1:_(s48) = G_LOAD %0(p0) :: (load 6 from %ir.0, align 8)
%2:_(s64) = G_ZEXT %1(s48)
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
$v0 = COPY %3(s32)
$v1 = COPY %4(s32)
RetRA implicit $v0, implicit $v1
...
---
name: load7align1
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0
; MIPS32-LABEL: name: load7align1
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.0, align 1)
; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load 4 from %ir.0 + 4, align 1)
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[AND1]](s32)
; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
; MIPS32: $v0 = COPY [[UV]](s32)
; MIPS32: $v1 = COPY [[UV1]](s32)
; MIPS32: RetRA implicit $v0, implicit $v1
; MIPS32R6-LABEL: name: load7align1
; MIPS32R6: liveins: $a0
; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32R6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32R6: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.0, align 1)
; MIPS32R6: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load 4 from %ir.0 + 4, align 1)
; MIPS32R6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; MIPS32R6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; MIPS32R6: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
; MIPS32R6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
; MIPS32R6: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[AND1]](s32)
; MIPS32R6: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
; MIPS32R6: $v0 = COPY [[UV]](s32)
; MIPS32R6: $v1 = COPY [[UV1]](s32)
; MIPS32R6: RetRA implicit $v0, implicit $v1
%0:_(p0) = COPY $a0
%1:_(s56) = G_LOAD %0(p0) :: (load 7 from %ir.0, align 1)
%2:_(s64) = G_ZEXT %1(s56)
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
$v0 = COPY %3(s32)
$v1 = COPY %4(s32)
RetRA implicit $v0, implicit $v1
...
---
name: load7align2
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0
; MIPS32-LABEL: name: load7align2
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.0, align 2)
; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load 4 from %ir.0 + 4, align 2)
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[AND1]](s32)
; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
; MIPS32: $v0 = COPY [[UV]](s32)
; MIPS32: $v1 = COPY [[UV1]](s32)
; MIPS32: RetRA implicit $v0, implicit $v1
; MIPS32R6-LABEL: name: load7align2
; MIPS32R6: liveins: $a0
; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32R6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32R6: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.0, align 2)
; MIPS32R6: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load 4 from %ir.0 + 4, align 2)
; MIPS32R6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; MIPS32R6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; MIPS32R6: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
; MIPS32R6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
; MIPS32R6: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[AND1]](s32)
; MIPS32R6: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
; MIPS32R6: $v0 = COPY [[UV]](s32)
; MIPS32R6: $v1 = COPY [[UV1]](s32)
; MIPS32R6: RetRA implicit $v0, implicit $v1
%0:_(p0) = COPY $a0
%1:_(s56) = G_LOAD %0(p0) :: (load 7 from %ir.0, align 2)
%2:_(s64) = G_ZEXT %1(s56)
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
$v0 = COPY %3(s32)
$v1 = COPY %4(s32)
RetRA implicit $v0, implicit $v1
...
---
name: load7align4
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0
; MIPS32-LABEL: name: load7align4
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.0)
; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load 4 from %ir.0 + 4)
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[AND1]](s32)
; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
; MIPS32: $v0 = COPY [[UV]](s32)
; MIPS32: $v1 = COPY [[UV1]](s32)
; MIPS32: RetRA implicit $v0, implicit $v1
; MIPS32R6-LABEL: name: load7align4
; MIPS32R6: liveins: $a0
; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32R6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32R6: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.0)
; MIPS32R6: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load 4 from %ir.0 + 4)
; MIPS32R6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; MIPS32R6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; MIPS32R6: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
; MIPS32R6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
; MIPS32R6: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[AND1]](s32)
; MIPS32R6: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
; MIPS32R6: $v0 = COPY [[UV]](s32)
; MIPS32R6: $v1 = COPY [[UV1]](s32)
; MIPS32R6: RetRA implicit $v0, implicit $v1
%0:_(p0) = COPY $a0
%1:_(s56) = G_LOAD %0(p0) :: (load 7 from %ir.0, align 4)
%2:_(s64) = G_ZEXT %1(s56)
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
$v0 = COPY %3(s32)
$v1 = COPY %4(s32)
RetRA implicit $v0, implicit $v1
...
---
name: load7align8
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
liveins: $a0
; MIPS32-LABEL: name: load7align8
; MIPS32: liveins: $a0
; MIPS32: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.0, align 8)
; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load 4 from %ir.0 + 4, align 8)
; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; MIPS32: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; MIPS32: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
; MIPS32: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[AND1]](s32)
; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
; MIPS32: $v0 = COPY [[UV]](s32)
; MIPS32: $v1 = COPY [[UV1]](s32)
; MIPS32: RetRA implicit $v0, implicit $v1
; MIPS32R6-LABEL: name: load7align8
; MIPS32R6: liveins: $a0
; MIPS32R6: [[COPY:%[0-9]+]]:_(p0) = COPY $a0
; MIPS32R6: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32R6: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32)
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load 4 from %ir.0, align 8)
; MIPS32R6: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (load 4 from %ir.0 + 4, align 8)
; MIPS32R6: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
; MIPS32R6: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16777215
; MIPS32R6: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], [[C1]]
; MIPS32R6: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LOAD1]], [[C2]]
; MIPS32R6: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[AND1]](s32)
; MIPS32R6: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
; MIPS32R6: $v0 = COPY [[UV]](s32)
; MIPS32R6: $v1 = COPY [[UV1]](s32)
; MIPS32R6: RetRA implicit $v0, implicit $v1
%0:_(p0) = COPY $a0
%1:_(s56) = G_LOAD %0(p0) :: (load 7 from %ir.0, align 8)
%2:_(s64) = G_ZEXT %1(s56)
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2(s64)
$v0 = COPY %3(s32)
$v1 = COPY %4(s32)
RetRA implicit $v0, implicit $v1
...
---
name: load_double_align1
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: load_double_align1
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @double_align1
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[GV]], [[C]](s32)
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @double_align1, align 1)
; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (dereferenceable load 4 from @double_align1 + 4, align 1)
; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
; MIPS32: $d0 = COPY [[MV]](s64)
; MIPS32: RetRA implicit $d0
; MIPS32R6-LABEL: name: load_double_align1
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @double_align1
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[GV]](p0) :: (dereferenceable load 8 from @double_align1, align 1)
; MIPS32R6: $d0 = COPY [[LOAD]](s64)
; MIPS32R6: RetRA implicit $d0
%1:_(p0) = G_GLOBAL_VALUE @double_align1
%0:_(s64) = G_LOAD %1(p0) :: (dereferenceable load 8 from @double_align1, align 1)
$d0 = COPY %0(s64)
RetRA implicit $d0
...
---
name: load_double_align2
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: load_double_align2
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @double_align2
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[GV]], [[C]](s32)
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @double_align2, align 2)
; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (dereferenceable load 4 from @double_align2 + 4, align 2)
; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
; MIPS32: $d0 = COPY [[MV]](s64)
; MIPS32: RetRA implicit $d0
; MIPS32R6-LABEL: name: load_double_align2
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @double_align2
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[GV]](p0) :: (dereferenceable load 8 from @double_align2, align 2)
; MIPS32R6: $d0 = COPY [[LOAD]](s64)
; MIPS32R6: RetRA implicit $d0
%1:_(p0) = G_GLOBAL_VALUE @double_align2
%0:_(s64) = G_LOAD %1(p0) :: (dereferenceable load 8 from @double_align2, align 2)
$d0 = COPY %0(s64)
RetRA implicit $d0
...
---
name: load_double_align4
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: load_double_align4
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @double_align4
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[GV]], [[C]](s32)
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @double_align4)
; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (dereferenceable load 4 from @double_align4 + 4)
; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD]](s32), [[LOAD1]](s32)
; MIPS32: $d0 = COPY [[MV]](s64)
; MIPS32: RetRA implicit $d0
; MIPS32R6-LABEL: name: load_double_align4
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @double_align4
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[GV]](p0) :: (dereferenceable load 8 from @double_align4, align 4)
; MIPS32R6: $d0 = COPY [[LOAD]](s64)
; MIPS32R6: RetRA implicit $d0
%1:_(p0) = G_GLOBAL_VALUE @double_align4
%0:_(s64) = G_LOAD %1(p0) :: (dereferenceable load 8 from @double_align4, align 4)
$d0 = COPY %0(s64)
RetRA implicit $d0
...
---
name: load_double_align8
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: load_double_align8
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @double_align8
; MIPS32: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[GV]](p0) :: (dereferenceable load 8 from @double_align8)
; MIPS32: $d0 = COPY [[LOAD]](s64)
; MIPS32: RetRA implicit $d0
; MIPS32R6-LABEL: name: load_double_align8
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @double_align8
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[GV]](p0) :: (dereferenceable load 8 from @double_align8)
; MIPS32R6: $d0 = COPY [[LOAD]](s64)
; MIPS32R6: RetRA implicit $d0
%1:_(p0) = G_GLOBAL_VALUE @double_align8
%0:_(s64) = G_LOAD %1(p0) :: (dereferenceable load 8 from @double_align8)
$d0 = COPY %0(s64)
RetRA implicit $d0
...
---
name: load_i64_align1
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: load_i64_align1
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i64_align1
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[GV]], [[C]](s32)
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @i64_align1, align 1)
; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (dereferenceable load 4 from @i64_align1 + 4, align 1)
; MIPS32: $v0 = COPY [[LOAD]](s32)
; MIPS32: $v1 = COPY [[LOAD1]](s32)
; MIPS32: RetRA implicit $v0, implicit $v1
; MIPS32R6-LABEL: name: load_i64_align1
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i64_align1
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[GV]](p0) :: (dereferenceable load 8 from @i64_align1, align 1)
; MIPS32R6: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](s64)
; MIPS32R6: $v0 = COPY [[UV]](s32)
; MIPS32R6: $v1 = COPY [[UV1]](s32)
; MIPS32R6: RetRA implicit $v0, implicit $v1
%1:_(p0) = G_GLOBAL_VALUE @i64_align1
%0:_(s64) = G_LOAD %1(p0) :: (dereferenceable load 8 from @i64_align1, align 1)
%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %0(s64)
$v0 = COPY %2(s32)
$v1 = COPY %3(s32)
RetRA implicit $v0, implicit $v1
...
---
name: load_i64_align2
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: load_i64_align2
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i64_align2
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[GV]], [[C]](s32)
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @i64_align2, align 2)
; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (dereferenceable load 4 from @i64_align2 + 4, align 2)
; MIPS32: $v0 = COPY [[LOAD]](s32)
; MIPS32: $v1 = COPY [[LOAD1]](s32)
; MIPS32: RetRA implicit $v0, implicit $v1
; MIPS32R6-LABEL: name: load_i64_align2
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i64_align2
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[GV]](p0) :: (dereferenceable load 8 from @i64_align2, align 2)
; MIPS32R6: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](s64)
; MIPS32R6: $v0 = COPY [[UV]](s32)
; MIPS32R6: $v1 = COPY [[UV1]](s32)
; MIPS32R6: RetRA implicit $v0, implicit $v1
%1:_(p0) = G_GLOBAL_VALUE @i64_align2
%0:_(s64) = G_LOAD %1(p0) :: (dereferenceable load 8 from @i64_align2, align 2)
%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %0(s64)
$v0 = COPY %2(s32)
$v1 = COPY %3(s32)
RetRA implicit $v0, implicit $v1
...
---
name: load_i64_align4
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: load_i64_align4
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i64_align4
; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; MIPS32: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[GV]], [[C]](s32)
; MIPS32: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[GV]](p0) :: (dereferenceable load 4 from @i64_align4)
; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD]](p0) :: (dereferenceable load 4 from @i64_align4 + 4)
; MIPS32: $v0 = COPY [[LOAD]](s32)
; MIPS32: $v1 = COPY [[LOAD1]](s32)
; MIPS32: RetRA implicit $v0, implicit $v1
; MIPS32R6-LABEL: name: load_i64_align4
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i64_align4
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[GV]](p0) :: (dereferenceable load 8 from @i64_align4, align 4)
; MIPS32R6: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](s64)
; MIPS32R6: $v0 = COPY [[UV]](s32)
; MIPS32R6: $v1 = COPY [[UV1]](s32)
; MIPS32R6: RetRA implicit $v0, implicit $v1
%1:_(p0) = G_GLOBAL_VALUE @i64_align4
%0:_(s64) = G_LOAD %1(p0) :: (dereferenceable load 8 from @i64_align4, align 4)
%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %0(s64)
$v0 = COPY %2(s32)
$v1 = COPY %3(s32)
RetRA implicit $v0, implicit $v1
...
---
name: load_i64_align8
alignment: 4
tracksRegLiveness: true
body: |
bb.1.entry:
; MIPS32-LABEL: name: load_i64_align8
; MIPS32: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i64_align8
; MIPS32: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[GV]](p0) :: (dereferenceable load 8 from @i64_align8)
; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](s64)
; MIPS32: $v0 = COPY [[UV]](s32)
; MIPS32: $v1 = COPY [[UV1]](s32)
; MIPS32: RetRA implicit $v0, implicit $v1
; MIPS32R6-LABEL: name: load_i64_align8
; MIPS32R6: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @i64_align8
; MIPS32R6: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[GV]](p0) :: (dereferenceable load 8 from @i64_align8)
; MIPS32R6: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[LOAD]](s64)
; MIPS32R6: $v0 = COPY [[UV]](s32)
; MIPS32R6: $v1 = COPY [[UV1]](s32)
; MIPS32R6: RetRA implicit $v0, implicit $v1
%1:_(p0) = G_GLOBAL_VALUE @i64_align8
%0:_(s64) = G_LOAD %1(p0) :: (dereferenceable load 8 from @i64_align8)
%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %0(s64)
$v0 = COPY %2(s32)
$v1 = COPY %3(s32)
RetRA implicit $v0, implicit $v1
...