# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX6 %s
---
name: fadd_s32_vvv
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; GFX6-LABEL: name: fadd_s32_vvv
; GFX6: liveins: $vgpr0, $vgpr1
; GFX6-NEXT: {{ $}}
; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX6-NEXT: %2:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX6-NEXT: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s32) = G_FADD %0, %1
S_ENDPGM 0, implicit %2
...
---
name: fadd_s32_vsv
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0, $sgpr0
; GFX6-LABEL: name: fadd_s32_vsv
; GFX6: liveins: $vgpr0, $sgpr0
; GFX6-NEXT: {{ $}}
; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6-NEXT: %2:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX6-NEXT: S_ENDPGM 0, implicit %2
%0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0
%2:vgpr(s32) = G_FADD %0, %1
S_ENDPGM 0, implicit %2
...
---
name: fadd_s32_vvs
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0, $sgpr0
; GFX6-LABEL: name: fadd_s32_vvs
; GFX6: liveins: $vgpr0, $sgpr0
; GFX6-NEXT: {{ $}}
; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX6-NEXT: %2:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX6-NEXT: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0
%1:sgpr(s32) = COPY $sgpr0
%2:vgpr(s32) = G_FADD %0, %1
S_ENDPGM 0, implicit %2
...
---
name: fadd_s32_vvv_fabs_lhs
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; GFX6-LABEL: name: fadd_s32_vvv_fabs_lhs
; GFX6: liveins: $vgpr0, $vgpr1
; GFX6-NEXT: {{ $}}
; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX6-NEXT: %3:vgpr_32 = nofpexcept V_ADD_F32_e64 2, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX6-NEXT: S_ENDPGM 0, implicit %3
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s32) = G_FABS %0
%3:vgpr(s32) = G_FADD %2, %1
S_ENDPGM 0, implicit %3
...
---
name: fadd_s32_vvv_fabs_rhs
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; GFX6-LABEL: name: fadd_s32_vvv_fabs_rhs
; GFX6: liveins: $vgpr0, $vgpr1
; GFX6-NEXT: {{ $}}
; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX6-NEXT: %3:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY]], 2, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX6-NEXT: S_ENDPGM 0, implicit %3
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s32) = G_FABS %1
%3:vgpr(s32) = G_FADD %1, %2
S_ENDPGM 0, implicit %3
...
---
name: fadd_s32_vvv_fneg_fabs_lhs
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; GFX6-LABEL: name: fadd_s32_vvv_fneg_fabs_lhs
; GFX6: liveins: $vgpr0, $vgpr1
; GFX6-NEXT: {{ $}}
; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX6-NEXT: %4:vgpr_32 = nofpexcept V_ADD_F32_e64 3, [[COPY]], 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX6-NEXT: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s32) = G_FABS %0
%3:vgpr(s32) = G_FNEG %2
%4:vgpr(s32) = G_FADD %3, %1
S_ENDPGM 0, implicit %4
...
---
name: fadd_s32_vvv_fneg_fabs_rhs
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; GFX6-LABEL: name: fadd_s32_vvv_fneg_fabs_rhs
; GFX6: liveins: $vgpr0, $vgpr1
; GFX6-NEXT: {{ $}}
; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX6-NEXT: %4:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY]], 3, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX6-NEXT: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s32) = G_FABS %1
%3:vgpr(s32) = G_FNEG %2
%4:vgpr(s32) = G_FADD %1, %3
S_ENDPGM 0, implicit %4
...
# Need to look through reg bank copy to find source modifiers
---
name: fadd_s32_fneg_copy_sgpr
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0, $sgpr0
; GFX6-LABEL: name: fadd_s32_fneg_copy_sgpr
; GFX6: liveins: $vgpr0, $sgpr0
; GFX6-NEXT: {{ $}}
; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX6-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
; GFX6-NEXT: %4:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY]], 1, [[COPY2]], 0, 0, implicit $mode, implicit $exec
; GFX6-NEXT: S_ENDPGM 0, implicit %4
%0:vgpr(s32) = COPY $vgpr0
%1:sgpr(s32) = COPY $sgpr0
%2:sgpr(s32) = G_FNEG %1
%3:vgpr(s32) = COPY %2
%4:vgpr(s32) = G_FADD %0, %3
S_ENDPGM 0, implicit %4
...
# Need to look through copy in between fneg and fabs
---
name: fadd_s32_copy_fneg_copy_fabs
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0, $sgpr0
; GFX6-LABEL: name: fadd_s32_copy_fneg_copy_fabs
; GFX6: liveins: $vgpr0, $sgpr0
; GFX6-NEXT: {{ $}}
; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX6-NEXT: %6:vgpr_32 = nofpexcept V_ADD_F32_e64 0, [[COPY]], 3, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GFX6-NEXT: S_ENDPGM 0, implicit %6
%0:vgpr(s32) = COPY $vgpr0
%1:sgpr(s32) = COPY $sgpr0
%2:sgpr(s32) = G_FABS %1
%3:sgpr(s32) = COPY %2
%4:sgpr(s32) = G_FNEG %3
%5:sgpr(s32) = COPY %4
%6:vgpr(s32) = G_FADD %0, %5
S_ENDPGM 0, implicit %6
...
# The source modifier lookup searches through SGPR->VGPR copies. Make
# sure we don't violate the constant bus restriction when we look at
# the source.
---
name: fadd_s32_copy_fabs_sgpr_copy_fabs_sgpr
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1
; GFX6-LABEL: name: fadd_s32_copy_fabs_sgpr_copy_fabs_sgpr
; GFX6: liveins: $sgpr0, $sgpr1
; GFX6-NEXT: {{ $}}
; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX6-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
; GFX6-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
; GFX6-NEXT: %6:vgpr_32 = nofpexcept V_ADD_F32_e64 2, [[COPY2]], 2, [[COPY3]], 0, 0, implicit $mode, implicit $exec
; GFX6-NEXT: S_ENDPGM 0, implicit %6
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s32) = G_FABS %0
%3:sgpr(s32) = G_FABS %1
%4:vgpr(s32) = COPY %2
%5:vgpr(s32) = COPY %3
%6:vgpr(s32) = G_FADD %4, %5
S_ENDPGM 0, implicit %6
...
---
name: fadd_s32_copy_fneg_sgpr_copy_fneg_sgpr
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1
; GFX6-LABEL: name: fadd_s32_copy_fneg_sgpr_copy_fneg_sgpr
; GFX6: liveins: $sgpr0, $sgpr1
; GFX6-NEXT: {{ $}}
; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX6-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
; GFX6-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
; GFX6-NEXT: %6:vgpr_32 = nofpexcept V_ADD_F32_e64 1, [[COPY2]], 1, [[COPY3]], 0, 0, implicit $mode, implicit $exec
; GFX6-NEXT: S_ENDPGM 0, implicit %6
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s32) = G_FNEG %0
%3:sgpr(s32) = G_FNEG %1
%4:vgpr(s32) = COPY %2
%5:vgpr(s32) = COPY %3
%6:vgpr(s32) = G_FADD %4, %5
S_ENDPGM 0, implicit %6
...
---
name: fadd_s32_copy_fneg_fabs_sgpr_copy_fneg_fabs_sgpr
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1
; GFX6-LABEL: name: fadd_s32_copy_fneg_fabs_sgpr_copy_fneg_fabs_sgpr
; GFX6: liveins: $sgpr0, $sgpr1
; GFX6-NEXT: {{ $}}
; GFX6-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX6-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX6-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
; GFX6-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
; GFX6-NEXT: %8:vgpr_32 = nofpexcept V_ADD_F32_e64 3, [[COPY2]], 3, [[COPY3]], 0, 0, implicit $mode, implicit $exec
; GFX6-NEXT: S_ENDPGM 0, implicit %8
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s32) = G_FABS %0
%3:sgpr(s32) = G_FABS %1
%4:sgpr(s32) = G_FNEG %2
%5:sgpr(s32) = G_FNEG %3
%6:vgpr(s32) = COPY %4
%7:vgpr(s32) = COPY %5
%8:vgpr(s32) = G_FADD %6, %7
S_ENDPGM 0, implicit %8
...