# RUN: llc -mtriple arm-- -run-pass=legalizer %s -o - | FileCheck %s
# RUN: llc -mtriple thumb-- -mattr=+v6t2 -run-pass=legalizer %s -o - | FileCheck %s
--- |
define void @test_zext_s16_to_s32() { ret void }
define void @test_sext_s8_to_s32() { ret void }
define void @test_sext_inreg_s8_to_s32() { ret void }
define void @test_anyext_s1_to_s32() { ret void }
define void @test_zext_s8_to_s16() { ret void }
define void @test_sext_s1_to_s16() { ret void }
define void @test_anyext_s1_to_s8() { ret void }
define void @test_ext_combine() { ret void }
...
---
name: test_zext_s16_to_s32
# CHECK-LABEL: name: test_zext_s16_to_s32
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.0:
liveins: $r0
%0(p0) = COPY $r0
%1(s16) = G_LOAD %0 :: (load (s16))
%2(s32) = G_ZEXT %1
; G_ZEXT with s16 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_ZEXT {{%[0-9]+}}
$r0 = COPY %2(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_sext_s8_to_s32
# CHECK-LABEL: name: test_sext_s8_to_s32
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.0:
liveins: $r0
%0(p0) = COPY $r0
%1(s8) = G_LOAD %0(p0) :: (load (s8))
%2(s32) = G_SEXT %1
; G_SEXT with s8 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_SEXT {{%[0-9]+}}
$r0 = COPY %2(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_sext_inreg_s8_to_s32
# CHECK-LABEL: name: test_sext_inreg_s8_to_s32
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.0:
liveins: $r0
%0(p0) = COPY $r0
%1(s32) = G_LOAD %0(p0) :: (load (s32))
%2(s32) = G_SEXT_INREG %1, 8
; G_SEXT_INREG should be lowered to a shift pair
; CHECK: [[T1:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
; CHECK: [[T2:%[0-9]+]]:_(s32) = G_SHL {{%[0-9]+}}, [[T1]]
; CHECK: {{%[0-9]+}}:_(s32) = G_ASHR [[T2]], [[T1]]
$r0 = COPY %2(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_anyext_s1_to_s32
# CHECK-LABEL: name: test_anyext_s1_to_s32
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.0:
liveins: $r0
%0(p0) = COPY $r0
%1(s1) = G_LOAD %0(p0) :: (load (s1))
%2(s32) = G_ANYEXT %1
; G_ANYEXT with s1 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s32) = G_ANYEXT {{%[0-9]+}}
$r0 = COPY %2(s32)
BX_RET 14, $noreg, implicit $r0
...
---
name: test_zext_s8_to_s16
# CHECK-LABEL: name: test_zext_s8_to_s16
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.0:
liveins: $r0
%0(p0) = COPY $r0
%1(s8) = G_LOAD %0(p0) :: (load (s8))
%2(s16) = G_ZEXT %1
; G_ZEXT from s8 to s16 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s16) = G_ZEXT {{%[0-9]+}}(s8)
G_STORE %2(s16), %0(p0) :: (store (s16))
BX_RET 14, $noreg
...
---
name: test_sext_s1_to_s16
# CHECK-LABEL: name: test_sext_s1_to_s16
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
body: |
bb.0:
liveins: $r0, $r1
%0:_(p0) = COPY $r0
%1:_(s32) = COPY $r1
%2:_(s32) = G_CONSTANT i32 0
%3:_(s1) = G_ICMP intpred(eq), %1, %2
%4:_(s16) = G_SEXT %3(s1)
; G_SEXT from s1 to s16 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s16) = G_SEXT {{%[0-9]+}}(s1)
G_STORE %4(s16), %0(p0) :: (store (s16))
BX_RET 14, $noreg
...
---
name: test_anyext_s1_to_s8
# CHECK-LABEL: name: test_anyext_s1_to_s8
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
body: |
bb.0:
liveins: $r0, $r1
%0:_(p0) = COPY $r0
%1:_(s32) = COPY $r1
%2:_(s32) = G_CONSTANT i32 0
%3:_(s1) = G_ICMP intpred(eq), %1, %2
%4:_(s8) = G_ANYEXT %3
; G_ANYEXT from s1 to s8 is legal, so we should find it unchanged in the output
; CHECK: {{%[0-9]+}}:_(s8) = G_ANYEXT {{%[0-9]+}}(s1)
G_STORE %4(s8), %0(p0) :: (store (s8))
BX_RET 14, $noreg
...
---
name: test_ext_combine
# CHECK-LABEL: name: test_ext_combine
legalized: false
# CHECK: legalized: true
regBankSelected: false
selected: false
tracksRegLiveness: true
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
- { id: 4, class: _ }
- { id: 5, class: _ }
body: |
bb.0:
liveins: $r0
%0(p0) = COPY $r0
%1(s8) = G_LOAD %0(p0) :: (load (s8))
; CHECK: [[V8:%[0-9]+]]:_(s8) = G_LOAD
%2(s16) = G_ZEXT %1
%3(s16) = G_SEXT %1
%4(s16) = G_OR %2, %3
; G_OR is going to widen to 32 bits and the extensions/truncs should combine
; with the already existing ones
; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[V8]](s8)
; CHECK: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[V8]](s8)
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[ZEXT]], [[SEXT]]
; CHECK: [[BITS:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
; CHECK: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[OR]], [[BITS]](s32)
; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[BITS]](s32)
; CHECK: $r0 = COPY [[ASHR]]
%5(s32) = G_SEXT %4(s16)
$r0 = COPY %5
BX_RET 14, $noreg, implicit $r0
...