#define ARM64_SYSREG(op0, op1, crn, crm, op2) \
( ((op0 & 1) << 14) | \
((op1 & 7) << 11) | \
((crn & 15) << 7) | \
((crm & 15) << 3) | \
((op2 & 7) << 0) )
#define ARM64_CNTVCT ARM64_SYSREG(3,3,14, 0,2)
#define ARM64_PMCCNTR_EL0 ARM64_SYSREG(3,3, 9,13,0)
#define ARM64_PMSELR_EL0 ARM64_SYSREG(3,3, 9,12,5)
#define ARM64_PMXEVCNTR_EL0 ARM64_SYSREG(3,3, 9,13,2)
#define ARM64_PMXEVCNTRn_EL0(n) ARM64_SYSREG(3,3,14, 8+((n)/8), (n)%8)
#define ARM64_TPIDR_EL0 ARM64_SYSREG(3,3,13, 0,2)
#define ARM64_TPIDRRO_EL0 ARM64_SYSREG(3,3,13, 0,3)
#define ARM64_TPIDR_EL1 ARM64_SYSREG(3,0,13, 0,4)
__int64 _ReadStatusReg(int);
void _WriteStatusReg(int, __int64);
void check_ReadWriteStatusReg(__int64 v) {
__int64 ret;
ret = _ReadStatusReg(ARM64_CNTVCT);
ret = _ReadStatusReg(ARM64_PMCCNTR_EL0);
ret = _ReadStatusReg(ARM64_PMSELR_EL0);
ret = _ReadStatusReg(ARM64_PMXEVCNTR_EL0);
ret = _ReadStatusReg(ARM64_PMXEVCNTRn_EL0(0));
ret = _ReadStatusReg(ARM64_PMXEVCNTRn_EL0(1));
ret = _ReadStatusReg(ARM64_PMXEVCNTRn_EL0(30));
ret = _ReadStatusReg(ARM64_TPIDR_EL0);
ret = _ReadStatusReg(ARM64_TPIDRRO_EL0);
ret = _ReadStatusReg(ARM64_TPIDR_EL1);
_WriteStatusReg(ARM64_CNTVCT, v);
_WriteStatusReg(ARM64_PMCCNTR_EL0, v);
_WriteStatusReg(ARM64_PMSELR_EL0, v);
_WriteStatusReg(ARM64_PMXEVCNTR_EL0, v);
_WriteStatusReg(ARM64_PMXEVCNTRn_EL0(0), v);
_WriteStatusReg(ARM64_PMXEVCNTRn_EL0(1), v);
_WriteStatusReg(ARM64_PMXEVCNTRn_EL0(30), v);
_WriteStatusReg(ARM64_TPIDR_EL0, v);
_WriteStatusReg(ARM64_TPIDRRO_EL0, v);
_WriteStatusReg(ARM64_TPIDR_EL1, v);
}