# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64-apple-ios -run-pass instruction-select %s \
# RUN: -disable-gisel-legality-check -verify-machineinstrs -simplify-mir \
# RUN: -o - | FileCheck %s
---
name: test_rule14_id188_at_idx1067
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $d0
; CHECK-LABEL: name: test_rule14_id188_at_idx1067
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load (s128))
; CHECK: $noreg = PATCHABLE_RET [[LDRQui]]
%1:fpr(p0) = COPY $d0
%0:fpr(s128) = G_LOAD %1(p0) :: (load (s128))
$noreg = PATCHABLE_RET %0(s128)
...
---
name: test_rule21_id2237_at_idx1449
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%0' }
- { reg: '$d1', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $d0, $d1
; CHECK-LABEL: name: test_rule21_id2237_at_idx1449
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
; CHECK: STRDui [[COPY1]], [[COPY2]], 0 :: (store (<8 x s8>))
; CHECK: $noreg = PATCHABLE_RET
%1:fpr(p0) = COPY $d1
%0:fpr(<8 x s8>) = COPY $d0
G_STORE %0(<8 x s8>), %1(p0) :: (store (<8 x s8>))
$noreg = PATCHABLE_RET
...
---
name: test_rule22_id2238_at_idx1505
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%0' }
- { reg: '$d1', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $d0, $d1
; CHECK-LABEL: name: test_rule22_id2238_at_idx1505
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
; CHECK: STRDui [[COPY1]], [[COPY2]], 0 :: (store (<4 x s16>))
; CHECK: $noreg = PATCHABLE_RET
%1:fpr(p0) = COPY $d1
%0:fpr(<4 x s16>) = COPY $d0
G_STORE %0(<4 x s16>), %1(p0) :: (store (<4 x s16>))
$noreg = PATCHABLE_RET
...
---
name: test_rule27_id2243_at_idx1781
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%0' }
- { reg: '$d0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $q0, $d0
; CHECK-LABEL: name: test_rule27_id2243_at_idx1781
; CHECK: liveins: $q0, $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
; CHECK: STRQui [[COPY1]], [[COPY2]], 0 :: (store (<4 x s32>))
; CHECK: $noreg = PATCHABLE_RET
%1:fpr(p0) = COPY $d0
%0:fpr(<4 x s32>) = COPY $q0
G_STORE %0(<4 x s32>), %1(p0) :: (store (<4 x s32>))
$noreg = PATCHABLE_RET
...
---
name: test_rule28_id2244_at_idx1837
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%0' }
- { reg: '$d0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $q0, $d0
; CHECK-LABEL: name: test_rule28_id2244_at_idx1837
; CHECK: liveins: $q0, $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
; CHECK: STRQui [[COPY1]], [[COPY2]], 0 :: (store (<2 x s64>))
; CHECK: $noreg = PATCHABLE_RET
%1:fpr(p0) = COPY $d0
%0:fpr(<2 x s64>) = COPY $q0
G_STORE %0(<2 x s64>), %1(p0) :: (store (<2 x s64>))
$noreg = PATCHABLE_RET
...
---
name: test_rule29_id2245_at_idx1893
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%0' }
- { reg: '$d0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $q0, $d0
; CHECK-LABEL: name: test_rule29_id2245_at_idx1893
; CHECK: liveins: $q0, $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
; CHECK: STRQui [[COPY1]], [[COPY2]], 0 :: (store (<16 x s8>))
; CHECK: $noreg = PATCHABLE_RET
%1:fpr(p0) = COPY $d0
%0:fpr(<16 x s8>) = COPY $q0
G_STORE %0(<16 x s8>), %1(p0) :: (store (<16 x s8>))
$noreg = PATCHABLE_RET
...
---
name: test_rule30_id2246_at_idx1949
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%0' }
- { reg: '$d0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $q0, $d0
; CHECK-LABEL: name: test_rule30_id2246_at_idx1949
; CHECK: liveins: $q0, $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
; CHECK: STRQui [[COPY1]], [[COPY2]], 0 :: (store (<8 x s16>))
; CHECK: $noreg = PATCHABLE_RET
%1:fpr(p0) = COPY $d0
%0:fpr(<8 x s16>) = COPY $q0
G_STORE %0(<8 x s16>), %1(p0) :: (store (<8 x s16>))
$noreg = PATCHABLE_RET
...
---
name: test_rule34_id2250_at_idx2173
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%0' }
- { reg: '$d0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $q0, $d0
; CHECK-LABEL: name: test_rule34_id2250_at_idx2173
; CHECK: liveins: $q0, $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[COPY2:%[0-9]+]]:gpr64sp = COPY [[COPY]]
; CHECK: STRQui [[COPY1]], [[COPY2]], 0 :: (store (s128))
; CHECK: $noreg = PATCHABLE_RET
%1:fpr(p0) = COPY $d0
%0:fpr(s128) = COPY $q0
G_STORE %0(s128), %1(p0) :: (store (s128))
$noreg = PATCHABLE_RET
...
# The rules that generated this test has changed. The generator should be rerun
---
name: test_rule92_id2150_at_idx7770
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
liveins:
- { reg: '$x0', virtual-reg: '%2' }
body: |
bb.0.entry:
liveins: $x0
; CHECK-LABEL: name: test_rule92_id2150_at_idx7770
; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load (s8))
; CHECK: $noreg = PATCHABLE_RET [[LDRBBui]]
%2:gpr(p0) = COPY $x0
%0:gpr(s32) = G_LOAD %2(p0) :: (load (s8))
$noreg = PATCHABLE_RET %0(s32)
...
# The rules that generated this test has changed. The generator should be rerun
---
name: test_rule96_id2146_at_idx8070
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
liveins:
- { reg: '$x0', virtual-reg: '%2' }
body: |
bb.0.entry:
liveins: $x0
; CHECK-LABEL: name: test_rule96_id2146_at_idx8070
; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[LDRBui:%[0-9]+]]:fpr8 = LDRBui [[COPY]], 0 :: (load (s8))
; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[LDRBui]]
; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 0, 7
; CHECK: $noreg = PATCHABLE_RET [[UBFMWri]]
%2:gpr(p0) = COPY $x0
%0:fpr(s8) = G_LOAD %2(p0) :: (load (s8))
%1:gpr(s32) = G_ZEXT %0(s8)
$noreg = PATCHABLE_RET %1(s32)
...
---
name: test_rule129_id2130_at_idx10828
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $d0
; CHECK-LABEL: name: test_rule129_id2130_at_idx10828
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 :: (load (<8 x s8>))
; CHECK: $noreg = PATCHABLE_RET [[LDRDui]]
%1:fpr(p0) = COPY $d0
%0:fpr(<8 x s8>) = G_LOAD %1(p0) :: (load (<8 x s8>))
$noreg = PATCHABLE_RET %0(<8 x s8>)
...
---
name: test_rule130_id2131_at_idx10884
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $d0
; CHECK-LABEL: name: test_rule130_id2131_at_idx10884
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 :: (load (<4 x s16>))
; CHECK: $noreg = PATCHABLE_RET [[LDRDui]]
%1:fpr(p0) = COPY $d0
%0:fpr(<4 x s16>) = G_LOAD %1(p0) :: (load (<4 x s16>))
$noreg = PATCHABLE_RET %0(<4 x s16>)
...
---
name: test_rule135_id2136_at_idx11160
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $d0
; CHECK-LABEL: name: test_rule135_id2136_at_idx11160
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load (<4 x s32>))
; CHECK: $noreg = PATCHABLE_RET [[LDRQui]]
%1:fpr(p0) = COPY $d0
%0:fpr(<4 x s32>) = G_LOAD %1(p0) :: (load (<4 x s32>))
$noreg = PATCHABLE_RET %0(<4 x s32>)
...
---
name: test_rule136_id2137_at_idx11216
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $d0
; CHECK-LABEL: name: test_rule136_id2137_at_idx11216
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load (<2 x s64>))
; CHECK: $noreg = PATCHABLE_RET [[LDRQui]]
%1:fpr(p0) = COPY $d0
%0:fpr(<2 x s64>) = G_LOAD %1(p0) :: (load (<2 x s64>))
$noreg = PATCHABLE_RET %0(<2 x s64>)
...
---
name: test_rule137_id2138_at_idx11272
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $d0
; CHECK-LABEL: name: test_rule137_id2138_at_idx11272
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load (<16 x s8>))
; CHECK: $noreg = PATCHABLE_RET [[LDRQui]]
%1:fpr(p0) = COPY $d0
%0:fpr(<16 x s8>) = G_LOAD %1(p0) :: (load (<16 x s8>))
$noreg = PATCHABLE_RET %0(<16 x s8>)
...
---
name: test_rule138_id2139_at_idx11328
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $d0
; CHECK-LABEL: name: test_rule138_id2139_at_idx11328
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[COPY]]
; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY1]], 0 :: (load (<8 x s16>))
; CHECK: $noreg = PATCHABLE_RET [[LDRQui]]
%1:fpr(p0) = COPY $d0
%0:fpr(<8 x s16>) = G_LOAD %1(p0) :: (load (<8 x s16>))
$noreg = PATCHABLE_RET %0(<8 x s16>)
...
---
name: test_rule339_id2369_at_idx26608
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
- { id: 5, class: fpr }
liveins:
- { reg: '$s0', virtual-reg: '%3' }
- { reg: '$s1', virtual-reg: '%4' }
- { reg: '$s2', virtual-reg: '%5' }
body: |
bb.0.entry:
liveins: $s0, $s1, $s2
; CHECK-LABEL: name: test_rule339_id2369_at_idx26608
; CHECK: liveins: $s0, $s1, $s2
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
; CHECK: [[FNMADDSrrr:%[0-9]+]]:fpr32 = nofpexcept FNMADDSrrr [[COPY1]], [[COPY2]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FNMADDSrrr]]
%5:fpr(s32) = COPY $s2
%4:fpr(s32) = COPY $s1
%3:fpr(s32) = COPY $s0
%1:fpr(s32) = G_FNEG %5
%0:fpr(s32) = G_FNEG %4
%2:fpr(s32) = G_FMA %0, %3, %1
$noreg = PATCHABLE_RET %2(s32)
...
---
name: test_rule340_id2370_at_idx26714
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
- { id: 5, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%3' }
- { reg: '$d1', virtual-reg: '%4' }
- { reg: '$d2', virtual-reg: '%5' }
body: |
bb.0.entry:
liveins: $d0, $d1, $d2
; CHECK-LABEL: name: test_rule340_id2370_at_idx26714
; CHECK: liveins: $d0, $d1, $d2
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[FNMADDDrrr:%[0-9]+]]:fpr64 = nofpexcept FNMADDDrrr [[COPY1]], [[COPY2]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FNMADDDrrr]]
%5:fpr(s64) = COPY $d2
%4:fpr(s64) = COPY $d1
%3:fpr(s64) = COPY $d0
%1:fpr(s64) = G_FNEG %5
%0:fpr(s64) = G_FNEG %4
%2:fpr(s64) = G_FMA %0, %3, %1
$noreg = PATCHABLE_RET %2(s64)
...
---
name: test_rule341_id2371_at_idx26820
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
- { id: 5, class: fpr }
liveins:
- { reg: '$s0', virtual-reg: '%3' }
- { reg: '$s1', virtual-reg: '%4' }
- { reg: '$s2', virtual-reg: '%5' }
body: |
bb.0.entry:
liveins: $s0, $s1, $s2
; CHECK-LABEL: name: test_rule341_id2371_at_idx26820
; CHECK: liveins: $s0, $s1, $s2
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
; CHECK: [[FNMADDSrrr:%[0-9]+]]:fpr32 = nofpexcept FNMADDSrrr [[COPY1]], [[COPY2]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FNMADDSrrr]]
%5:fpr(s32) = COPY $s2
%4:fpr(s32) = COPY $s1
%3:fpr(s32) = COPY $s0
%1:fpr(s32) = G_FNEG %5
%0:fpr(s32) = G_FNEG %4
%2:fpr(s32) = G_FMA %3, %0, %1
$noreg = PATCHABLE_RET %2(s32)
...
---
name: test_rule342_id2372_at_idx26926
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
- { id: 5, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%3' }
- { reg: '$d1', virtual-reg: '%4' }
- { reg: '$d2', virtual-reg: '%5' }
body: |
bb.0.entry:
liveins: $d0, $d1, $d2
; CHECK-LABEL: name: test_rule342_id2372_at_idx26926
; CHECK: liveins: $d0, $d1, $d2
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[FNMADDDrrr:%[0-9]+]]:fpr64 = nofpexcept FNMADDDrrr [[COPY1]], [[COPY2]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FNMADDDrrr]]
%5:fpr(s64) = COPY $d2
%4:fpr(s64) = COPY $d1
%3:fpr(s64) = COPY $d0
%1:fpr(s64) = G_FNEG %5
%0:fpr(s64) = G_FNEG %4
%2:fpr(s64) = G_FMA %3, %0, %1
$noreg = PATCHABLE_RET %2(s64)
...
---
name: test_rule343_id1266_at_idx27032
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%3' }
- { reg: '$d1', virtual-reg: '%4' }
body: |
bb.0.entry:
liveins: $d0, $d1
; CHECK-LABEL: name: test_rule343_id1266_at_idx27032
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[SADDLv8i8_v8i16_:%[0-9]+]]:fpr128 = SADDLv8i8_v8i16 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[SADDLv8i8_v8i16_]]
%4:fpr(<8 x s8>) = COPY $d1
%3:fpr(<8 x s8>) = COPY $d0
%1:fpr(<8 x s16>) = G_SEXT %4(<8 x s8>)
%0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>)
%2:fpr(<8 x s16>) = G_ADD %0, %1
$noreg = PATCHABLE_RET %2(<8 x s16>)
...
---
name: test_rule344_id1268_at_idx27128
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%3' }
- { reg: '$d1', virtual-reg: '%4' }
body: |
bb.0.entry:
liveins: $d0, $d1
; CHECK-LABEL: name: test_rule344_id1268_at_idx27128
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[SADDLv4i16_v4i32_:%[0-9]+]]:fpr128 = SADDLv4i16_v4i32 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[SADDLv4i16_v4i32_]]
%4:fpr(<4 x s16>) = COPY $d1
%3:fpr(<4 x s16>) = COPY $d0
%1:fpr(<4 x s32>) = G_SEXT %4(<4 x s16>)
%0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>)
%2:fpr(<4 x s32>) = G_ADD %0, %1
$noreg = PATCHABLE_RET %2(<4 x s32>)
...
---
name: test_rule345_id1270_at_idx27224
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%3' }
- { reg: '$d1', virtual-reg: '%4' }
body: |
bb.0.entry:
liveins: $d0, $d1
; CHECK-LABEL: name: test_rule345_id1270_at_idx27224
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[SADDLv2i32_v2i64_:%[0-9]+]]:fpr128 = SADDLv2i32_v2i64 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[SADDLv2i32_v2i64_]]
%4:fpr(<2 x s32>) = COPY $d1
%3:fpr(<2 x s32>) = COPY $d0
%1:fpr(<2 x s64>) = G_SEXT %4(<2 x s32>)
%0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>)
%2:fpr(<2 x s64>) = G_ADD %0, %1
$noreg = PATCHABLE_RET %2(<2 x s64>)
...
---
name: test_rule346_id1326_at_idx27320
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%3' }
- { reg: '$d1', virtual-reg: '%4' }
body: |
bb.0.entry:
liveins: $d0, $d1
; CHECK-LABEL: name: test_rule346_id1326_at_idx27320
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[UADDLv8i8_v8i16_:%[0-9]+]]:fpr128 = UADDLv8i8_v8i16 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[UADDLv8i8_v8i16_]]
%4:fpr(<8 x s8>) = COPY $d1
%3:fpr(<8 x s8>) = COPY $d0
%1:fpr(<8 x s16>) = G_ZEXT %4(<8 x s8>)
%0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>)
%2:fpr(<8 x s16>) = G_ADD %0, %1
$noreg = PATCHABLE_RET %2(<8 x s16>)
...
---
name: test_rule347_id1328_at_idx27416
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%3' }
- { reg: '$d1', virtual-reg: '%4' }
body: |
bb.0.entry:
liveins: $d0, $d1
; CHECK-LABEL: name: test_rule347_id1328_at_idx27416
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[UADDLv4i16_v4i32_:%[0-9]+]]:fpr128 = UADDLv4i16_v4i32 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[UADDLv4i16_v4i32_]]
%4:fpr(<4 x s16>) = COPY $d1
%3:fpr(<4 x s16>) = COPY $d0
%1:fpr(<4 x s32>) = G_ZEXT %4(<4 x s16>)
%0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>)
%2:fpr(<4 x s32>) = G_ADD %0, %1
$noreg = PATCHABLE_RET %2(<4 x s32>)
...
---
name: test_rule348_id1330_at_idx27512
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%3' }
- { reg: '$d1', virtual-reg: '%4' }
body: |
bb.0.entry:
liveins: $d0, $d1
; CHECK-LABEL: name: test_rule348_id1330_at_idx27512
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[UADDLv2i32_v2i64_:%[0-9]+]]:fpr128 = UADDLv2i32_v2i64 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[UADDLv2i32_v2i64_]]
%4:fpr(<2 x s32>) = COPY $d1
%3:fpr(<2 x s32>) = COPY $d0
%1:fpr(<2 x s64>) = G_ZEXT %4(<2 x s32>)
%0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>)
%2:fpr(<2 x s64>) = G_ADD %0, %1
$noreg = PATCHABLE_RET %2(<2 x s64>)
...
---
name: test_rule349_id1308_at_idx27608
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%3' }
- { reg: '$d1', virtual-reg: '%4' }
body: |
bb.0.entry:
liveins: $d0, $d1
; CHECK-LABEL: name: test_rule349_id1308_at_idx27608
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[SSUBLv8i8_v8i16_:%[0-9]+]]:fpr128 = SSUBLv8i8_v8i16 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[SSUBLv8i8_v8i16_]]
%4:fpr(<8 x s8>) = COPY $d1
%3:fpr(<8 x s8>) = COPY $d0
%1:fpr(<8 x s16>) = G_SEXT %4(<8 x s8>)
%0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>)
%2:fpr(<8 x s16>) = G_SUB %0, %1
$noreg = PATCHABLE_RET %2(<8 x s16>)
...
---
name: test_rule350_id1310_at_idx27704
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%3' }
- { reg: '$d1', virtual-reg: '%4' }
body: |
bb.0.entry:
liveins: $d0, $d1
; CHECK-LABEL: name: test_rule350_id1310_at_idx27704
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[SSUBLv4i16_v4i32_:%[0-9]+]]:fpr128 = SSUBLv4i16_v4i32 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[SSUBLv4i16_v4i32_]]
%4:fpr(<4 x s16>) = COPY $d1
%3:fpr(<4 x s16>) = COPY $d0
%1:fpr(<4 x s32>) = G_SEXT %4(<4 x s16>)
%0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>)
%2:fpr(<4 x s32>) = G_SUB %0, %1
$noreg = PATCHABLE_RET %2(<4 x s32>)
...
---
name: test_rule351_id1312_at_idx27800
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%3' }
- { reg: '$d1', virtual-reg: '%4' }
body: |
bb.0.entry:
liveins: $d0, $d1
; CHECK-LABEL: name: test_rule351_id1312_at_idx27800
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[SSUBLv2i32_v2i64_:%[0-9]+]]:fpr128 = SSUBLv2i32_v2i64 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[SSUBLv2i32_v2i64_]]
%4:fpr(<2 x s32>) = COPY $d1
%3:fpr(<2 x s32>) = COPY $d0
%1:fpr(<2 x s64>) = G_SEXT %4(<2 x s32>)
%0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>)
%2:fpr(<2 x s64>) = G_SUB %0, %1
$noreg = PATCHABLE_RET %2(<2 x s64>)
...
---
name: test_rule352_id1356_at_idx27896
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%3' }
- { reg: '$d1', virtual-reg: '%4' }
body: |
bb.0.entry:
liveins: $d0, $d1
; CHECK-LABEL: name: test_rule352_id1356_at_idx27896
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[USUBLv8i8_v8i16_:%[0-9]+]]:fpr128 = USUBLv8i8_v8i16 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[USUBLv8i8_v8i16_]]
%4:fpr(<8 x s8>) = COPY $d1
%3:fpr(<8 x s8>) = COPY $d0
%1:fpr(<8 x s16>) = G_ZEXT %4(<8 x s8>)
%0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>)
%2:fpr(<8 x s16>) = G_SUB %0, %1
$noreg = PATCHABLE_RET %2(<8 x s16>)
...
---
name: test_rule353_id1358_at_idx27992
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%3' }
- { reg: '$d1', virtual-reg: '%4' }
body: |
bb.0.entry:
liveins: $d0, $d1
; CHECK-LABEL: name: test_rule353_id1358_at_idx27992
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[USUBLv4i16_v4i32_:%[0-9]+]]:fpr128 = USUBLv4i16_v4i32 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[USUBLv4i16_v4i32_]]
%4:fpr(<4 x s16>) = COPY $d1
%3:fpr(<4 x s16>) = COPY $d0
%1:fpr(<4 x s32>) = G_ZEXT %4(<4 x s16>)
%0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>)
%2:fpr(<4 x s32>) = G_SUB %0, %1
$noreg = PATCHABLE_RET %2(<4 x s32>)
...
---
name: test_rule354_id1360_at_idx28088
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%3' }
- { reg: '$d1', virtual-reg: '%4' }
body: |
bb.0.entry:
liveins: $d0, $d1
; CHECK-LABEL: name: test_rule354_id1360_at_idx28088
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[USUBLv2i32_v2i64_:%[0-9]+]]:fpr128 = USUBLv2i32_v2i64 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[USUBLv2i32_v2i64_]]
%4:fpr(<2 x s32>) = COPY $d1
%3:fpr(<2 x s32>) = COPY $d0
%1:fpr(<2 x s64>) = G_ZEXT %4(<2 x s32>)
%0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>)
%2:fpr(<2 x s64>) = G_SUB %0, %1
$noreg = PATCHABLE_RET %2(<2 x s64>)
...
---
name: test_rule928_id2367_at_idx60019
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
liveins:
- { reg: '$s0', virtual-reg: '%2' }
- { reg: '$s1', virtual-reg: '%3' }
- { reg: '$s2', virtual-reg: '%4' }
body: |
bb.0.entry:
liveins: $s0, $s1, $s2
; CHECK-LABEL: name: test_rule928_id2367_at_idx60019
; CHECK: liveins: $s0, $s1, $s2
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
; CHECK: [[FMSUBSrrr:%[0-9]+]]:fpr32 = nofpexcept FMSUBSrrr [[COPY]], [[COPY2]], [[COPY1]]
; CHECK: $noreg = PATCHABLE_RET [[FMSUBSrrr]]
%4:fpr(s32) = COPY $s2
%3:fpr(s32) = COPY $s1
%2:fpr(s32) = COPY $s0
%0:fpr(s32) = G_FNEG %4
%1:fpr(s32) = G_FMA %0, %2, %3
$noreg = PATCHABLE_RET %1(s32)
...
---
name: test_rule929_id2368_at_idx60105
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%2' }
- { reg: '$d1', virtual-reg: '%3' }
- { reg: '$d2', virtual-reg: '%4' }
body: |
bb.0.entry:
liveins: $d0, $d1, $d2
; CHECK-LABEL: name: test_rule929_id2368_at_idx60105
; CHECK: liveins: $d0, $d1, $d2
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[FMSUBDrrr:%[0-9]+]]:fpr64 = nofpexcept FMSUBDrrr [[COPY]], [[COPY2]], [[COPY1]]
; CHECK: $noreg = PATCHABLE_RET [[FMSUBDrrr]]
%4:fpr(s64) = COPY $d2
%3:fpr(s64) = COPY $d1
%2:fpr(s64) = COPY $d0
%0:fpr(s64) = G_FNEG %4
%1:fpr(s64) = G_FMA %0, %2, %3
$noreg = PATCHABLE_RET %1(s64)
...
---
name: test_rule930_id2446_at_idx60191
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%2' }
- { reg: '$d1', virtual-reg: '%3' }
- { reg: '$d2', virtual-reg: '%4' }
body: |
bb.0.entry:
liveins: $d0, $d1, $d2
; CHECK-LABEL: name: test_rule930_id2446_at_idx60191
; CHECK: liveins: $d0, $d1, $d2
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[FMLSv2f32_:%[0-9]+]]:fpr64 = nofpexcept FMLSv2f32 [[COPY1]], [[COPY2]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FMLSv2f32_]]
%4:fpr(<2 x s32>) = COPY $d2
%3:fpr(<2 x s32>) = COPY $d1
%2:fpr(<2 x s32>) = COPY $d0
%0:fpr(<2 x s32>) = G_FNEG %4
%1:fpr(<2 x s32>) = G_FMA %0, %2, %3
$noreg = PATCHABLE_RET %1(<2 x s32>)
...
---
name: test_rule931_id2447_at_idx60277
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%2' }
- { reg: '$q1', virtual-reg: '%3' }
- { reg: '$q2', virtual-reg: '%4' }
body: |
bb.0.entry:
liveins: $q0, $q1, $q2
; CHECK-LABEL: name: test_rule931_id2447_at_idx60277
; CHECK: liveins: $q0, $q1, $q2
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[FMLSv4f32_:%[0-9]+]]:fpr128 = nofpexcept FMLSv4f32 [[COPY1]], [[COPY2]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FMLSv4f32_]]
%4:fpr(<4 x s32>) = COPY $q2
%3:fpr(<4 x s32>) = COPY $q1
%2:fpr(<4 x s32>) = COPY $q0
%0:fpr(<4 x s32>) = G_FNEG %4
%1:fpr(<4 x s32>) = G_FMA %0, %2, %3
$noreg = PATCHABLE_RET %1(<4 x s32>)
...
---
name: test_rule932_id2448_at_idx60363
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%2' }
- { reg: '$q1', virtual-reg: '%3' }
- { reg: '$q2', virtual-reg: '%4' }
body: |
bb.0.entry:
liveins: $q0, $q1, $q2
; CHECK-LABEL: name: test_rule932_id2448_at_idx60363
; CHECK: liveins: $q0, $q1, $q2
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[FMLSv2f64_:%[0-9]+]]:fpr128 = nofpexcept FMLSv2f64 [[COPY1]], [[COPY2]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FMLSv2f64_]]
%4:fpr(<2 x s64>) = COPY $q2
%3:fpr(<2 x s64>) = COPY $q1
%2:fpr(<2 x s64>) = COPY $q0
%0:fpr(<2 x s64>) = G_FNEG %4
%1:fpr(<2 x s64>) = G_FMA %0, %2, %3
$noreg = PATCHABLE_RET %1(<2 x s64>)
...
---
name: test_rule934_id429_at_idx60537
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
liveins:
- { reg: '$s0', virtual-reg: '%2' }
- { reg: '$s1', virtual-reg: '%3' }
- { reg: '$s2', virtual-reg: '%4' }
body: |
bb.0.entry:
liveins: $s0, $s1, $s2
; CHECK-LABEL: name: test_rule934_id429_at_idx60537
; CHECK: liveins: $s0, $s1, $s2
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
; CHECK: [[FMSUBSrrr:%[0-9]+]]:fpr32 = nofpexcept FMSUBSrrr [[COPY2]], [[COPY]], [[COPY1]]
; CHECK: $noreg = PATCHABLE_RET [[FMSUBSrrr]]
%4:fpr(s32) = COPY $s2
%3:fpr(s32) = COPY $s1
%2:fpr(s32) = COPY $s0
%0:fpr(s32) = G_FNEG %4
%1:fpr(s32) = G_FMA %2, %0, %3
$noreg = PATCHABLE_RET %1(s32)
...
---
name: test_rule935_id430_at_idx60625
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%2' }
- { reg: '$d1', virtual-reg: '%3' }
- { reg: '$d2', virtual-reg: '%4' }
body: |
bb.0.entry:
liveins: $d0, $d1, $d2
; CHECK-LABEL: name: test_rule935_id430_at_idx60625
; CHECK: liveins: $d0, $d1, $d2
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[FMSUBDrrr:%[0-9]+]]:fpr64 = nofpexcept FMSUBDrrr [[COPY2]], [[COPY]], [[COPY1]]
; CHECK: $noreg = PATCHABLE_RET [[FMSUBDrrr]]
%4:fpr(s64) = COPY $d2
%3:fpr(s64) = COPY $d1
%2:fpr(s64) = COPY $d0
%0:fpr(s64) = G_FNEG %4
%1:fpr(s64) = G_FMA %2, %0, %3
$noreg = PATCHABLE_RET %1(s64)
...
---
name: test_rule938_id899_at_idx60889
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%2' }
- { reg: '$d1', virtual-reg: '%3' }
- { reg: '$d2', virtual-reg: '%4' }
body: |
bb.0.entry:
liveins: $d0, $d1, $d2
; CHECK-LABEL: name: test_rule938_id899_at_idx60889
; CHECK: liveins: $d0, $d1, $d2
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[FMLSv2f32_:%[0-9]+]]:fpr64 = nofpexcept FMLSv2f32 [[COPY1]], [[COPY2]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FMLSv2f32_]]
%4:fpr(<2 x s32>) = COPY $d2
%3:fpr(<2 x s32>) = COPY $d1
%2:fpr(<2 x s32>) = COPY $d0
%0:fpr(<2 x s32>) = G_FNEG %4
%1:fpr(<2 x s32>) = G_FMA %2, %0, %3
$noreg = PATCHABLE_RET %1(<2 x s32>)
...
---
name: test_rule939_id900_at_idx60977
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%2' }
- { reg: '$q1', virtual-reg: '%3' }
- { reg: '$q2', virtual-reg: '%4' }
body: |
bb.0.entry:
liveins: $q0, $q1, $q2
; CHECK-LABEL: name: test_rule939_id900_at_idx60977
; CHECK: liveins: $q0, $q1, $q2
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[FMLSv4f32_:%[0-9]+]]:fpr128 = nofpexcept FMLSv4f32 [[COPY1]], [[COPY2]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FMLSv4f32_]]
%4:fpr(<4 x s32>) = COPY $q2
%3:fpr(<4 x s32>) = COPY $q1
%2:fpr(<4 x s32>) = COPY $q0
%0:fpr(<4 x s32>) = G_FNEG %4
%1:fpr(<4 x s32>) = G_FMA %2, %0, %3
$noreg = PATCHABLE_RET %1(<4 x s32>)
...
---
name: test_rule940_id901_at_idx61065
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%2' }
- { reg: '$q1', virtual-reg: '%3' }
- { reg: '$q2', virtual-reg: '%4' }
body: |
bb.0.entry:
liveins: $q0, $q1, $q2
; CHECK-LABEL: name: test_rule940_id901_at_idx61065
; CHECK: liveins: $q0, $q1, $q2
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[FMLSv2f64_:%[0-9]+]]:fpr128 = nofpexcept FMLSv2f64 [[COPY1]], [[COPY2]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FMLSv2f64_]]
%4:fpr(<2 x s64>) = COPY $q2
%3:fpr(<2 x s64>) = COPY $q1
%2:fpr(<2 x s64>) = COPY $q0
%0:fpr(<2 x s64>) = G_FNEG %4
%1:fpr(<2 x s64>) = G_FMA %2, %0, %3
$noreg = PATCHABLE_RET %1(<2 x s64>)
...
---
name: test_rule942_id435_at_idx61241
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
liveins:
- { reg: '$s0', virtual-reg: '%2' }
- { reg: '$s1', virtual-reg: '%3' }
- { reg: '$s2', virtual-reg: '%4' }
body: |
bb.0.entry:
liveins: $s0, $s1, $s2
; CHECK-LABEL: name: test_rule942_id435_at_idx61241
; CHECK: liveins: $s0, $s1, $s2
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
; CHECK: [[FNMSUBSrrr:%[0-9]+]]:fpr32 = nofpexcept FNMSUBSrrr [[COPY2]], [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FNMSUBSrrr]]
%4:fpr(s32) = COPY $s2
%3:fpr(s32) = COPY $s1
%2:fpr(s32) = COPY $s0
%0:fpr(s32) = G_FNEG %4
%1:fpr(s32) = G_FMA %2, %3, %0
$noreg = PATCHABLE_RET %1(s32)
...
---
name: test_rule943_id436_at_idx61329
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%2' }
- { reg: '$d1', virtual-reg: '%3' }
- { reg: '$d2', virtual-reg: '%4' }
body: |
bb.0.entry:
liveins: $d0, $d1, $d2
; CHECK-LABEL: name: test_rule943_id436_at_idx61329
; CHECK: liveins: $d0, $d1, $d2
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[FNMSUBDrrr:%[0-9]+]]:fpr64 = nofpexcept FNMSUBDrrr [[COPY2]], [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FNMSUBDrrr]]
%4:fpr(s64) = COPY $d2
%3:fpr(s64) = COPY $d1
%2:fpr(s64) = COPY $d0
%0:fpr(s64) = G_FNEG %4
%1:fpr(s64) = G_FMA %2, %3, %0
$noreg = PATCHABLE_RET %1(s64)
...
---
name: test_rule944_id3803_at_idx61417
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%2' }
- { reg: '$d1', virtual-reg: '%3' }
- { reg: '$d2', virtual-reg: '%4' }
body: |
bb.0.entry:
liveins: $d0, $d1, $d2
; CHECK-LABEL: name: test_rule944_id3803_at_idx61417
; CHECK: liveins: $d0, $d1, $d2
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[MULv8i8_:%[0-9]+]]:fpr64 = MULv8i8 [[COPY1]], [[COPY]]
; CHECK: [[ADDv8i8_:%[0-9]+]]:fpr64 = ADDv8i8 [[MULv8i8_]], [[COPY2]]
; CHECK: $noreg = PATCHABLE_RET [[ADDv8i8_]]
%4:fpr(<8 x s8>) = COPY $d2
%3:fpr(<8 x s8>) = COPY $d1
%2:fpr(<8 x s8>) = COPY $d0
%0:fpr(<8 x s8>) = G_MUL %3, %4
%1:fpr(<8 x s8>) = G_ADD %0, %2
$noreg = PATCHABLE_RET %1(<8 x s8>)
...
---
name: test_rule945_id3804_at_idx61505
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%2' }
- { reg: '$q1', virtual-reg: '%3' }
- { reg: '$q2', virtual-reg: '%4' }
body: |
bb.0.entry:
liveins: $q0, $q1, $q2
; CHECK-LABEL: name: test_rule945_id3804_at_idx61505
; CHECK: liveins: $q0, $q1, $q2
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[MULv16i8_:%[0-9]+]]:fpr128 = MULv16i8 [[COPY1]], [[COPY]]
; CHECK: [[ADDv16i8_:%[0-9]+]]:fpr128 = ADDv16i8 [[MULv16i8_]], [[COPY2]]
; CHECK: $noreg = PATCHABLE_RET [[ADDv16i8_]]
%4:fpr(<16 x s8>) = COPY $q2
%3:fpr(<16 x s8>) = COPY $q1
%2:fpr(<16 x s8>) = COPY $q0
%0:fpr(<16 x s8>) = G_MUL %3, %4
%1:fpr(<16 x s8>) = G_ADD %0, %2
$noreg = PATCHABLE_RET %1(<16 x s8>)
...
---
name: test_rule946_id3805_at_idx61593
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%2' }
- { reg: '$d1', virtual-reg: '%3' }
- { reg: '$d2', virtual-reg: '%4' }
body: |
bb.0.entry:
liveins: $d0, $d1, $d2
; CHECK-LABEL: name: test_rule946_id3805_at_idx61593
; CHECK: liveins: $d0, $d1, $d2
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[MULv4i16_:%[0-9]+]]:fpr64 = MULv4i16 [[COPY1]], [[COPY]]
; CHECK: [[ADDv4i16_:%[0-9]+]]:fpr64 = ADDv4i16 [[MULv4i16_]], [[COPY2]]
; CHECK: $noreg = PATCHABLE_RET [[ADDv4i16_]]
%4:fpr(<4 x s16>) = COPY $d2
%3:fpr(<4 x s16>) = COPY $d1
%2:fpr(<4 x s16>) = COPY $d0
%0:fpr(<4 x s16>) = G_MUL %3, %4
%1:fpr(<4 x s16>) = G_ADD %0, %2
$noreg = PATCHABLE_RET %1(<4 x s16>)
...
---
name: test_rule947_id3806_at_idx61681
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%2' }
- { reg: '$q1', virtual-reg: '%3' }
- { reg: '$q2', virtual-reg: '%4' }
body: |
bb.0.entry:
liveins: $q0, $q1, $q2
; CHECK-LABEL: name: test_rule947_id3806_at_idx61681
; CHECK: liveins: $q0, $q1, $q2
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[MULv8i16_:%[0-9]+]]:fpr128 = MULv8i16 [[COPY1]], [[COPY]]
; CHECK: [[ADDv8i16_:%[0-9]+]]:fpr128 = ADDv8i16 [[MULv8i16_]], [[COPY2]]
; CHECK: $noreg = PATCHABLE_RET [[ADDv8i16_]]
%4:fpr(<8 x s16>) = COPY $q2
%3:fpr(<8 x s16>) = COPY $q1
%2:fpr(<8 x s16>) = COPY $q0
%0:fpr(<8 x s16>) = G_MUL %3, %4
%1:fpr(<8 x s16>) = G_ADD %0, %2
$noreg = PATCHABLE_RET %1(<8 x s16>)
...
---
name: test_rule950_id3869_at_idx61945
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%2' }
- { reg: '$d0', virtual-reg: '%3' }
body: |
bb.0.entry:
liveins: $q0, $d0
; CHECK-LABEL: name: test_rule950_id3869_at_idx61945
; CHECK: liveins: $q0, $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[SADDWv8i8_v8i16_:%[0-9]+]]:fpr128 = SADDWv8i8_v8i16 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[SADDWv8i8_v8i16_]]
%3:fpr(<8 x s8>) = COPY $d0
%2:fpr(<8 x s16>) = COPY $q0
%0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>)
%1:fpr(<8 x s16>) = G_ADD %0, %2
$noreg = PATCHABLE_RET %1(<8 x s16>)
...
---
name: test_rule951_id3871_at_idx62021
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%2' }
- { reg: '$d0', virtual-reg: '%3' }
body: |
bb.0.entry:
liveins: $q0, $d0
; CHECK-LABEL: name: test_rule951_id3871_at_idx62021
; CHECK: liveins: $q0, $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[SADDWv4i16_v4i32_:%[0-9]+]]:fpr128 = SADDWv4i16_v4i32 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[SADDWv4i16_v4i32_]]
%3:fpr(<4 x s16>) = COPY $d0
%2:fpr(<4 x s32>) = COPY $q0
%0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>)
%1:fpr(<4 x s32>) = G_ADD %0, %2
$noreg = PATCHABLE_RET %1(<4 x s32>)
...
---
name: test_rule952_id3873_at_idx62097
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%2' }
- { reg: '$d0', virtual-reg: '%3' }
body: |
bb.0.entry:
liveins: $q0, $d0
; CHECK-LABEL: name: test_rule952_id3873_at_idx62097
; CHECK: liveins: $q0, $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[SADDWv2i32_v2i64_:%[0-9]+]]:fpr128 = SADDWv2i32_v2i64 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[SADDWv2i32_v2i64_]]
%3:fpr(<2 x s32>) = COPY $d0
%2:fpr(<2 x s64>) = COPY $q0
%0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>)
%1:fpr(<2 x s64>) = G_ADD %0, %2
$noreg = PATCHABLE_RET %1(<2 x s64>)
...
---
name: test_rule953_id3887_at_idx62173
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%2' }
- { reg: '$d0', virtual-reg: '%3' }
body: |
bb.0.entry:
liveins: $q0, $d0
; CHECK-LABEL: name: test_rule953_id3887_at_idx62173
; CHECK: liveins: $q0, $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[UADDWv8i8_v8i16_:%[0-9]+]]:fpr128 = UADDWv8i8_v8i16 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[UADDWv8i8_v8i16_]]
%3:fpr(<8 x s8>) = COPY $d0
%2:fpr(<8 x s16>) = COPY $q0
%0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>)
%1:fpr(<8 x s16>) = G_ADD %0, %2
$noreg = PATCHABLE_RET %1(<8 x s16>)
...
---
name: test_rule954_id3889_at_idx62249
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%2' }
- { reg: '$d0', virtual-reg: '%3' }
body: |
bb.0.entry:
liveins: $q0, $d0
; CHECK-LABEL: name: test_rule954_id3889_at_idx62249
; CHECK: liveins: $q0, $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[UADDWv4i16_v4i32_:%[0-9]+]]:fpr128 = UADDWv4i16_v4i32 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[UADDWv4i16_v4i32_]]
%3:fpr(<4 x s16>) = COPY $d0
%2:fpr(<4 x s32>) = COPY $q0
%0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>)
%1:fpr(<4 x s32>) = G_ADD %0, %2
$noreg = PATCHABLE_RET %1(<4 x s32>)
...
---
name: test_rule955_id3891_at_idx62325
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%2' }
- { reg: '$d0', virtual-reg: '%3' }
body: |
bb.0.entry:
liveins: $q0, $d0
; CHECK-LABEL: name: test_rule955_id3891_at_idx62325
; CHECK: liveins: $q0, $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[UADDWv2i32_v2i64_:%[0-9]+]]:fpr128 = UADDWv2i32_v2i64 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[UADDWv2i32_v2i64_]]
%3:fpr(<2 x s32>) = COPY $d0
%2:fpr(<2 x s64>) = COPY $q0
%0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>)
%1:fpr(<2 x s64>) = G_ADD %0, %2
$noreg = PATCHABLE_RET %1(<2 x s64>)
...
---
name: test_rule956_id927_at_idx62401
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%2' }
- { reg: '$d1', virtual-reg: '%3' }
- { reg: '$d2', virtual-reg: '%4' }
body: |
bb.0.entry:
liveins: $d0, $d1, $d2
; CHECK-LABEL: name: test_rule956_id927_at_idx62401
; CHECK: liveins: $d0, $d1, $d2
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[MULv8i8_:%[0-9]+]]:fpr64 = MULv8i8 [[COPY1]], [[COPY]]
; CHECK: [[ADDv8i8_:%[0-9]+]]:fpr64 = ADDv8i8 [[COPY2]], [[MULv8i8_]]
; CHECK: $noreg = PATCHABLE_RET [[ADDv8i8_]]
%4:fpr(<8 x s8>) = COPY $d2
%3:fpr(<8 x s8>) = COPY $d1
%2:fpr(<8 x s8>) = COPY $d0
%0:fpr(<8 x s8>) = G_MUL %3, %4
%1:fpr(<8 x s8>) = G_ADD %2, %0
$noreg = PATCHABLE_RET %1(<8 x s8>)
...
---
name: test_rule957_id928_at_idx62489
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%2' }
- { reg: '$q1', virtual-reg: '%3' }
- { reg: '$q2', virtual-reg: '%4' }
body: |
bb.0.entry:
liveins: $q0, $q1, $q2
; CHECK-LABEL: name: test_rule957_id928_at_idx62489
; CHECK: liveins: $q0, $q1, $q2
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[MULv16i8_:%[0-9]+]]:fpr128 = MULv16i8 [[COPY1]], [[COPY]]
; CHECK: [[ADDv16i8_:%[0-9]+]]:fpr128 = ADDv16i8 [[COPY2]], [[MULv16i8_]]
; CHECK: $noreg = PATCHABLE_RET [[ADDv16i8_]]
%4:fpr(<16 x s8>) = COPY $q2
%3:fpr(<16 x s8>) = COPY $q1
%2:fpr(<16 x s8>) = COPY $q0
%0:fpr(<16 x s8>) = G_MUL %3, %4
%1:fpr(<16 x s8>) = G_ADD %2, %0
$noreg = PATCHABLE_RET %1(<16 x s8>)
...
---
name: test_rule958_id929_at_idx62577
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%2' }
- { reg: '$d1', virtual-reg: '%3' }
- { reg: '$d2', virtual-reg: '%4' }
body: |
bb.0.entry:
liveins: $d0, $d1, $d2
; CHECK-LABEL: name: test_rule958_id929_at_idx62577
; CHECK: liveins: $d0, $d1, $d2
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[MULv4i16_:%[0-9]+]]:fpr64 = MULv4i16 [[COPY1]], [[COPY]]
; CHECK: [[ADDv4i16_:%[0-9]+]]:fpr64 = ADDv4i16 [[COPY2]], [[MULv4i16_]]
; CHECK: $noreg = PATCHABLE_RET [[ADDv4i16_]]
%4:fpr(<4 x s16>) = COPY $d2
%3:fpr(<4 x s16>) = COPY $d1
%2:fpr(<4 x s16>) = COPY $d0
%0:fpr(<4 x s16>) = G_MUL %3, %4
%1:fpr(<4 x s16>) = G_ADD %2, %0
$noreg = PATCHABLE_RET %1(<4 x s16>)
...
---
name: test_rule959_id930_at_idx62665
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%2' }
- { reg: '$q1', virtual-reg: '%3' }
- { reg: '$q2', virtual-reg: '%4' }
body: |
bb.0.entry:
liveins: $q0, $q1, $q2
; CHECK-LABEL: name: test_rule959_id930_at_idx62665
; CHECK: liveins: $q0, $q1, $q2
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[MULv8i16_:%[0-9]+]]:fpr128 = MULv8i16 [[COPY1]], [[COPY]]
; CHECK: [[ADDv8i16_:%[0-9]+]]:fpr128 = ADDv8i16 [[COPY2]], [[MULv8i16_]]
; CHECK: $noreg = PATCHABLE_RET [[ADDv8i16_]]
%4:fpr(<8 x s16>) = COPY $q2
%3:fpr(<8 x s16>) = COPY $q1
%2:fpr(<8 x s16>) = COPY $q0
%0:fpr(<8 x s16>) = G_MUL %3, %4
%1:fpr(<8 x s16>) = G_ADD %2, %0
$noreg = PATCHABLE_RET %1(<8 x s16>)
...
---
name: test_rule962_id1272_at_idx62929
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%2' }
- { reg: '$d0', virtual-reg: '%3' }
body: |
bb.0.entry:
liveins: $q0, $d0
; CHECK-LABEL: name: test_rule962_id1272_at_idx62929
; CHECK: liveins: $q0, $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[SADDWv8i8_v8i16_:%[0-9]+]]:fpr128 = SADDWv8i8_v8i16 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[SADDWv8i8_v8i16_]]
%3:fpr(<8 x s8>) = COPY $d0
%2:fpr(<8 x s16>) = COPY $q0
%0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>)
%1:fpr(<8 x s16>) = G_ADD %2, %0
$noreg = PATCHABLE_RET %1(<8 x s16>)
...
---
name: test_rule963_id1274_at_idx63005
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%2' }
- { reg: '$d0', virtual-reg: '%3' }
body: |
bb.0.entry:
liveins: $q0, $d0
; CHECK-LABEL: name: test_rule963_id1274_at_idx63005
; CHECK: liveins: $q0, $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[SADDWv4i16_v4i32_:%[0-9]+]]:fpr128 = SADDWv4i16_v4i32 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[SADDWv4i16_v4i32_]]
%3:fpr(<4 x s16>) = COPY $d0
%2:fpr(<4 x s32>) = COPY $q0
%0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>)
%1:fpr(<4 x s32>) = G_ADD %2, %0
$noreg = PATCHABLE_RET %1(<4 x s32>)
...
---
name: test_rule964_id1276_at_idx63081
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%2' }
- { reg: '$d0', virtual-reg: '%3' }
body: |
bb.0.entry:
liveins: $q0, $d0
; CHECK-LABEL: name: test_rule964_id1276_at_idx63081
; CHECK: liveins: $q0, $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[SADDWv2i32_v2i64_:%[0-9]+]]:fpr128 = SADDWv2i32_v2i64 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[SADDWv2i32_v2i64_]]
%3:fpr(<2 x s32>) = COPY $d0
%2:fpr(<2 x s64>) = COPY $q0
%0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>)
%1:fpr(<2 x s64>) = G_ADD %2, %0
$noreg = PATCHABLE_RET %1(<2 x s64>)
...
---
name: test_rule965_id1332_at_idx63157
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%2' }
- { reg: '$d0', virtual-reg: '%3' }
body: |
bb.0.entry:
liveins: $q0, $d0
; CHECK-LABEL: name: test_rule965_id1332_at_idx63157
; CHECK: liveins: $q0, $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[UADDWv8i8_v8i16_:%[0-9]+]]:fpr128 = UADDWv8i8_v8i16 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[UADDWv8i8_v8i16_]]
%3:fpr(<8 x s8>) = COPY $d0
%2:fpr(<8 x s16>) = COPY $q0
%0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>)
%1:fpr(<8 x s16>) = G_ADD %2, %0
$noreg = PATCHABLE_RET %1(<8 x s16>)
...
---
name: test_rule966_id1334_at_idx63233
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%2' }
- { reg: '$d0', virtual-reg: '%3' }
body: |
bb.0.entry:
liveins: $q0, $d0
; CHECK-LABEL: name: test_rule966_id1334_at_idx63233
; CHECK: liveins: $q0, $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[UADDWv4i16_v4i32_:%[0-9]+]]:fpr128 = UADDWv4i16_v4i32 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[UADDWv4i16_v4i32_]]
%3:fpr(<4 x s16>) = COPY $d0
%2:fpr(<4 x s32>) = COPY $q0
%0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>)
%1:fpr(<4 x s32>) = G_ADD %2, %0
$noreg = PATCHABLE_RET %1(<4 x s32>)
...
---
name: test_rule967_id1336_at_idx63309
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%2' }
- { reg: '$d0', virtual-reg: '%3' }
body: |
bb.0.entry:
liveins: $q0, $d0
; CHECK-LABEL: name: test_rule967_id1336_at_idx63309
; CHECK: liveins: $q0, $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[UADDWv2i32_v2i64_:%[0-9]+]]:fpr128 = UADDWv2i32_v2i64 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[UADDWv2i32_v2i64_]]
%3:fpr(<2 x s32>) = COPY $d0
%2:fpr(<2 x s64>) = COPY $q0
%0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>)
%1:fpr(<2 x s64>) = G_ADD %2, %0
$noreg = PATCHABLE_RET %1(<2 x s64>)
...
---
name: test_rule977_id933_at_idx64051
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%2' }
- { reg: '$d1', virtual-reg: '%3' }
- { reg: '$d2', virtual-reg: '%4' }
body: |
bb.0.entry:
liveins: $d0, $d1, $d2
; CHECK-LABEL: name: test_rule977_id933_at_idx64051
; CHECK: liveins: $d0, $d1, $d2
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[MULv8i8_:%[0-9]+]]:fpr64 = MULv8i8 [[COPY1]], [[COPY]]
; CHECK: [[SUBv8i8_:%[0-9]+]]:fpr64 = SUBv8i8 [[COPY2]], [[MULv8i8_]]
; CHECK: $noreg = PATCHABLE_RET [[SUBv8i8_]]
%4:fpr(<8 x s8>) = COPY $d2
%3:fpr(<8 x s8>) = COPY $d1
%2:fpr(<8 x s8>) = COPY $d0
%0:fpr(<8 x s8>) = G_MUL %3, %4
%1:fpr(<8 x s8>) = G_SUB %2, %0
$noreg = PATCHABLE_RET %1(<8 x s8>)
...
---
name: test_rule978_id934_at_idx64139
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%2' }
- { reg: '$q1', virtual-reg: '%3' }
- { reg: '$q2', virtual-reg: '%4' }
body: |
bb.0.entry:
liveins: $q0, $q1, $q2
; CHECK-LABEL: name: test_rule978_id934_at_idx64139
; CHECK: liveins: $q0, $q1, $q2
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[MULv16i8_:%[0-9]+]]:fpr128 = MULv16i8 [[COPY1]], [[COPY]]
; CHECK: [[SUBv16i8_:%[0-9]+]]:fpr128 = SUBv16i8 [[COPY2]], [[MULv16i8_]]
; CHECK: $noreg = PATCHABLE_RET [[SUBv16i8_]]
%4:fpr(<16 x s8>) = COPY $q2
%3:fpr(<16 x s8>) = COPY $q1
%2:fpr(<16 x s8>) = COPY $q0
%0:fpr(<16 x s8>) = G_MUL %3, %4
%1:fpr(<16 x s8>) = G_SUB %2, %0
$noreg = PATCHABLE_RET %1(<16 x s8>)
...
---
name: test_rule979_id935_at_idx64227
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%2' }
- { reg: '$d1', virtual-reg: '%3' }
- { reg: '$d2', virtual-reg: '%4' }
body: |
bb.0.entry:
liveins: $d0, $d1, $d2
; CHECK-LABEL: name: test_rule979_id935_at_idx64227
; CHECK: liveins: $d0, $d1, $d2
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[MULv4i16_:%[0-9]+]]:fpr64 = MULv4i16 [[COPY1]], [[COPY]]
; CHECK: [[SUBv4i16_:%[0-9]+]]:fpr64 = SUBv4i16 [[COPY2]], [[MULv4i16_]]
; CHECK: $noreg = PATCHABLE_RET [[SUBv4i16_]]
%4:fpr(<4 x s16>) = COPY $d2
%3:fpr(<4 x s16>) = COPY $d1
%2:fpr(<4 x s16>) = COPY $d0
%0:fpr(<4 x s16>) = G_MUL %3, %4
%1:fpr(<4 x s16>) = G_SUB %2, %0
$noreg = PATCHABLE_RET %1(<4 x s16>)
...
---
name: test_rule980_id936_at_idx64315
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%2' }
- { reg: '$q1', virtual-reg: '%3' }
- { reg: '$q2', virtual-reg: '%4' }
body: |
bb.0.entry:
liveins: $q0, $q1, $q2
; CHECK-LABEL: name: test_rule980_id936_at_idx64315
; CHECK: liveins: $q0, $q1, $q2
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[MULv8i16_:%[0-9]+]]:fpr128 = MULv8i16 [[COPY1]], [[COPY]]
; CHECK: [[SUBv8i16_:%[0-9]+]]:fpr128 = SUBv8i16 [[COPY2]], [[MULv8i16_]]
; CHECK: $noreg = PATCHABLE_RET [[SUBv8i16_]]
%4:fpr(<8 x s16>) = COPY $q2
%3:fpr(<8 x s16>) = COPY $q1
%2:fpr(<8 x s16>) = COPY $q0
%0:fpr(<8 x s16>) = G_MUL %3, %4
%1:fpr(<8 x s16>) = G_SUB %2, %0
$noreg = PATCHABLE_RET %1(<8 x s16>)
...
---
name: test_rule983_id1314_at_idx64579
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%2' }
- { reg: '$d0', virtual-reg: '%3' }
body: |
bb.0.entry:
liveins: $q0, $d0
; CHECK-LABEL: name: test_rule983_id1314_at_idx64579
; CHECK: liveins: $q0, $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[SSUBWv8i8_v8i16_:%[0-9]+]]:fpr128 = SSUBWv8i8_v8i16 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[SSUBWv8i8_v8i16_]]
%3:fpr(<8 x s8>) = COPY $d0
%2:fpr(<8 x s16>) = COPY $q0
%0:fpr(<8 x s16>) = G_SEXT %3(<8 x s8>)
%1:fpr(<8 x s16>) = G_SUB %2, %0
$noreg = PATCHABLE_RET %1(<8 x s16>)
...
---
name: test_rule984_id1316_at_idx64655
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%2' }
- { reg: '$d0', virtual-reg: '%3' }
body: |
bb.0.entry:
liveins: $q0, $d0
; CHECK-LABEL: name: test_rule984_id1316_at_idx64655
; CHECK: liveins: $q0, $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[SSUBWv4i16_v4i32_:%[0-9]+]]:fpr128 = SSUBWv4i16_v4i32 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[SSUBWv4i16_v4i32_]]
%3:fpr(<4 x s16>) = COPY $d0
%2:fpr(<4 x s32>) = COPY $q0
%0:fpr(<4 x s32>) = G_SEXT %3(<4 x s16>)
%1:fpr(<4 x s32>) = G_SUB %2, %0
$noreg = PATCHABLE_RET %1(<4 x s32>)
...
---
name: test_rule985_id1318_at_idx64731
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%2' }
- { reg: '$d0', virtual-reg: '%3' }
body: |
bb.0.entry:
liveins: $q0, $d0
; CHECK-LABEL: name: test_rule985_id1318_at_idx64731
; CHECK: liveins: $q0, $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[SSUBWv2i32_v2i64_:%[0-9]+]]:fpr128 = SSUBWv2i32_v2i64 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[SSUBWv2i32_v2i64_]]
%3:fpr(<2 x s32>) = COPY $d0
%2:fpr(<2 x s64>) = COPY $q0
%0:fpr(<2 x s64>) = G_SEXT %3(<2 x s32>)
%1:fpr(<2 x s64>) = G_SUB %2, %0
$noreg = PATCHABLE_RET %1(<2 x s64>)
...
---
name: test_rule986_id1362_at_idx64807
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%2' }
- { reg: '$d0', virtual-reg: '%3' }
body: |
bb.0.entry:
liveins: $q0, $d0
; CHECK-LABEL: name: test_rule986_id1362_at_idx64807
; CHECK: liveins: $q0, $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[USUBWv8i8_v8i16_:%[0-9]+]]:fpr128 = USUBWv8i8_v8i16 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[USUBWv8i8_v8i16_]]
%3:fpr(<8 x s8>) = COPY $d0
%2:fpr(<8 x s16>) = COPY $q0
%0:fpr(<8 x s16>) = G_ZEXT %3(<8 x s8>)
%1:fpr(<8 x s16>) = G_SUB %2, %0
$noreg = PATCHABLE_RET %1(<8 x s16>)
...
---
name: test_rule987_id1364_at_idx64883
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%2' }
- { reg: '$d0', virtual-reg: '%3' }
body: |
bb.0.entry:
liveins: $q0, $d0
; CHECK-LABEL: name: test_rule987_id1364_at_idx64883
; CHECK: liveins: $q0, $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[USUBWv4i16_v4i32_:%[0-9]+]]:fpr128 = USUBWv4i16_v4i32 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[USUBWv4i16_v4i32_]]
%3:fpr(<4 x s16>) = COPY $d0
%2:fpr(<4 x s32>) = COPY $q0
%0:fpr(<4 x s32>) = G_ZEXT %3(<4 x s16>)
%1:fpr(<4 x s32>) = G_SUB %2, %0
$noreg = PATCHABLE_RET %1(<4 x s32>)
...
---
name: test_rule988_id1366_at_idx64959
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%2' }
- { reg: '$d0', virtual-reg: '%3' }
body: |
bb.0.entry:
liveins: $q0, $d0
; CHECK-LABEL: name: test_rule988_id1366_at_idx64959
; CHECK: liveins: $q0, $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[USUBWv2i32_v2i64_:%[0-9]+]]:fpr128 = USUBWv2i32_v2i64 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[USUBWv2i32_v2i64_]]
%3:fpr(<2 x s32>) = COPY $d0
%2:fpr(<2 x s64>) = COPY $q0
%0:fpr(<2 x s64>) = G_ZEXT %3(<2 x s32>)
%1:fpr(<2 x s64>) = G_SUB %2, %0
$noreg = PATCHABLE_RET %1(<2 x s64>)
...
---
name: test_rule990_id432_at_idx65123
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
liveins:
- { reg: '$s0', virtual-reg: '%2' }
- { reg: '$s1', virtual-reg: '%3' }
- { reg: '$s2', virtual-reg: '%4' }
body: |
bb.0.entry:
liveins: $s0, $s1, $s2
; CHECK-LABEL: name: test_rule990_id432_at_idx65123
; CHECK: liveins: $s0, $s1, $s2
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s2
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1
; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s0
; CHECK: [[FNMADDSrrr:%[0-9]+]]:fpr32 = nofpexcept FNMADDSrrr [[COPY2]], [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FNMADDSrrr]]
%4:fpr(s32) = COPY $s2
%3:fpr(s32) = COPY $s1
%2:fpr(s32) = COPY $s0
%0:fpr(s32) = G_FMA %2, %3, %4
%1:fpr(s32) = G_FNEG %0
$noreg = PATCHABLE_RET %1(s32)
...
---
name: test_rule991_id433_at_idx65211
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
- { id: 4, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%2' }
- { reg: '$d1', virtual-reg: '%3' }
- { reg: '$d2', virtual-reg: '%4' }
body: |
bb.0.entry:
liveins: $d0, $d1, $d2
; CHECK-LABEL: name: test_rule991_id433_at_idx65211
; CHECK: liveins: $d0, $d1, $d2
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[FNMADDDrrr:%[0-9]+]]:fpr64 = nofpexcept FNMADDDrrr [[COPY2]], [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FNMADDDrrr]]
%4:fpr(s64) = COPY $d2
%3:fpr(s64) = COPY $d1
%2:fpr(s64) = COPY $d0
%0:fpr(s64) = G_FMA %2, %3, %4
%1:fpr(s64) = G_FNEG %0
$noreg = PATCHABLE_RET %1(s64)
...
---
name: test_rule993_id420_at_idx65375
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
liveins:
- { reg: '$s0', virtual-reg: '%2' }
- { reg: '$s1', virtual-reg: '%3' }
body: |
bb.0.entry:
liveins: $s0, $s1
; CHECK-LABEL: name: test_rule993_id420_at_idx65375
; CHECK: liveins: $s0, $s1
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s1
; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
; CHECK: [[FNMULSrr:%[0-9]+]]:fpr32 = nofpexcept FNMULSrr [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FNMULSrr]]
%3:fpr(s32) = COPY $s1
%2:fpr(s32) = COPY $s0
%0:fpr(s32) = G_FMUL %2, %3
%1:fpr(s32) = G_FNEG %0
$noreg = PATCHABLE_RET %1(s32)
...
---
name: test_rule994_id421_at_idx65451
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%2' }
- { reg: '$d1', virtual-reg: '%3' }
body: |
bb.0.entry:
liveins: $d0, $d1
; CHECK-LABEL: name: test_rule994_id421_at_idx65451
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[FNMULDrr:%[0-9]+]]:fpr64 = nofpexcept FNMULDrr [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FNMULDrr]]
%3:fpr(s64) = COPY $d1
%2:fpr(s64) = COPY $d0
%0:fpr(s64) = G_FMUL %2, %3
%1:fpr(s64) = G_FNEG %0
$noreg = PATCHABLE_RET %1(s64)
...
---
name: test_rule1230_id2969_at_idx81784
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
liveins:
- { reg: '$x0', virtual-reg: '%0' }
- { reg: '$x1', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $x0, $x1
; CHECK-LABEL: name: test_rule1230_id2969_at_idx81784
; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
; CHECK: [[COPY1:%[0-9]+]]:gpr64all = COPY $x0
; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]]
; CHECK: ST1Onev8b [[COPY2]], [[COPY]] :: (store (<8 x s8>))
; CHECK: $noreg = PATCHABLE_RET
%1:gpr(p0) = COPY $x1
%0:gpr(<8 x s8>) = COPY $x0
G_STORE %0(<8 x s8>), %1(p0) :: (store (<8 x s8>))
$noreg = PATCHABLE_RET
...
---
name: test_rule1231_id2970_at_idx81816
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
liveins:
- { reg: '$x0', virtual-reg: '%0' }
- { reg: '$x1', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $x0, $x1
; CHECK-LABEL: name: test_rule1231_id2970_at_idx81816
; CHECK: liveins: $x0, $x1
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x1
; CHECK: [[COPY1:%[0-9]+]]:gpr64all = COPY $x0
; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]]
; CHECK: ST1Onev4h [[COPY2]], [[COPY]] :: (store (<4 x s16>))
; CHECK: $noreg = PATCHABLE_RET
%1:gpr(p0) = COPY $x1
%0:gpr(<4 x s16>) = COPY $x0
G_STORE %0(<4 x s16>), %1(p0) :: (store (<4 x s16>))
$noreg = PATCHABLE_RET
...
---
name: test_rule1239_id894_at_idx82201
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
- { reg: '$d1', virtual-reg: '%2' }
- { reg: '$d2', virtual-reg: '%3' }
body: |
bb.0.entry:
liveins: $d0, $d1, $d2
; CHECK-LABEL: name: test_rule1239_id894_at_idx82201
; CHECK: liveins: $d0, $d1, $d2
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d2
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[FMLAv2f32_:%[0-9]+]]:fpr64 = nofpexcept FMLAv2f32 [[COPY]], [[COPY1]], [[COPY2]]
; CHECK: $noreg = PATCHABLE_RET [[FMLAv2f32_]]
%3:fpr(<2 x s32>) = COPY $d2
%2:fpr(<2 x s32>) = COPY $d1
%1:fpr(<2 x s32>) = COPY $d0
%0:fpr(<2 x s32>) = G_FMA %1, %2, %3
$noreg = PATCHABLE_RET %0(<2 x s32>)
...
---
name: test_rule1240_id895_at_idx82269
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%1' }
- { reg: '$q1', virtual-reg: '%2' }
- { reg: '$q2', virtual-reg: '%3' }
body: |
bb.0.entry:
liveins: $q0, $q1, $q2
; CHECK-LABEL: name: test_rule1240_id895_at_idx82269
; CHECK: liveins: $q0, $q1, $q2
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[FMLAv4f32_:%[0-9]+]]:fpr128 = nofpexcept FMLAv4f32 [[COPY]], [[COPY1]], [[COPY2]]
; CHECK: $noreg = PATCHABLE_RET [[FMLAv4f32_]]
%3:fpr(<4 x s32>) = COPY $q2
%2:fpr(<4 x s32>) = COPY $q1
%1:fpr(<4 x s32>) = COPY $q0
%0:fpr(<4 x s32>) = G_FMA %1, %2, %3
$noreg = PATCHABLE_RET %0(<4 x s32>)
...
---
name: test_rule1241_id896_at_idx82337
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
- { id: 3, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%1' }
- { reg: '$q1', virtual-reg: '%2' }
- { reg: '$q2', virtual-reg: '%3' }
body: |
bb.0.entry:
liveins: $q0, $q1, $q2
; CHECK-LABEL: name: test_rule1241_id896_at_idx82337
; CHECK: liveins: $q0, $q1, $q2
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q2
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY2:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[FMLAv2f64_:%[0-9]+]]:fpr128 = nofpexcept FMLAv2f64 [[COPY]], [[COPY1]], [[COPY2]]
; CHECK: $noreg = PATCHABLE_RET [[FMLAv2f64_]]
%3:fpr(<2 x s64>) = COPY $q2
%2:fpr(<2 x s64>) = COPY $q1
%1:fpr(<2 x s64>) = COPY $q0
%0:fpr(<2 x s64>) = G_FMA %1, %2, %3
$noreg = PATCHABLE_RET %0(<2 x s64>)
...
---
name: test_rule1244_id751_at_idx82487
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
- { reg: '$d1', virtual-reg: '%2' }
body: |
bb.0.entry:
liveins: $d0, $d1
; CHECK-LABEL: name: test_rule1244_id751_at_idx82487
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[ADDv8i8_:%[0-9]+]]:fpr64 = ADDv8i8 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[ADDv8i8_]]
%2:fpr(<8 x s8>) = COPY $d1
%1:fpr(<8 x s8>) = COPY $d0
%0:fpr(<8 x s8>) = G_ADD %1, %2
$noreg = PATCHABLE_RET %0(<8 x s8>)
...
---
name: test_rule1245_id752_at_idx82530
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%1' }
- { reg: '$q1', virtual-reg: '%2' }
body: |
bb.0.entry:
liveins: $q0, $q1
; CHECK-LABEL: name: test_rule1245_id752_at_idx82530
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[ADDv16i8_:%[0-9]+]]:fpr128 = ADDv16i8 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[ADDv16i8_]]
%2:fpr(<16 x s8>) = COPY $q1
%1:fpr(<16 x s8>) = COPY $q0
%0:fpr(<16 x s8>) = G_ADD %1, %2
$noreg = PATCHABLE_RET %0(<16 x s8>)
...
---
name: test_rule1246_id753_at_idx82573
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
- { reg: '$d1', virtual-reg: '%2' }
body: |
bb.0.entry:
liveins: $d0, $d1
; CHECK-LABEL: name: test_rule1246_id753_at_idx82573
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[ADDv4i16_:%[0-9]+]]:fpr64 = ADDv4i16 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[ADDv4i16_]]
%2:fpr(<4 x s16>) = COPY $d1
%1:fpr(<4 x s16>) = COPY $d0
%0:fpr(<4 x s16>) = G_ADD %1, %2
$noreg = PATCHABLE_RET %0(<4 x s16>)
...
---
name: test_rule1247_id754_at_idx82616
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%1' }
- { reg: '$q1', virtual-reg: '%2' }
body: |
bb.0.entry:
liveins: $q0, $q1
; CHECK-LABEL: name: test_rule1247_id754_at_idx82616
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[ADDv8i16_:%[0-9]+]]:fpr128 = ADDv8i16 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[ADDv8i16_]]
%2:fpr(<8 x s16>) = COPY $q1
%1:fpr(<8 x s16>) = COPY $q0
%0:fpr(<8 x s16>) = G_ADD %1, %2
$noreg = PATCHABLE_RET %0(<8 x s16>)
...
---
name: test_rule1254_id1162_at_idx82913
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
- { reg: '$d1', virtual-reg: '%2' }
body: |
bb.0.entry:
liveins: $d0, $d1
; CHECK-LABEL: name: test_rule1254_id1162_at_idx82913
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[ANDv8i8_]]
%2:fpr(<8 x s8>) = COPY $d1
%1:fpr(<8 x s8>) = COPY $d0
%0:fpr(<8 x s8>) = G_AND %1, %2
$noreg = PATCHABLE_RET %0(<8 x s8>)
...
---
name: test_rule1255_id1163_at_idx82956
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%1' }
- { reg: '$q1', virtual-reg: '%2' }
body: |
bb.0.entry:
liveins: $q0, $q1
; CHECK-LABEL: name: test_rule1255_id1163_at_idx82956
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[ANDv16i8_:%[0-9]+]]:fpr128 = ANDv16i8 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[ANDv16i8_]]
%2:fpr(<16 x s8>) = COPY $q1
%1:fpr(<16 x s8>) = COPY $q0
%0:fpr(<16 x s8>) = G_AND %1, %2
$noreg = PATCHABLE_RET %0(<16 x s8>)
...
---
name: test_rule1256_id1751_at_idx82999
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
- { reg: '$d1', virtual-reg: '%2' }
body: |
bb.0.entry:
liveins: $d0, $d1
; CHECK-LABEL: name: test_rule1256_id1751_at_idx82999
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[ANDv8i8_:%[0-9]+]]:fpr64 = ANDv8i8 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[ANDv8i8_]]
%2:fpr(<4 x s16>) = COPY $d1
%1:fpr(<4 x s16>) = COPY $d0
%0:fpr(<4 x s16>) = G_AND %1, %2
$noreg = PATCHABLE_RET %0(<4 x s16>)
...
---
name: test_rule1259_id1754_at_idx83128
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%1' }
- { reg: '$q1', virtual-reg: '%2' }
body: |
bb.0.entry:
liveins: $q0, $q1
; CHECK-LABEL: name: test_rule1259_id1754_at_idx83128
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[ANDv16i8_:%[0-9]+]]:fpr128 = ANDv16i8 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[ANDv16i8_]]
%2:fpr(<8 x s16>) = COPY $q1
%1:fpr(<8 x s16>) = COPY $q0
%0:fpr(<8 x s16>) = G_AND %1, %2
$noreg = PATCHABLE_RET %0(<8 x s16>)
...
---
name: test_rule1268_id829_at_idx83513
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
- { reg: '$d1', virtual-reg: '%2' }
body: |
bb.0.entry:
liveins: $d0, $d1
; CHECK-LABEL: name: test_rule1268_id829_at_idx83513
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[FADDv2f32_:%[0-9]+]]:fpr64 = nofpexcept FADDv2f32 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FADDv2f32_]]
%2:fpr(<2 x s32>) = COPY $d1
%1:fpr(<2 x s32>) = COPY $d0
%0:fpr(<2 x s32>) = G_FADD %1, %2
$noreg = PATCHABLE_RET %0(<2 x s32>)
...
---
name: test_rule1269_id830_at_idx83556
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%1' }
- { reg: '$q1', virtual-reg: '%2' }
body: |
bb.0.entry:
liveins: $q0, $q1
; CHECK-LABEL: name: test_rule1269_id830_at_idx83556
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[FADDv4f32_:%[0-9]+]]:fpr128 = nofpexcept FADDv4f32 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FADDv4f32_]]
%2:fpr(<4 x s32>) = COPY $q1
%1:fpr(<4 x s32>) = COPY $q0
%0:fpr(<4 x s32>) = G_FADD %1, %2
$noreg = PATCHABLE_RET %0(<4 x s32>)
...
---
name: test_rule1270_id831_at_idx83599
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%1' }
- { reg: '$q1', virtual-reg: '%2' }
body: |
bb.0.entry:
liveins: $q0, $q1
; CHECK-LABEL: name: test_rule1270_id831_at_idx83599
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[FADDv2f64_:%[0-9]+]]:fpr128 = nofpexcept FADDv2f64 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FADDv2f64_]]
%2:fpr(<2 x s64>) = COPY $q1
%1:fpr(<2 x s64>) = COPY $q0
%0:fpr(<2 x s64>) = G_FADD %1, %2
$noreg = PATCHABLE_RET %0(<2 x s64>)
...
---
name: test_rule1276_id849_at_idx83857
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
- { reg: '$d1', virtual-reg: '%2' }
body: |
bb.0.entry:
liveins: $d0, $d1
; CHECK-LABEL: name: test_rule1276_id849_at_idx83857
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[FDIVv2f32_:%[0-9]+]]:fpr64 = nofpexcept FDIVv2f32 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FDIVv2f32_]]
%2:fpr(<2 x s32>) = COPY $d1
%1:fpr(<2 x s32>) = COPY $d0
%0:fpr(<2 x s32>) = G_FDIV %1, %2
$noreg = PATCHABLE_RET %0(<2 x s32>)
...
---
name: test_rule1277_id850_at_idx83900
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%1' }
- { reg: '$q1', virtual-reg: '%2' }
body: |
bb.0.entry:
liveins: $q0, $q1
; CHECK-LABEL: name: test_rule1277_id850_at_idx83900
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[FDIVv4f32_:%[0-9]+]]:fpr128 = nofpexcept FDIVv4f32 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FDIVv4f32_]]
%2:fpr(<4 x s32>) = COPY $q1
%1:fpr(<4 x s32>) = COPY $q0
%0:fpr(<4 x s32>) = G_FDIV %1, %2
$noreg = PATCHABLE_RET %0(<4 x s32>)
...
---
name: test_rule1278_id851_at_idx83943
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%1' }
- { reg: '$q1', virtual-reg: '%2' }
body: |
bb.0.entry:
liveins: $q0, $q1
; CHECK-LABEL: name: test_rule1278_id851_at_idx83943
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[FDIVv2f64_:%[0-9]+]]:fpr128 = nofpexcept FDIVv2f64 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FDIVv2f64_]]
%2:fpr(<2 x s64>) = COPY $q1
%1:fpr(<2 x s64>) = COPY $q0
%0:fpr(<2 x s64>) = G_FDIV %1, %2
$noreg = PATCHABLE_RET %0(<2 x s64>)
...
---
name: test_rule1284_id909_at_idx84201
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
- { reg: '$d1', virtual-reg: '%2' }
body: |
bb.0.entry:
liveins: $d0, $d1
; CHECK-LABEL: name: test_rule1284_id909_at_idx84201
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[FMULv2f32_:%[0-9]+]]:fpr64 = nofpexcept FMULv2f32 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FMULv2f32_]]
%2:fpr(<2 x s32>) = COPY $d1
%1:fpr(<2 x s32>) = COPY $d0
%0:fpr(<2 x s32>) = G_FMUL %1, %2
$noreg = PATCHABLE_RET %0(<2 x s32>)
...
---
name: test_rule1285_id910_at_idx84244
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%1' }
- { reg: '$q1', virtual-reg: '%2' }
body: |
bb.0.entry:
liveins: $q0, $q1
; CHECK-LABEL: name: test_rule1285_id910_at_idx84244
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[FMULv4f32_:%[0-9]+]]:fpr128 = nofpexcept FMULv4f32 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FMULv4f32_]]
%2:fpr(<4 x s32>) = COPY $q1
%1:fpr(<4 x s32>) = COPY $q0
%0:fpr(<4 x s32>) = G_FMUL %1, %2
$noreg = PATCHABLE_RET %0(<4 x s32>)
...
---
name: test_rule1286_id911_at_idx84287
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%1' }
- { reg: '$q1', virtual-reg: '%2' }
body: |
bb.0.entry:
liveins: $q0, $q1
; CHECK-LABEL: name: test_rule1286_id911_at_idx84287
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[FMULv2f64_:%[0-9]+]]:fpr128 = nofpexcept FMULv2f64 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FMULv2f64_]]
%2:fpr(<2 x s64>) = COPY $q1
%1:fpr(<2 x s64>) = COPY $q0
%0:fpr(<2 x s64>) = G_FMUL %1, %2
$noreg = PATCHABLE_RET %0(<2 x s64>)
...
---
name: test_rule1292_id924_at_idx84545
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
- { reg: '$d1', virtual-reg: '%2' }
body: |
bb.0.entry:
liveins: $d0, $d1
; CHECK-LABEL: name: test_rule1292_id924_at_idx84545
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[FSUBv2f32_:%[0-9]+]]:fpr64 = nofpexcept FSUBv2f32 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FSUBv2f32_]]
%2:fpr(<2 x s32>) = COPY $d1
%1:fpr(<2 x s32>) = COPY $d0
%0:fpr(<2 x s32>) = G_FSUB %1, %2
$noreg = PATCHABLE_RET %0(<2 x s32>)
...
---
name: test_rule1293_id925_at_idx84588
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%1' }
- { reg: '$q1', virtual-reg: '%2' }
body: |
bb.0.entry:
liveins: $q0, $q1
; CHECK-LABEL: name: test_rule1293_id925_at_idx84588
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[FSUBv4f32_:%[0-9]+]]:fpr128 = nofpexcept FSUBv4f32 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FSUBv4f32_]]
%2:fpr(<4 x s32>) = COPY $q1
%1:fpr(<4 x s32>) = COPY $q0
%0:fpr(<4 x s32>) = G_FSUB %1, %2
$noreg = PATCHABLE_RET %0(<4 x s32>)
...
---
name: test_rule1294_id926_at_idx84631
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%1' }
- { reg: '$q1', virtual-reg: '%2' }
body: |
bb.0.entry:
liveins: $q0, $q1
; CHECK-LABEL: name: test_rule1294_id926_at_idx84631
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[FSUBv2f64_:%[0-9]+]]:fpr128 = nofpexcept FSUBv2f64 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FSUBv2f64_]]
%2:fpr(<2 x s64>) = COPY $q1
%1:fpr(<2 x s64>) = COPY $q0
%0:fpr(<2 x s64>) = G_FSUB %1, %2
$noreg = PATCHABLE_RET %0(<2 x s64>)
...
---
name: test_rule1296_id939_at_idx84715
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
- { reg: '$d1', virtual-reg: '%2' }
body: |
bb.0.entry:
liveins: $d0, $d1
; CHECK-LABEL: name: test_rule1296_id939_at_idx84715
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[MULv8i8_:%[0-9]+]]:fpr64 = MULv8i8 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[MULv8i8_]]
%2:fpr(<8 x s8>) = COPY $d1
%1:fpr(<8 x s8>) = COPY $d0
%0:fpr(<8 x s8>) = G_MUL %1, %2
$noreg = PATCHABLE_RET %0(<8 x s8>)
...
---
name: test_rule1297_id940_at_idx84758
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%1' }
- { reg: '$q1', virtual-reg: '%2' }
body: |
bb.0.entry:
liveins: $q0, $q1
; CHECK-LABEL: name: test_rule1297_id940_at_idx84758
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[MULv16i8_:%[0-9]+]]:fpr128 = MULv16i8 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[MULv16i8_]]
%2:fpr(<16 x s8>) = COPY $q1
%1:fpr(<16 x s8>) = COPY $q0
%0:fpr(<16 x s8>) = G_MUL %1, %2
$noreg = PATCHABLE_RET %0(<16 x s8>)
...
---
name: test_rule1298_id941_at_idx84801
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
- { reg: '$d1', virtual-reg: '%2' }
body: |
bb.0.entry:
liveins: $d0, $d1
; CHECK-LABEL: name: test_rule1298_id941_at_idx84801
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[MULv4i16_:%[0-9]+]]:fpr64 = MULv4i16 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[MULv4i16_]]
%2:fpr(<4 x s16>) = COPY $d1
%1:fpr(<4 x s16>) = COPY $d0
%0:fpr(<4 x s16>) = G_MUL %1, %2
$noreg = PATCHABLE_RET %0(<4 x s16>)
...
---
name: test_rule1299_id942_at_idx84844
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%1' }
- { reg: '$q1', virtual-reg: '%2' }
body: |
bb.0.entry:
liveins: $q0, $q1
; CHECK-LABEL: name: test_rule1299_id942_at_idx84844
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[MULv8i16_:%[0-9]+]]:fpr128 = MULv8i16 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[MULv8i16_]]
%2:fpr(<8 x s16>) = COPY $q1
%1:fpr(<8 x s16>) = COPY $q0
%0:fpr(<8 x s16>) = G_MUL %1, %2
$noreg = PATCHABLE_RET %0(<8 x s16>)
...
---
name: test_rule1304_id1174_at_idx85055
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
- { reg: '$d1', virtual-reg: '%2' }
body: |
bb.0.entry:
liveins: $d0, $d1
; CHECK-LABEL: name: test_rule1304_id1174_at_idx85055
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[ORRv8i8_]]
%2:fpr(<8 x s8>) = COPY $d1
%1:fpr(<8 x s8>) = COPY $d0
%0:fpr(<8 x s8>) = G_OR %1, %2
$noreg = PATCHABLE_RET %0(<8 x s8>)
...
---
name: test_rule1305_id1175_at_idx85098
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%1' }
- { reg: '$q1', virtual-reg: '%2' }
body: |
bb.0.entry:
liveins: $q0, $q1
; CHECK-LABEL: name: test_rule1305_id1175_at_idx85098
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[ORRv16i8_:%[0-9]+]]:fpr128 = ORRv16i8 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[ORRv16i8_]]
%2:fpr(<16 x s8>) = COPY $q1
%1:fpr(<16 x s8>) = COPY $q0
%0:fpr(<16 x s8>) = G_OR %1, %2
$noreg = PATCHABLE_RET %0(<16 x s8>)
...
---
name: test_rule1306_id1827_at_idx85141
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
- { reg: '$d1', virtual-reg: '%2' }
body: |
bb.0.entry:
liveins: $d0, $d1
; CHECK-LABEL: name: test_rule1306_id1827_at_idx85141
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[ORRv8i8_]]
%2:fpr(<4 x s16>) = COPY $d1
%1:fpr(<4 x s16>) = COPY $d0
%0:fpr(<4 x s16>) = G_OR %1, %2
$noreg = PATCHABLE_RET %0(<4 x s16>)
...
---
name: test_rule1309_id1830_at_idx85270
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%1' }
- { reg: '$q1', virtual-reg: '%2' }
body: |
bb.0.entry:
liveins: $q0, $q1
; CHECK-LABEL: name: test_rule1309_id1830_at_idx85270
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[ORRv16i8_:%[0-9]+]]:fpr128 = ORRv16i8 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[ORRv16i8_]]
%2:fpr(<8 x s16>) = COPY $q1
%1:fpr(<8 x s16>) = COPY $q0
%0:fpr(<8 x s16>) = G_OR %1, %2
$noreg = PATCHABLE_RET %0(<8 x s16>)
...
---
name: test_rule1315_id1051_at_idx85522
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
- { reg: '$d1', virtual-reg: '%2' }
body: |
bb.0.entry:
liveins: $d0, $d1
; CHECK-LABEL: name: test_rule1315_id1051_at_idx85522
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[SUBv8i8_:%[0-9]+]]:fpr64 = SUBv8i8 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[SUBv8i8_]]
%2:fpr(<8 x s8>) = COPY $d1
%1:fpr(<8 x s8>) = COPY $d0
%0:fpr(<8 x s8>) = G_SUB %1, %2
$noreg = PATCHABLE_RET %0(<8 x s8>)
...
---
name: test_rule1316_id1052_at_idx85565
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%1' }
- { reg: '$q1', virtual-reg: '%2' }
body: |
bb.0.entry:
liveins: $q0, $q1
; CHECK-LABEL: name: test_rule1316_id1052_at_idx85565
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[SUBv16i8_:%[0-9]+]]:fpr128 = SUBv16i8 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[SUBv16i8_]]
%2:fpr(<16 x s8>) = COPY $q1
%1:fpr(<16 x s8>) = COPY $q0
%0:fpr(<16 x s8>) = G_SUB %1, %2
$noreg = PATCHABLE_RET %0(<16 x s8>)
...
---
name: test_rule1317_id1053_at_idx85608
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
- { reg: '$d1', virtual-reg: '%2' }
body: |
bb.0.entry:
liveins: $d0, $d1
; CHECK-LABEL: name: test_rule1317_id1053_at_idx85608
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[SUBv4i16_:%[0-9]+]]:fpr64 = SUBv4i16 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[SUBv4i16_]]
%2:fpr(<4 x s16>) = COPY $d1
%1:fpr(<4 x s16>) = COPY $d0
%0:fpr(<4 x s16>) = G_SUB %1, %2
$noreg = PATCHABLE_RET %0(<4 x s16>)
...
---
name: test_rule1318_id1054_at_idx85651
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%1' }
- { reg: '$q1', virtual-reg: '%2' }
body: |
bb.0.entry:
liveins: $q0, $q1
; CHECK-LABEL: name: test_rule1318_id1054_at_idx85651
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[SUBv8i16_:%[0-9]+]]:fpr128 = SUBv8i16 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[SUBv8i16_]]
%2:fpr(<8 x s16>) = COPY $q1
%1:fpr(<8 x s16>) = COPY $q0
%0:fpr(<8 x s16>) = G_SUB %1, %2
$noreg = PATCHABLE_RET %0(<8 x s16>)
...
---
name: test_rule1329_id1170_at_idx86118
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
- { reg: '$d1', virtual-reg: '%2' }
body: |
bb.0.entry:
liveins: $d0, $d1
; CHECK-LABEL: name: test_rule1329_id1170_at_idx86118
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[EORv8i8_:%[0-9]+]]:fpr64 = EORv8i8 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[EORv8i8_]]
%2:fpr(<8 x s8>) = COPY $d1
%1:fpr(<8 x s8>) = COPY $d0
%0:fpr(<8 x s8>) = G_XOR %1, %2
$noreg = PATCHABLE_RET %0(<8 x s8>)
...
---
name: test_rule1330_id1171_at_idx86161
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%1' }
- { reg: '$q1', virtual-reg: '%2' }
body: |
bb.0.entry:
liveins: $q0, $q1
; CHECK-LABEL: name: test_rule1330_id1171_at_idx86161
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[EORv16i8_:%[0-9]+]]:fpr128 = EORv16i8 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[EORv16i8_]]
%2:fpr(<16 x s8>) = COPY $q1
%1:fpr(<16 x s8>) = COPY $q0
%0:fpr(<16 x s8>) = G_XOR %1, %2
$noreg = PATCHABLE_RET %0(<16 x s8>)
...
---
name: test_rule1331_id1791_at_idx86204
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
- { reg: '$d1', virtual-reg: '%2' }
body: |
bb.0.entry:
liveins: $d0, $d1
; CHECK-LABEL: name: test_rule1331_id1791_at_idx86204
; CHECK: liveins: $d0, $d1
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d1
; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[EORv8i8_:%[0-9]+]]:fpr64 = EORv8i8 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[EORv8i8_]]
%2:fpr(<4 x s16>) = COPY $d1
%1:fpr(<4 x s16>) = COPY $d0
%0:fpr(<4 x s16>) = G_XOR %1, %2
$noreg = PATCHABLE_RET %0(<4 x s16>)
...
---
name: test_rule1334_id1794_at_idx86333
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
- { id: 2, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%1' }
- { reg: '$q1', virtual-reg: '%2' }
body: |
bb.0.entry:
liveins: $q0, $q1
; CHECK-LABEL: name: test_rule1334_id1794_at_idx86333
; CHECK: liveins: $q0, $q1
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q1
; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[EORv16i8_:%[0-9]+]]:fpr128 = EORv16i8 [[COPY1]], [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[EORv16i8_]]
%2:fpr(<8 x s16>) = COPY $q1
%1:fpr(<8 x s16>) = COPY $q0
%0:fpr(<8 x s16>) = G_XOR %1, %2
$noreg = PATCHABLE_RET %0(<8 x s16>)
...
---
name: test_rule1337_id2925_at_idx86462
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $d0
; CHECK-LABEL: name: test_rule1337_id2925_at_idx86462
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[USHLLv8i8_shift:%[0-9]+]]:fpr128 = USHLLv8i8_shift [[COPY]], 0
; CHECK: $noreg = PATCHABLE_RET [[USHLLv8i8_shift]]
%1:fpr(<8 x s8>) = COPY $d0
%0:fpr(<8 x s16>) = G_ANYEXT %1(<8 x s8>)
$noreg = PATCHABLE_RET %0(<8 x s16>)
...
---
name: test_rule1338_id2928_at_idx86507
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $d0
; CHECK-LABEL: name: test_rule1338_id2928_at_idx86507
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[USHLLv4i16_shift:%[0-9]+]]:fpr128 = USHLLv4i16_shift [[COPY]], 0
; CHECK: $noreg = PATCHABLE_RET [[USHLLv4i16_shift]]
%1:fpr(<4 x s16>) = COPY $d0
%0:fpr(<4 x s32>) = G_ANYEXT %1(<4 x s16>)
$noreg = PATCHABLE_RET %0(<4 x s32>)
...
---
name: test_rule1339_id2931_at_idx86552
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $d0
; CHECK-LABEL: name: test_rule1339_id2931_at_idx86552
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[USHLLv2i32_shift:%[0-9]+]]:fpr128 = USHLLv2i32_shift [[COPY]], 0
; CHECK: $noreg = PATCHABLE_RET [[USHLLv2i32_shift]]
%1:fpr(<2 x s32>) = COPY $d0
%0:fpr(<2 x s64>) = G_ANYEXT %1(<2 x s32>)
$noreg = PATCHABLE_RET %0(<2 x s64>)
...
---
name: test_rule1582_id372_at_idx97075
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$s0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $s0
; CHECK-LABEL: name: test_rule1582_id372_at_idx97075
; CHECK: liveins: $s0
; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
; CHECK: [[FNEGSr:%[0-9]+]]:fpr32 = FNEGSr [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FNEGSr]]
%1:fpr(s32) = COPY $s0
%0:fpr(s32) = G_FNEG %1
$noreg = PATCHABLE_RET %0(s32)
...
---
name: test_rule1583_id373_at_idx97110
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $d0
; CHECK-LABEL: name: test_rule1583_id373_at_idx97110
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[FNEGDr:%[0-9]+]]:fpr64 = FNEGDr [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FNEGDr]]
%1:fpr(s64) = COPY $d0
%0:fpr(s64) = G_FNEG %1
$noreg = PATCHABLE_RET %0(s64)
...
---
name: test_rule1586_id597_at_idx97215
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $d0
; CHECK-LABEL: name: test_rule1586_id597_at_idx97215
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[FNEGv2f32_:%[0-9]+]]:fpr64 = FNEGv2f32 [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FNEGv2f32_]]
%1:fpr(<2 x s32>) = COPY $d0
%0:fpr(<2 x s32>) = G_FNEG %1
$noreg = PATCHABLE_RET %0(<2 x s32>)
...
---
name: test_rule1587_id598_at_idx97250
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $q0
; CHECK-LABEL: name: test_rule1587_id598_at_idx97250
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[FNEGv4f32_:%[0-9]+]]:fpr128 = FNEGv4f32 [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FNEGv4f32_]]
%1:fpr(<4 x s32>) = COPY $q0
%0:fpr(<4 x s32>) = G_FNEG %1
$noreg = PATCHABLE_RET %0(<4 x s32>)
...
---
name: test_rule1588_id599_at_idx97285
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $q0
; CHECK-LABEL: name: test_rule1588_id599_at_idx97285
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[FNEGv2f64_:%[0-9]+]]:fpr128 = FNEGv2f64 [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FNEGv2f64_]]
%1:fpr(<2 x s64>) = COPY $q0
%0:fpr(<2 x s64>) = G_FNEG %1
$noreg = PATCHABLE_RET %0(<2 x s64>)
...
---
name: test_rule1592_id2383_at_idx97425
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $d0
; CHECK-LABEL: name: test_rule1592_id2383_at_idx97425
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[FCVTLv2i32_:%[0-9]+]]:fpr128 = nofpexcept FCVTLv2i32 [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FCVTLv2i32_]]
%1:fpr(<2 x s32>) = COPY $d0
%0:fpr(<2 x s64>) = G_FPEXT %1(<2 x s32>)
$noreg = PATCHABLE_RET %0(<2 x s64>)
...
---
name: test_rule1593_id2385_at_idx97458
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $d0
; CHECK-LABEL: name: test_rule1593_id2385_at_idx97458
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[FCVTLv4i16_:%[0-9]+]]:fpr128 = nofpexcept FCVTLv4i16 [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FCVTLv4i16_]]
%1:fpr(<4 x s16>) = COPY $d0
%0:fpr(<4 x s32>) = G_FPEXT %1(<4 x s16>)
$noreg = PATCHABLE_RET %0(<4 x s32>)
...
---
name: test_rule1602_id587_at_idx97771
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $d0
; CHECK-LABEL: name: test_rule1602_id587_at_idx97771
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[FCVTZSv2f32_:%[0-9]+]]:fpr64 = nofpexcept FCVTZSv2f32 [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FCVTZSv2f32_]]
%1:fpr(<2 x s32>) = COPY $d0
%0:fpr(<2 x s32>) = G_FPTOSI %1(<2 x s32>)
$noreg = PATCHABLE_RET %0(<2 x s32>)
...
---
name: test_rule1603_id588_at_idx97806
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $q0
; CHECK-LABEL: name: test_rule1603_id588_at_idx97806
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[FCVTZSv4f32_:%[0-9]+]]:fpr128 = nofpexcept FCVTZSv4f32 [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FCVTZSv4f32_]]
%1:fpr(<4 x s32>) = COPY $q0
%0:fpr(<4 x s32>) = G_FPTOSI %1(<4 x s32>)
$noreg = PATCHABLE_RET %0(<4 x s32>)
...
---
name: test_rule1604_id589_at_idx97841
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $q0
; CHECK-LABEL: name: test_rule1604_id589_at_idx97841
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[FCVTZSv2f64_:%[0-9]+]]:fpr128 = nofpexcept FCVTZSv2f64 [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FCVTZSv2f64_]]
%1:fpr(<2 x s64>) = COPY $q0
%0:fpr(<2 x s64>) = G_FPTOSI %1(<2 x s64>)
$noreg = PATCHABLE_RET %0(<2 x s64>)
...
---
name: test_rule1613_id592_at_idx98156
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $d0
; CHECK-LABEL: name: test_rule1613_id592_at_idx98156
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[FCVTZUv2f32_:%[0-9]+]]:fpr64 = nofpexcept FCVTZUv2f32 [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FCVTZUv2f32_]]
%1:fpr(<2 x s32>) = COPY $d0
%0:fpr(<2 x s32>) = G_FPTOUI %1(<2 x s32>)
$noreg = PATCHABLE_RET %0(<2 x s32>)
...
---
name: test_rule1614_id593_at_idx98191
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $q0
; CHECK-LABEL: name: test_rule1614_id593_at_idx98191
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[FCVTZUv4f32_:%[0-9]+]]:fpr128 = nofpexcept FCVTZUv4f32 [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FCVTZUv4f32_]]
%1:fpr(<4 x s32>) = COPY $q0
%0:fpr(<4 x s32>) = G_FPTOUI %1(<4 x s32>)
$noreg = PATCHABLE_RET %0(<4 x s32>)
...
---
name: test_rule1615_id594_at_idx98226
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $q0
; CHECK-LABEL: name: test_rule1615_id594_at_idx98226
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[FCVTZUv2f64_:%[0-9]+]]:fpr128 = nofpexcept FCVTZUv2f64 [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FCVTZUv2f64_]]
%1:fpr(<2 x s64>) = COPY $q0
%0:fpr(<2 x s64>) = G_FPTOUI %1(<2 x s64>)
$noreg = PATCHABLE_RET %0(<2 x s64>)
...
---
name: test_rule1619_id2389_at_idx98366
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $q0
; CHECK-LABEL: name: test_rule1619_id2389_at_idx98366
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[FCVTNv2i32_:%[0-9]+]]:fpr64 = nofpexcept FCVTNv2i32 [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FCVTNv2i32_]]
%1:fpr(<2 x s64>) = COPY $q0
%0:fpr(<2 x s32>) = G_FPTRUNC %1(<2 x s64>)
$noreg = PATCHABLE_RET %0(<2 x s32>)
...
---
name: test_rule1620_id2390_at_idx98399
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $q0
; CHECK-LABEL: name: test_rule1620_id2390_at_idx98399
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[FCVTNv4i16_:%[0-9]+]]:fpr64 = nofpexcept FCVTNv4i16 [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[FCVTNv4i16_]]
%1:fpr(<4 x s32>) = COPY $q0
%0:fpr(<4 x s16>) = G_FPTRUNC %1(<4 x s32>)
$noreg = PATCHABLE_RET %0(<4 x s16>)
...
---
name: test_rule1621_id2923_at_idx98432
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $d0
; CHECK-LABEL: name: test_rule1621_id2923_at_idx98432
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[SSHLLv8i8_shift:%[0-9]+]]:fpr128 = SSHLLv8i8_shift [[COPY]], 0
; CHECK: $noreg = PATCHABLE_RET [[SSHLLv8i8_shift]]
%1:fpr(<8 x s8>) = COPY $d0
%0:fpr(<8 x s16>) = G_SEXT %1(<8 x s8>)
$noreg = PATCHABLE_RET %0(<8 x s16>)
...
---
name: test_rule1622_id2926_at_idx98477
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $d0
; CHECK-LABEL: name: test_rule1622_id2926_at_idx98477
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[SSHLLv4i16_shift:%[0-9]+]]:fpr128 = SSHLLv4i16_shift [[COPY]], 0
; CHECK: $noreg = PATCHABLE_RET [[SSHLLv4i16_shift]]
%1:fpr(<4 x s16>) = COPY $d0
%0:fpr(<4 x s32>) = G_SEXT %1(<4 x s16>)
$noreg = PATCHABLE_RET %0(<4 x s32>)
...
---
name: test_rule1623_id2929_at_idx98522
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $d0
; CHECK-LABEL: name: test_rule1623_id2929_at_idx98522
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[SSHLLv2i32_shift:%[0-9]+]]:fpr128 = SSHLLv2i32_shift [[COPY]], 0
; CHECK: $noreg = PATCHABLE_RET [[SSHLLv2i32_shift]]
%1:fpr(<2 x s32>) = COPY $d0
%0:fpr(<2 x s64>) = G_SEXT %1(<2 x s32>)
$noreg = PATCHABLE_RET %0(<2 x s64>)
...
---
name: test_rule1632_id687_at_idx98847
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $d0
; CHECK-LABEL: name: test_rule1632_id687_at_idx98847
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[SCVTFv2f32_:%[0-9]+]]:fpr64 = nofpexcept SCVTFv2f32 [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[SCVTFv2f32_]]
%1:fpr(<2 x s32>) = COPY $d0
%0:fpr(<2 x s32>) = G_SITOFP %1(<2 x s32>)
$noreg = PATCHABLE_RET %0(<2 x s32>)
...
---
name: test_rule1633_id688_at_idx98882
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $q0
; CHECK-LABEL: name: test_rule1633_id688_at_idx98882
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[SCVTFv4f32_:%[0-9]+]]:fpr128 = nofpexcept SCVTFv4f32 [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[SCVTFv4f32_]]
%1:fpr(<4 x s32>) = COPY $q0
%0:fpr(<4 x s32>) = G_SITOFP %1(<4 x s32>)
$noreg = PATCHABLE_RET %0(<4 x s32>)
...
---
name: test_rule1634_id689_at_idx98917
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $q0
; CHECK-LABEL: name: test_rule1634_id689_at_idx98917
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[SCVTFv2f64_:%[0-9]+]]:fpr128 = nofpexcept SCVTFv2f64 [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[SCVTFv2f64_]]
%1:fpr(<2 x s64>) = COPY $q0
%0:fpr(<2 x s64>) = G_SITOFP %1(<2 x s64>)
$noreg = PATCHABLE_RET %0(<2 x s64>)
...
---
name: test_rule1635_id748_at_idx98952
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $q0
; CHECK-LABEL: name: test_rule1635_id748_at_idx98952
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[XTNv8i8_:%[0-9]+]]:fpr64 = XTNv8i8 [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[XTNv8i8_]]
%1:fpr(<8 x s16>) = COPY $q0
%0:fpr(<8 x s8>) = G_TRUNC %1(<8 x s16>)
$noreg = PATCHABLE_RET %0(<8 x s8>)
...
---
name: test_rule1636_id749_at_idx98987
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $q0
; CHECK-LABEL: name: test_rule1636_id749_at_idx98987
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[XTNv4i16_:%[0-9]+]]:fpr64 = XTNv4i16 [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[XTNv4i16_]]
%1:fpr(<4 x s32>) = COPY $q0
%0:fpr(<4 x s16>) = G_TRUNC %1(<4 x s32>)
$noreg = PATCHABLE_RET %0(<4 x s16>)
...
---
name: test_rule1637_id750_at_idx99022
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $q0
; CHECK-LABEL: name: test_rule1637_id750_at_idx99022
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[XTNv2i32_:%[0-9]+]]:fpr64 = XTNv2i32 [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[XTNv2i32_]]
%1:fpr(<2 x s64>) = COPY $q0
%0:fpr(<2 x s32>) = G_TRUNC %1(<2 x s64>)
$noreg = PATCHABLE_RET %0(<2 x s32>)
...
---
name: test_rule1647_id731_at_idx99386
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $d0
; CHECK-LABEL: name: test_rule1647_id731_at_idx99386
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[UCVTFv2f32_:%[0-9]+]]:fpr64 = nofpexcept UCVTFv2f32 [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[UCVTFv2f32_]]
%1:fpr(<2 x s32>) = COPY $d0
%0:fpr(<2 x s32>) = G_UITOFP %1(<2 x s32>)
$noreg = PATCHABLE_RET %0(<2 x s32>)
...
---
name: test_rule1648_id732_at_idx99421
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $q0
; CHECK-LABEL: name: test_rule1648_id732_at_idx99421
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[UCVTFv4f32_:%[0-9]+]]:fpr128 = nofpexcept UCVTFv4f32 [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[UCVTFv4f32_]]
%1:fpr(<4 x s32>) = COPY $q0
%0:fpr(<4 x s32>) = G_UITOFP %1(<4 x s32>)
$noreg = PATCHABLE_RET %0(<4 x s32>)
...
---
name: test_rule1649_id733_at_idx99456
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$q0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $q0
; CHECK-LABEL: name: test_rule1649_id733_at_idx99456
; CHECK: liveins: $q0
; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
; CHECK: [[UCVTFv2f64_:%[0-9]+]]:fpr128 = nofpexcept UCVTFv2f64 [[COPY]]
; CHECK: $noreg = PATCHABLE_RET [[UCVTFv2f64_]]
%1:fpr(<2 x s64>) = COPY $q0
%0:fpr(<2 x s64>) = G_UITOFP %1(<2 x s64>)
$noreg = PATCHABLE_RET %0(<2 x s64>)
...
---
name: test_rule1650_id2924_at_idx99491
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $d0
; CHECK-LABEL: name: test_rule1650_id2924_at_idx99491
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[USHLLv8i8_shift:%[0-9]+]]:fpr128 = USHLLv8i8_shift [[COPY]], 0
; CHECK: $noreg = PATCHABLE_RET [[USHLLv8i8_shift]]
%1:fpr(<8 x s8>) = COPY $d0
%0:fpr(<8 x s16>) = G_ZEXT %1(<8 x s8>)
$noreg = PATCHABLE_RET %0(<8 x s16>)
...
---
name: test_rule1651_id2927_at_idx99536
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $d0
; CHECK-LABEL: name: test_rule1651_id2927_at_idx99536
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[USHLLv4i16_shift:%[0-9]+]]:fpr128 = USHLLv4i16_shift [[COPY]], 0
; CHECK: $noreg = PATCHABLE_RET [[USHLLv4i16_shift]]
%1:fpr(<4 x s16>) = COPY $d0
%0:fpr(<4 x s32>) = G_ZEXT %1(<4 x s16>)
$noreg = PATCHABLE_RET %0(<4 x s32>)
...
---
name: test_rule1652_id2930_at_idx99581
alignment: 4
legalized: true
regBankSelected: true
tracksRegLiveness: true
registers:
- { id: 0, class: fpr }
- { id: 1, class: fpr }
liveins:
- { reg: '$d0', virtual-reg: '%1' }
body: |
bb.0.entry:
liveins: $d0
; CHECK-LABEL: name: test_rule1652_id2930_at_idx99581
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
; CHECK: [[USHLLv2i32_shift:%[0-9]+]]:fpr128 = USHLLv2i32_shift [[COPY]], 0
; CHECK: $noreg = PATCHABLE_RET [[USHLLv2i32_shift]]
%1:fpr(<2 x s32>) = COPY $d0
%0:fpr(<2 x s64>) = G_ZEXT %1(<2 x s32>)
$noreg = PATCHABLE_RET %0(<2 x s64>)
...