# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -march=amdgcn -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s --- name: test_add_rhs body: | bb.0: liveins: $vgpr0, $vgpr1 ; CHECK-LABEL: name: test_add_rhs ; CHECK: liveins: $vgpr0, $vgpr1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[COPY1]] ; CHECK-NEXT: $vgpr0 = COPY [[FSUB]](s32) %0:_(s32) = COPY $vgpr0 %1:_(s32) = COPY $vgpr1 %2:_(s32) = G_FNEG %1 %3:_(s32) = G_FADD %0, %2 $vgpr0 = COPY %3(s32) ... --- name: test_add_lhs body: | bb.0: liveins: $vgpr0, $vgpr1 ; CHECK-LABEL: name: test_add_lhs ; CHECK: liveins: $vgpr0, $vgpr1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY1]], [[COPY]] ; CHECK-NEXT: $vgpr0 = COPY [[FSUB]](s32) %0:_(s32) = COPY $vgpr0 %1:_(s32) = COPY $vgpr1 %2:_(s32) = G_FNEG %0 %3:_(s32) = G_FADD %2, %1 $vgpr0 = COPY %3(s32) ... --- name: test_sub body: | bb.0: liveins: $vgpr0, $vgpr1 ; CHECK-LABEL: name: test_sub ; CHECK: liveins: $vgpr0, $vgpr1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY]], [[COPY1]] ; CHECK-NEXT: $vgpr0 = COPY [[FADD]](s32) %0:_(s32) = COPY $vgpr0 %1:_(s32) = COPY $vgpr1 %2:_(s32) = G_FNEG %1 %3:_(s32) = G_FSUB %0, %2 $vgpr0 = COPY %3(s32) ... --- name: test_mul body: | bb.0: liveins: $vgpr0, $vgpr1 ; CHECK-LABEL: name: test_mul ; CHECK: liveins: $vgpr0, $vgpr1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[COPY1]] ; CHECK-NEXT: $vgpr0 = COPY [[FMUL]](s32) %0:_(s32) = COPY $vgpr0 %1:_(s32) = COPY $vgpr1 %2:_(s32) = G_FNEG %0 %3:_(s32) = G_FNEG %1 %4:_(s32) = G_FMUL %2, %3 $vgpr0 = COPY %4(s32) ... --- name: test_div body: | bb.0: liveins: $vgpr0, $vgpr1 ; CHECK-LABEL: name: test_div ; CHECK: liveins: $vgpr0, $vgpr1 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; CHECK-NEXT: [[FDIV:%[0-9]+]]:_(s32) = G_FDIV [[COPY]], [[COPY1]] ; CHECK-NEXT: $vgpr0 = COPY [[FDIV]](s32) %0:_(s32) = COPY $vgpr0 %1:_(s32) = COPY $vgpr1 %2:_(s32) = G_FNEG %0 %3:_(s32) = G_FNEG %1 %4:_(s32) = G_FDIV %2, %3 $vgpr0 = COPY %4(s32) ... --- name: test_fmad body: | bb.0: liveins: $vgpr0, $vgpr1, $vgpr2 ; CHECK-LABEL: name: test_fmad ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 ; CHECK-NEXT: [[FMAD:%[0-9]+]]:_(s32) = G_FMAD [[COPY]], [[COPY1]], [[COPY2]] ; CHECK-NEXT: $vgpr0 = COPY [[FMAD]](s32) %0:_(s32) = COPY $vgpr0 %1:_(s32) = COPY $vgpr1 %2:_(s32) = COPY $vgpr2 %3:_(s32) = G_FNEG %0 %4:_(s32) = G_FNEG %1 %5:_(s32) = G_FMAD %3, %4, %2 $vgpr0 = COPY %5(s32) ... --- name: test_fma body: | bb.0: liveins: $vgpr0, $vgpr1, $vgpr2 ; CHECK-LABEL: name: test_fma ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 ; CHECK-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[COPY]], [[COPY1]], [[COPY2]] ; CHECK-NEXT: $vgpr0 = COPY [[FMA]](s32) %0:_(s32) = COPY $vgpr0 %1:_(s32) = COPY $vgpr1 %2:_(s32) = COPY $vgpr2 %3:_(s32) = G_FNEG %0 %4:_(s32) = G_FNEG %1 %5:_(s32) = G_FMA %3, %4, %2 $vgpr0 = COPY %5(s32) ...