// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -no-opaque-pointers -triple riscv64 -target-feature +zbkx -emit-llvm %s -o - \
// RUN:     | FileCheck %s  -check-prefix=RV64ZBKX

// RV64ZBKX-LABEL: @xperm8(
// RV64ZBKX-NEXT:  entry:
// RV64ZBKX-NEXT:    [[RS1_ADDR:%.*]] = alloca i64, align 8
// RV64ZBKX-NEXT:    [[RS2_ADDR:%.*]] = alloca i64, align 8
// RV64ZBKX-NEXT:    store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
// RV64ZBKX-NEXT:    store i64 [[RS2:%.*]], i64* [[RS2_ADDR]], align 8
// RV64ZBKX-NEXT:    [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
// RV64ZBKX-NEXT:    [[TMP1:%.*]] = load i64, i64* [[RS2_ADDR]], align 8
// RV64ZBKX-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.xperm8.i64(i64 [[TMP0]], i64 [[TMP1]])
// RV64ZBKX-NEXT:    ret i64 [[TMP2]]
//
long xperm8(long rs1, long rs2)
{
  return __builtin_riscv_xperm8(rs1, rs2);
}

// RV64ZBKX-LABEL: @xperm4(
// RV64ZBKX-NEXT:  entry:
// RV64ZBKX-NEXT:    [[RS1_ADDR:%.*]] = alloca i64, align 8
// RV64ZBKX-NEXT:    [[RS2_ADDR:%.*]] = alloca i64, align 8
// RV64ZBKX-NEXT:    store i64 [[RS1:%.*]], i64* [[RS1_ADDR]], align 8
// RV64ZBKX-NEXT:    store i64 [[RS2:%.*]], i64* [[RS2_ADDR]], align 8
// RV64ZBKX-NEXT:    [[TMP0:%.*]] = load i64, i64* [[RS1_ADDR]], align 8
// RV64ZBKX-NEXT:    [[TMP1:%.*]] = load i64, i64* [[RS2_ADDR]], align 8
// RV64ZBKX-NEXT:    [[TMP2:%.*]] = call i64 @llvm.riscv.xperm4.i64(i64 [[TMP0]], i64 [[TMP1]])
// RV64ZBKX-NEXT:    ret i64 [[TMP2]]
//
long xperm4(long rs1, long rs2)
{
  return __builtin_riscv_xperm4(rs1, rs2);
}