# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=aarch64 -mcpu=cortex-a55 --all-views=false --summary-view --iterations=1000 < %s | FileCheck %s

# DIV is not modeled precisely: on hardware it takes variable
# number of cycles depending on its operands. LLVM scheduling model
# only provides an average latency.

add	w8, w8, #1
movz    w10, #1, lsl #16
movz    w12, #32768, lsl #16
mul	w11, w8, w8
sdiv	w10, w12, w10

# CHECK:      Iterations:        1000
# CHECK-NEXT: Instructions:      5000
# CHECK-NEXT: Total Cycles:      8004
# CHECK-NEXT: Total uOps:        5000

# CHECK:      Dispatch Width:    2
# CHECK-NEXT: uOps Per Cycle:    0.62
# CHECK-NEXT: IPC:               0.62
# CHECK-NEXT: Block RThroughput: 8.0