// SPDX-License-Identifier: CERN-OHL-S-2.0

// A basic SOC with the core, ram, and uart
// Default 32KiB ram

`default_nettype none
`timescale 1ps/1ps

module soc
(
    input   logic clk_i,
    input   logic rst_ni,

    input   logic uart_i,
    output  logic uart_o
);
    uart uart_impl(.clk_i, .rst_ni, .uart_i, .uart_o);

    soc_pkg::mem_in_t mem_in;
    soc_pkg::mem_out_t mem_out;

    mem ram(.clk_i, .core_i(mem_in), .core_o(mem_out));

    `ifndef SYNTHESIS
    initial begin
        if ($test$plusargs("trace") != 0) begin
            $display("[%0t] Tracing to logs/vlt_dump.vcd...\n", $time);
            $dumpfile("logs/vlt_dump.vcd");
            $dumpvars();
        end
    end
    `endif

endmodule