Refactor soc and core
Created by 8Cqo1QjSCQ3F66Vh3nan9N8dv1MjQSAEz8RNwt2cTacK on May 18, 2024, 1:33 AM
State:
NI3LA5WCMNMXAG3HMUQTKWU5CLHKYAN4AVC6E6SABF52JUXQBTQAC- rtl/regfile.sv
- rtl/soc.sv
- rtl/basic_rv32i.sv
- rtl/mem.sv
- rtl/soc
- rtl/soc/uart.sv
- rtl/soc/soc_pkg.sv
- rtl/soc/soc.sv
5 more files
- rtl/soc/mem.sv
- rtl/core
- rtl/core/core_pkg.sv
- README.md
- Makefile
Implemented register file and created skeleton for basic core
Created by 8Cqo1QjSCQ3F66Vh3nan9N8dv1MjQSAEz8RNwt2cTacK on May 15, 2024, 5:15 AM
State:
5GVTHJ6RTEZ5KV4AWEGXBASR7EBRO7AUN67UZUGEOTX47RZN6IHAC- rtl/soc.sv
- rtl/regfile.sv
- rtl/mem.sv
- rtl/basic_rv32i.sv
Factored out memory interface
Created by 8Cqo1QjSCQ3F66Vh3nan9N8dv1MjQSAEz8RNwt2cTacK on May 15, 2024, 4:49 AM
State:
X4K5QXNHDGNJNVGPYMU6KMLQV5SE4SKPAQUBTFTJXDYNDYMUXNDAC- rtl/soc.sv
- rtl/mem.sv
- Makefile
Focus on the hardware design by dropping alternative HDLS for Verilog
Created by 8Cqo1QjSCQ3F66Vh3nan9N8dv1MjQSAEz8RNwt2cTacK on May 15, 2024, 3:37 AM
State:
HDH6SKT3OMEPEEC5JAONOOKG4QEGLR4MPJYBBRMRIFJBFWVLLQNAC- swim.toml
- src
- src/main.spade
- swim.lock
- rtl
- rtl/soc.sv
- README.md
- Makefile
1 more file
- .ignore
Add swim lockfile
Created by 8Cqo1QjSCQ3F66Vh3nan9N8dv1MjQSAEz8RNwt2cTacK on May 10, 2024, 11:17 PM
State:
TZLMNKK3LF3OXUZUE6QMXPWPE732EGOLOPI46WPET4VX5XCCC7GAC- swim.lock
Add SPDX License
Created by 8Cqo1QjSCQ3F66Vh3nan9N8dv1MjQSAEz8RNwt2cTacK on May 10, 2024, 11:15 PM
State:
6LIANER4V6H7I4HXTBZH5VZXJYAT4X6JS42YY2NB2ZQLF7UTF2EQC- swim.toml
- src/main.spade
- COPYING
Create spade project
Created by 8Cqo1QjSCQ3F66Vh3nan9N8dv1MjQSAEz8RNwt2cTacK on May 10, 2024, 10:42 PM
State:
6OQ2HLPYRWZJVHY3VN2AI4NHJMZLZG52RDWHD55PGINKEN2T6OHQC- swim.toml
- src
- src/main.spade
- .ignore
State:
5NUGJYYZD3XYGUDKNQ54Q4U24OHFHDNY2A4V6BDG6APP7EGC5PGQC