Refactor soc and core
Created by 8Cqo1QjSCQ3F66Vh3nan9N8dv1MjQSAEz8RNwt2cTacK on May 18, 2024, 1:33 AM
State:
NI3LA5WCMNMXAG3HMUQTKWU5CLHKYAN4AVC6E6SABF52JUXQBTQACImplemented register file and created skeleton for basic core
Created by 8Cqo1QjSCQ3F66Vh3nan9N8dv1MjQSAEz8RNwt2cTacK on May 15, 2024, 5:15 AM
State:
5GVTHJ6RTEZ5KV4AWEGXBASR7EBRO7AUN67UZUGEOTX47RZN6IHACFactored out memory interface
Created by 8Cqo1QjSCQ3F66Vh3nan9N8dv1MjQSAEz8RNwt2cTacK on May 15, 2024, 4:49 AM
State:
X4K5QXNHDGNJNVGPYMU6KMLQV5SE4SKPAQUBTFTJXDYNDYMUXNDACFocus on the hardware design by dropping alternative HDLS for Verilog
Created by 8Cqo1QjSCQ3F66Vh3nan9N8dv1MjQSAEz8RNwt2cTacK on May 15, 2024, 3:37 AM
State:
HDH6SKT3OMEPEEC5JAONOOKG4QEGLR4MPJYBBRMRIFJBFWVLLQNACAdd swim lockfile
Created by 8Cqo1QjSCQ3F66Vh3nan9N8dv1MjQSAEz8RNwt2cTacK on May 10, 2024, 11:17 PM
State:
TZLMNKK3LF3OXUZUE6QMXPWPE732EGOLOPI46WPET4VX5XCCC7GACAdd SPDX License
Created by 8Cqo1QjSCQ3F66Vh3nan9N8dv1MjQSAEz8RNwt2cTacK on May 10, 2024, 11:15 PM
State:
6LIANER4V6H7I4HXTBZH5VZXJYAT4X6JS42YY2NB2ZQLF7UTF2EQCCreate spade project
Created by 8Cqo1QjSCQ3F66Vh3nan9N8dv1MjQSAEz8RNwt2cTacK on May 10, 2024, 10:42 PM
State:
6OQ2HLPYRWZJVHY3VN2AI4NHJMZLZG52RDWHD55PGINKEN2T6OHQCState:
5NUGJYYZD3XYGUDKNQ54Q4U24OHFHDNY2A4V6BDG6APP7EGC5PGQC